Commit Graph

170113 Commits

Author SHA1 Message Date
Craig Topper 4e511d4c19 [X86][Disassembler] Add bizarro versions of the MOVSXD instruction that sign extend from a GR32 to GR32 or GR16.
The 0x63 opcodes in 64-bit mode have a fixed source size of 32-bits, but the destination size is controlled by REX.W and the 0x66 opsize prefix. This instruction is normally used with a REX.W prefix which provides desired behavior. The other encodings are interpretted as valid by the processor, but aren't useful.

This patch makes us recognize them for the disassembler to match objdump.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343614 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-02 18:16:19 +00:00
Daniel Sanders 8f3aebf19b [globalisel][verifier] Run the MachineVerifier from IRTranslator onwards
-verify-machineinstrs inserts the MachineVerifier after every MachineInstr-based
pass. However, GlobalISel creates MachineInstr-based passes earlier than DAGISel
and the corresponding verifiers are not being added. This patch fixes that.

If GlobalISel triggers the fallback path then the MIR can be left in a bad
state that is going to be cleared by ResetMachineFunctions. In this situation
verifying between GlobalISel passes will prevent the fallback path from
recovering from this. As a result, we bail out of verifying a function if the
FailedISel attribute is present.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343613 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-02 17:56:58 +00:00
Reid Kleckner a507425e00 [codeview] Fix 32-bit x86 variable locations in realigned stack frames
Add the .cv_fpo_stackalign directive so that we can define $T0, or the
VFRAME virtual register, with it. This was overlooked in the initial
implementation because unlike MSVC, we push CSRs before allocating stack
space, so this value is only needed to describe local variable
locations. Variables that the compiler now addresses via ESP are instead
described as being stored at offsets from VFRAME, which for us is ESP
after alignment in the prologue.

This adds tests that show that we use the VFRAME register properly in
our S_DEFRANGE records, and that we emit the correct FPO data to define
it.

Fixes PR38857

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343603 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-02 16:43:52 +00:00
Simon Pilgrim 2e34e6d02b [X86][Btver2] Fix BLENDV and AESDEC schedules
Match AMD Fam16h SOG + llvm-exegesis tests

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343597 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-02 15:13:18 +00:00
Krzysztof Parzyszek 4cd3487f7f [Hexagon] Fix extracting subvectors of non-HVX vNi1
Patch by Brendon Cahoon.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343596 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-02 15:05:43 +00:00
Sanjay Patel 1b9f2a9da5 [InstCombine] add tests with undef elements; NFC
See discussion in D52747.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343595 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-02 15:00:56 +00:00
Diogo N. Sampaio f646df2dd3 [ARM] Emmit data symbol for constant pool data
The ARM elf emitter would omit printing data
symbol when constant data. This patch
overrides the emitFill method as to enforce that
the symbol is correctly printed.

Differential revision: https://reviews.llvm.org/D52737



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343594 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-02 14:55:48 +00:00
Roman Lebedev fc829e82f6 [NFC][CodeGen][X86] fma.ll, lwp-intrinsics.ll: actually spell --check-prefixes correctly :/
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343588 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-02 13:34:50 +00:00
Sanjay Patel cbe63a8c2b [InstCombine] add more insert/extract vector tests with FP types; NFC
These are candidates for the same fold that was implemented in
D52439, but FP types require bitcasting (and that changes the
extra uses profitability calculation).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343587 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-02 13:34:05 +00:00
Simon Pilgrim 68276e8ffb [X86] Remove unnecessary BT(C/R/S)m(i/r) scheduler overrides
Some SchedAlias remain due to some badly setup RMW tags - but at least the overrides are all removed

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343586 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-02 13:11:59 +00:00
Roman Lebedev 67253e401e [NFC][CodeGen][X86] lwp-intrinsics.ll: fix check prefixes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343585 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-02 13:11:08 +00:00
Roman Lebedev d3241c7821 [NFC][CodeGen][X86] fma.ll: fix check prefixes for -mcpu=bdver2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343584 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-02 13:10:55 +00:00
Simon Pilgrim 2c248c1213 [X86] Add APInt constant assembly printer helper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343577 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-02 11:32:33 +00:00
Oliver Stannard 08e636c3eb [AArch64][v8.5A] Add Memory Tagging instructions
This adds new instructions to manipluate tagged pointers, and to load
and store the tags associated with memory.

Patch by Pablo Barrio, David Spickett and Oliver Stannard!

Differential revision: https://reviews.llvm.org/D52490



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343572 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-02 10:04:39 +00:00
Oliver Stannard cc07c6d050 [AArch64][v8.5A] Add Memory Tagging system registers
This adds new system registers introduced by the Memory Tagging
extension.

Patch by Pablo Barrio!

Differential revision: https://reviews.llvm.org/D52488



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343571 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-02 09:54:35 +00:00
Oliver Stannard ea81843dbd [AArch64][v8.5A] Add MTE system instructions
The Memory Tagging Extension adds system instructions for data cache
maintenance, implemented as new operands to the DC instruction.

Patch by Pablo Barrio!

Differential revision: https://reviews.llvm.org/D52487



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343570 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-02 09:48:43 +00:00
David Green cf1b18658c [InstCombine] Fold ~A - Min/Max(~A, O) -> Max/Min(A, ~O) - A
This is an attempt to get out of a local-minimum that instcombine currently
gets stuck in. We essentially combine two optimisations at once, ~a - ~b = b-a
and min(~a, ~b) = ~max(a, b), only doing the transform if the result is at
least neutral. This involves using IsFreeToInvert, which has been expanded a
little to include selects that can be easily inverted.

This is trying to fix PR35875, using the ideas from Sanjay. It is a large
improvement to one of our rgb to cmy kernels.

Differential Revision: https://reviews.llvm.org/D52177


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343569 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-02 09:48:34 +00:00
Oliver Stannard 637450a7f2 [AArch64][v8.5A] Add MTE as an optional AArch64 extension
This adds the memory tagging extension, which is an optional extension
introduced in v8.5A. The new instructions and registers will be added by
subsequent patches.

Patch by Pablo Barrio!

Differential revision: https://reviews.llvm.org/D52486



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343563 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-02 09:36:28 +00:00
Simon Pilgrim 16b860b6ae [X86] Standardize floating point assembly comments
Consistently try to use APFloat::toString for floating point constant comments to get rid of differences between Constant / ConstantDataSequential values - it should help stop some of the linux-windows buildbot failures matching NaN/INF etc. as well.

Differential Revision: https://reviews.llvm.org/D52702

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343562 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-02 09:08:51 +00:00
David Green abe8e0a65f [InstCombine] Tests for ~A - Min/Max(~A, O) -> Max/Min(A, ~O) - A. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343561 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-02 09:06:49 +00:00
Matt Arsenault b3a02e1925 AMDGPU: Expand atomicrmw nand in IR
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343559 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-02 03:50:56 +00:00
Thomas Lively 73aeabb0f0 [WebAssembly] Restore slashes in SIMD conversion names
Summary: Depends on D52372 and D52442.

Reviewers: aheejin, dschuff, aardappel

Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D52512

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343558 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-02 01:52:21 +00:00
Owen Rodley 0dc07911df [MCA] Remove SM.hasNext() call in FetchStage::execute.
Summary:
This is redundant, as FetchStage::getNextInstruction already checks this
and returns llvm::ErrorSuccess() as appropriate.

NFC.

Reviewers: andreadb

Subscribers: gbedwell, llvm-commits

Differential Revision: https://reviews.llvm.org/D52642

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343555 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-02 00:40:08 +00:00
Fangrui Song 8ffa63b4d5 [AArch64][DAGCombiner]: change -stop-after=isel to instruction-select
"isel" is registered by AMDGPU. The test will break if the AMDGPU target
is not built.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343553 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-02 00:22:51 +00:00
Craig Topper 2982360e7a [SimplifyCFG] Use Value::hasNUses instead of 'getNumUses() =='. NFCI
getNumUses is linear in the number of uses. Since we're looking for a specific use count, we can use hasNUses which will stop as soon as it determines there are more than N uses instead of walking all of them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343550 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-01 23:09:52 +00:00
Matt Davis 9aca4e8d36 [llvm-mca] Rename the 'Subtract' method to 'subtract'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343549 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-01 23:01:45 +00:00
Craig Topper e9e1c785d6 [SimplifyCFG] Update comments that refer to CondBB to say ThenBB instead. NFC
There is no variable in this function named CondBB, but there is one named ThenBB and I believe the comments are all refering to it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343548 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-01 22:56:11 +00:00
Zachary Turner 5877e4ed63 [PDB] Add support for more kinds of PDB Sym Tags.
DIA SDK is returning several new sym tag types, so we update
the enumeration and printing code to support these.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343547 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-01 22:39:19 +00:00
Daniel Sanders d31f3f6227 Revert: r343521 and r343541: [globalisel] Add a combiner helpers for extending loads and use them in a pre-legalize combiner for AArch64
There's a strange assertion on two of the Green Dragon bots that goes away when
this is reverted. The assertion is in RegBankAlloc and if it is this commit then
-verify-machine-instrs should have caught it earlier in the pipeline.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343546 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-01 22:32:08 +00:00
Reid Kleckner 9c94c5fb80 [codeview] Simplify S_DEFRANGE emission code, NFC
These assembler directives are still pretty unreadable and it would be
nice to clean them up at some point.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343544 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-01 22:25:49 +00:00
Reid Kleckner 6d4c271eeb [codeview] Emit S_FRAMEPROC and use S_DEFRANGE_FRAMEPOINTER_REL
Summary:
Before this change, LLVM would always describe locals on the stack as
being relative to some specific register, RSP, ESP, EBP, ESI, etc.
Variables in stack memory are pretty common, so there is a special
S_DEFRANGE_FRAMEPOINTER_REL symbol for them. This change uses it to
reduce the size of our debug info.

On top of the size savings, there are cases on 32-bit x86 where local
variables are addressed from ESP, but ESP changes across the function.
Unlike in DWARF, there is no FPO data to describe the stack adjustments
made to push arguments onto the stack and pop them off after the call,
which makes it hard for the debugger to find the local variables in
frames further up the stack.

To handle this, CodeView has a special VFRAME register, which
corresponds to the $T0 variable set by our FPO data in 32-bit.  Offsets
to local variables are instead relative to this value.

This is part of PR38857.

Reviewers: hans, zturner, javed.absar

Subscribers: aprantl, hiraditya, JDevlieghere, llvm-commits

Differential Revision: https://reviews.llvm.org/D52217

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343543 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-01 21:59:45 +00:00
Reid Kleckner 02b91a8b77 Fix the Windows build in GlobalISel
Clang-cl was complaining about some sort of constexpr narrowing bug:

C:\src\llvm-project\llvm\lib\CodeGen\GlobalISel\CombinerHelper.cpp(136,31):  error: non-constant-expression cannot be narrowed from type 'llvm::TargetOpcode::(anonymous enum at C:\src\llvm-project\llvm\include\llvm/CodeGen/TargetOpcodes.h:22:1)' to 'unsigned int' in initializer list [-Wc++11-narrowing]
                              unsigned(MI.getOpcode()) == unsigned(TargetOpcode::G_LOAD)
                              ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
C:\src\llvm-project\llvm\lib\CodeGen\GlobalISel\CombinerHelper.cpp(136,31):  note: insert an explicit cast to silence this issue
                              unsigned(MI.getOpcode()) == unsigned(TargetOpcode::G_LOAD)
                              ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
                              static_cast<unsigned int>(

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343541 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-01 21:39:39 +00:00
Craig Topper d8de965221 Recommit r343499 "[X86] Enable load folding in the test shrinking code"
Original message:
This patch adds load folding support to the test shrinking code. This was noticed missing in the review for D52669

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343540 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-01 21:35:28 +00:00
Craig Topper 6ba8c38c50 Recommit r343498 "[X86] Improve test instruction shrinking when the sign flag is used and the output of the and is truncated."
This includes a fix to prevent i16 compares with i32/i64 ands from being shrunk if bit 15 of the and is set and the sign bit is used.

Original commit message:
Currently we skip looking through truncates if the sign flag is used. But that's overly restrictive.

It's safe to look through the truncate as long as we ensure one of the 3 things when we shrink. Either the MSB of the mask at the shrunken size isn't set. If the mask bit is set then either the shrunk size needs to be equal to the compare size or the sign

There are still missed opportunities to shrink a load and fold it in here. This will be fixed in a future patch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343539 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-01 21:35:26 +00:00
Sanjay Patel e467ad47ea [InstCombine] add inverse test for vector trunc canonical form; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343529 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-01 20:25:49 +00:00
Sanjay Patel aba2e4f005 [InstCombine] regenerate test checks; NFC
These files used an old version of the script.
We regex more now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343527 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-01 20:22:28 +00:00
Stefan Pintilie e957cca256 [PowerPC] Folding XForm to DForm loads requires alignment for some DForm loads.
Going from XForm Load to DSForm Load requires that the immediate be 4 byte
aligned.
If we are not aligned we must leave the load as LDX (XForm).
This bug is causing a compile-time failure in the benchmark h264ref.

Differential Revision: https://reviews.llvm.org/D51988

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343525 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-01 20:16:27 +00:00
Eric Christopher 2f73099e90 Temporarily revert "[GVNHoist] Re-enable GVNHoist by default"
This reverts commit r342387 as it's showing significant performance
regressions in a number of benchmarks. Followed up with the
committer and original thread with an example and will get performance
numbers before recommitting.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343522 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-01 18:57:08 +00:00
Daniel Sanders 55eda328c5 [globalisel] Add a combiner helpers for extending loads and use them in a pre-legalize combiner for AArch64
Summary: Depends on D45541

Reviewers: ab, aditya_nandakumar, bogner, rtereshin, volkan, rovka, javed.absar, aemerson

Subscribers: aemerson, rengolin, mgorny, javed.absar, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D45543

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343521 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-01 18:56:47 +00:00
Matthias Braun 79816c8fee X86, AArch64, ARM: Do not attach debug location to spill/reload instructions
Spill/reload instructions are artificially generated by the compiler and
have no relation to the original source code. So the best thing to do is
not attach any debug location to them (instead of just taking the next
debug location we find on following instructions).

Differential Revision: https://reviews.llvm.org/D52125

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343520 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-01 18:56:39 +00:00
Craig Topper f6d7cdc06b [X86] Add more test shrinking with truncate and sign bit usage tests. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343519 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-01 18:52:19 +00:00
Craig Topper 5c1f4358a9 Revert r343499 and r343498. X86 test improvements
There's a subtle bug in the handling of truncate from i32/i64 to i32 without minsize.

I'll be adding more test cases and trying to find a fix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343516 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-01 18:40:44 +00:00
Krzysztof Parzyszek beae29ccd4 [Hexagon] Remove incorrect pattern for swiz
The pattern had a couple of problems:
- It was checking for loads of bytes in the reverse order to what it
  should have been looking for.
- It would replace loads of bytes with a load of a word without making
  sure that the alignment was correct.

Thanks to Eli Friedman for pointing it out.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343514 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-01 18:24:40 +00:00
Stanislav Mekhanoshin cdda304902 [AMDGPU] Fixed SIInstrInfo::getOpSize to handle subregs
Currently it returns incorrect operand size for a target independet
node such as COPY if operand is a register with subreg. Instead of
correct subreg size it returns a size of the whole superreg.

Differential Revision: https://reviews.llvm.org/D52736

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343508 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-01 18:00:02 +00:00
Zachary Turner b47810926d [PDB] Add support for dumping Typedef records.
These work a little differently because they are actually in
the globals stream and are treated as symbol records, even though
DIA presents them as types.  So this also adds the necessary
infrastructure to cache records that live somewhere other than
the TPI stream as well.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343507 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-01 17:55:38 +00:00
Zachary Turner a93560b336 [PDB] Add support for parsing VFTable Shape records.
This allows them to be returned from the native API.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343506 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-01 17:55:16 +00:00
Matthias Braun 429bce6ae9 MIRParser: Check that instructions only reference DILocation metadata
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343505 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-01 17:50:52 +00:00
Wouter van Oortmerssen 2e04af78a2 [WebAssembly] Fixed AsmParser not allowing instructions with /
Summary:
The AsmParser Lexer regards these as a seperate token.
Here we expand the instruction name with them if they are
adjacent (no whitespace).

Tested: the basic-assembly.s test case has one case with a / in it.
The currently are also instructions with : in them, which we intend
to rename rather than fix them here.

Reviewers: tlively, dschuff

Subscribers: sbc100, jgravelle-google, aheejin, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D52442

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343501 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-01 17:20:31 +00:00
Craig Topper f0bd8cc308 [X86] Enable load folding in the test shrinking code
This patch adds load folding support to the test shrinking code. This was noticed missing in the review for D52669

Differential Revision: https://reviews.llvm.org/D52699

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343499 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-01 17:10:50 +00:00
Craig Topper b023cfc60d [X86] Improve test instruction shrinking when the sign flag is used and the output of the and is truncated
Currently we skip looking through truncates if the sign flag is used. But that's overly restrictive.

It's safe to look through the truncate as long as we ensure one of the 3 things when we shrink. Either the MSB of the mask at the shrunken size isn't set. If the mask bit is set then either the shrunk size needs to be equal to the compare size or the sign flag needs to be unused.

There are still missed opportunities to shrink a load and fold it in here. This will be fixed in a future patch.

Differential Revision: https://reviews.llvm.org/D52669

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343498 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-01 17:10:45 +00:00