Commit Graph

186931 Commits

Author SHA1 Message Date
David Green
32893f0502 [ARM] Lower sadd_sat to qadd8 and qadd16
Lower the target independent signed saturating intrinsics to qadd8 and qadd16.
This custom lowers them from a sadd_sat, catching the node early before it is
promoted. It also adds a QADD8b and QADD16b node to mean the bottom "lane" of a
qadd8/qadd16, so that we can call demand bits on it to show that it does not
use the upper bits.

Also handles QSUB8 and QSUB16.

Differential Revision: https://reviews.llvm.org/D68974


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375402 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-21 09:53:38 +00:00
David Green
7f7fc30ded [ARM] Add and adjust saturation tests for upcoming qadd changes. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375401 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-21 09:43:37 +00:00
Guillaume Chatelet
2bcdb486dd Use Align for TFL::TransientStackAlignment
Summary:
This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790

Reviewers: courbet

Subscribers: arsenm, dschuff, jyknight, sdardis, jvesely, nhaehnle, sbc100, jgravelle-google, hiraditya, aheejin, fedor.sergeev, jrtc27, atanasyan, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D69216

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375398 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-21 08:31:25 +00:00
Roman Lebedev
475d7dd7ac [NFC][InstCombine] Fixup comments
As noted in post-commit review of rL375378375378.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375397 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-21 08:21:54 +00:00
Roman Lebedev
3ddad0b0b1 [CVP] Deduce no-wrap on mul
Summary:
`ConstantRange::makeGuaranteedNoWrapRegion()` knows how to deal with `mul`
since rL335646, there is exhaustive test coverage.
This is already used by CVP's `processOverflowIntrinsic()`,
and by SCEV's `StrengthenNoWrapFlags()`

That being said, currently, this doesn't help much in the end:
| statistic                              |     old |     new | delta | percentage |
| correlated-value-propagation.NumMulNSW |       4 |     275 |   271 |   6775.00% |
| correlated-value-propagation.NumMulNUW |       4 |    1323 |  1319 |  32975.00% |
| correlated-value-propagation.NumMulNW  |       8 |    1598 |  1590 |  19875.00% |
| correlated-value-propagation.NumNSW    |    5715 |    5986 |   271 |      4.74% |
| correlated-value-propagation.NumNUW    |    9193 |   10512 |  1319 |     14.35% |
| correlated-value-propagation.NumNW     |   14908 |   16498 |  1590 |     10.67% |
| instcount.NumAddInst                   |  275871 |  275869 |    -2 |      0.00% |
| instcount.NumBrInst                    |  708234 |  708232 |    -2 |      0.00% |
| instcount.NumMulInst                   |   43812 |   43810 |    -2 |      0.00% |
| instcount.NumPHIInst                   |  316786 |  316784 |    -2 |      0.00% |
| instcount.NumTruncInst                 |   62165 |   62167 |     2 |      0.00% |
| instcount.NumUDivInst                  |    2528 |    2526 |    -2 |     -0.08% |
| instcount.TotalBlocks                  |  842995 |  842993 |    -2 |      0.00% |
| instcount.TotalInsts                   | 7376486 | 7376478 |    -8 |      0.00% |
(^ test-suite plain, tests still pass)

Reviewers: nikic, reames, luqmana, sanjoy, timshen

Reviewed By: reames

Subscribers: hiraditya, javed.absar, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D69203

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375396 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-21 08:21:44 +00:00
Piotr Sobczak
ec10cb25d9 [InstCombine] Allow values with multiple users in SimplifyDemandedVectorElts
Summary:
Allow for ignoring the check for a single use in SimplifyDemandedVectorElts
to be able to simplify operands if DemandedElts is known to contain
the union of elements used by all users.
It is a responsibility of a caller of SimplifyDemandedVectorElts to
supply correct DemandedElts.

Simplify a series of extractelement instructions if only a subset of
elements is used.

Reviewers: reames, arsenm, majnemer, nhaehnle

Reviewed By: nhaehnle

Subscribers: wdng, jvesely, nhaehnle, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D67345

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375395 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-21 08:12:47 +00:00
GN Sync Bot
919bed3ee7 gn build: Merge r375390
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375393 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-21 08:06:38 +00:00
Martin Storsjo
9cc8630a80 [LLDB] [Windows] Initial support for ARM register contexts
Differential Revision: https://reviews.llvm.org/D69226

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375392 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-21 08:02:34 +00:00
Yevgeny Rouban
53fb41197c [IR] Fix mayReadFromMemory() for writeonly calls
Current implementation of Instruction::mayReadFromMemory()
returns !doesNotAccessMemory() which is !ReadNone. This
does not take into account that the writeonly attribute
also indicates that the call does not read from memory.

The patch changes the predicate to !doesNotReadMemory()
that reflects the intended behavior.

Differential Revision: https://reviews.llvm.org/D69086

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375389 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-21 06:52:08 +00:00
Yonghong Song
adc79ba5db [BPF] fix indirect call assembly code
Currently, for indirect call, the assembly code printed out as
  callx <imm>
This is not right, it should be
  callx <reg>

Fixed the issue with proper format.

Differential Revision: https://reviews.llvm.org/D69229

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375386 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-21 03:22:03 +00:00
Johannes Doerfert
cd2c099476 [Attributor][FIX] Silence sign-compare warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375384 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-21 01:29:10 +00:00
Johannes Doerfert
463d8212b2 [Attributor] Teach AANoCapture to use information in-flight more aggressively
AAReturnedValues, AAMemoryBehavior, and AANoUnwind, can provide
information that helps during the tracking or even justifies no-capture.
We now use this information and enable no-capture in some test cases
designed a long while a ago for these cases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375382 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-21 00:48:42 +00:00
Craig Topper
f5c1edb2b9 [X86] Check Subtarget.hasSSE3() before calling shouldUseHorizontalOp and emitting X86ISD::FHADD in LowerUINT_TO_FP_i64.
This was a regression from r375341.

Fixes PR43729.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375381 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-20 23:54:19 +00:00
Philip Reames
d1d5cb7698 [IndVars] Add a todo to reflect a further oppurtunity identified in D69009
Nikita pointed out an oppurtunity, might as well document it in the code.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375380 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-20 23:44:01 +00:00
Philip Reames
9efd72ad02 [IndVars] Eliminate loop exits with equivalent exit counts
We can end up with two loop exits whose exit counts are equivalent, but whose textual representation is different and non-obvious. For the sub-case where we have a series of exits which dominate one another (common), eliminate any exits which would iterate *after* a previous exit on the exiting iteration.

As noted in the TODO being removed, I'd always thought this was a good idea, but I've now seen this in a real workload as well.

Interestingly, in review, Nikita pointed out there's let another oppurtunity to leverage SCEV's reasoning.  If we kept track of the min of dominanting exits so far, we could discharge exits with EC >= MDE.  This is less powerful than the existing transform (since later exits aren't considered), but potentially more powerful for any case where SCEV can prove a >= b, but neither a == b or a > b.  I don't have an example to illustrate that oppurtunity, but won't be suprised if we find one and return to handle that case as well.  

Differential Revision: https://reviews.llvm.org/D69009



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375379 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-20 23:38:02 +00:00
Roman Lebedev
b93a52f5fe [InstCombine] conditional sign-extend of high-bit-extract: 'or' pattern.
In this pattern, all the "magic" bits that we'd `add` are all
high sign bits, and in the value we'd be adding to they are all unset,
not unexpectedly, so we can have an `or` there:
https://rise4fun.com/Alive/ups

It is possible that `haveNoCommonBitsSet()` should be taught about this
pattern so that we never have an `add` variant, but the reasoning would
need to be recursive (because of that `select`), so i'm not really sure
that would be worth it just yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375378 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-20 20:52:06 +00:00
Roman Lebedev
150b0bedb7 [NFC][InstCombine] conditional sign-extend of high-bit-extract: 'and' pat. can be 'or' pattern.
In this pattern, all the "magic" bits that we'd add are all
high sign bits, and in the value we'd be adding to they are all unset,
not unexpectedly, so we can have an `or` there:
https://rise4fun.com/Alive/ups

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375377 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-20 20:51:37 +00:00
GN Sync Bot
b7aa2ef391 gn build: Merge r375375
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375376 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-20 20:44:56 +00:00
Vladimir Vereschaka
eec7ef7443 Reverted r375254 as it has broken some build bots for a long time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375375 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-20 20:39:33 +00:00
Nikita Popov
e568120da3 [InstCombine] Fold uadd.sat(a, b) == 0 and usub.sat(a, b) == 0
This adds folds for comparing uadd.sat/usub.sat with zero:

 * uadd.sat(a, b) == 0 => a == 0 && b == 0 => (a | b) == 0
 * usub.sat(a, b) == 0 => a <= b

And inverted forms for !=.

Differential Revision: https://reviews.llvm.org/D69224

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375374 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-20 20:19:42 +00:00
Zinovy Nis
2b0c82a99f Fix buildbot error in SIRegisterInfo.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375373 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-20 20:01:16 +00:00
Nikita Popov
3ab0cb15c0 [InstCombine] Add tests for uadd/sub.sat(a, b) == 0; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375372 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-20 19:50:31 +00:00
Roman Lebedev
32d24a3249 [InstCombine] Shift amount reassociation in shifty sign bit test (PR43595)
Summary:
This problem consists of several parts:
* Basic sign bit extraction - `trunc? (?shr %x, (bitwidth(x)-1))`.
  This is trivial, and easy to do, we have a fold for it.
* Shift amount reassociation - if we have two identical shifts,
  and we can simplify-add their shift amounts together,
  then we likely can just perform them as a single shift.
  But this is finicky, has one-use restrictions,
  and shift opcodes must be identical.

But there is a super-pattern where both of these work together.
to produce sign bit test from two shifts + comparison.
We do indeed already handle this in most cases.
But since we get that fold transitively, it has one-use restrictions.
And what's worse, in this case the right-shifts aren't required to be
identical, and we can't handle that transitively:

If the total shift amount is bitwidth-1, only a sign bit will remain
in the output value. But if we look at this from the perspective of
two shifts, we can't fold - we can't possibly know what bit pattern
we'd produce via two shifts, it will be *some* kind of a mask
produced from original sign bit, but we just can't tell it's shape:
https://rise4fun.com/Alive/cM0 https://rise4fun.com/Alive/9IN

But it will *only* contain sign bit and zeros.
So from the perspective of sign bit test, we're good:
https://rise4fun.com/Alive/FRz https://rise4fun.com/Alive/qBU
Superb!

So the simplest solution is to extend `reassociateShiftAmtsOfTwoSameDirectionShifts()` to also have a
sudo-analysis mode that will ignore extra-uses, and will only check
whether a) those are two right shifts and b) they end up with bitwidth(x)-1
shift amount and return either the original value that we sign-checking,
or null.

This does not have any functionality change for
the existing `reassociateShiftAmtsOfTwoSameDirectionShifts()`.

All that being said, as disscussed in the review, this yet again
increases usage of instsimplify in instcombine as utility.
Some day that may need to be reevaluated.

https://bugs.llvm.org/show_bug.cgi?id=43595

Reviewers: spatel, efriedma, vsk

Reviewed By: spatel

Subscribers: xbolva00, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D68930

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375371 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-20 19:38:50 +00:00
Roman Lebedev
7bd6e166d9 [ConstantRange] makeGuaranteedNoWrapRegion(): shl support
Summary:
If all the shifts amount are already poison-producing,
then we can add more poison-producing flags ontop:
https://rise4fun.com/Alive/Ocwi

Otherwise, we should only consider the possible range of shift amts that don't result in poison.

For unsigned range not not overflow, we must not shift out any set bits,
and the actual limit for `x` can be computed by backtransforming
the maximal value we could ever get out of the `shl` - `-1` through
`lshr`. If the `x` is any larger than that then it will overflow.

Likewise for signed range, but just in signed domain..

This is based on the general idea outlined by @nikic in https://reviews.llvm.org/D68672#1714990

Reviewers: nikic, sanjoy

Reviewed By: nikic

Subscribers: hiraditya, llvm-commits, nikic

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D69217

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375370 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-20 19:36:55 +00:00
Nikita Popov
467514942a [ConstantRange] Optimize nowrap region test, remove redundant tests; NFC
Enumerate one less constant range in TestNoWrapRegionExhaustive,
which was unnecessary. This allows us to bump the bit count from
3 to 5 while keeping reasonable timing.

Drop four tests for multiply nowrap regions, as these cover subsets
of the exhaustive test. They do use a wider bitwidth, but I don't
think it's worthwhile to have them additionally now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375369 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-20 18:59:14 +00:00
Matt Arsenault
2df5f8ca5d AMDGPU: Increase vcc liveness scan threshold
Avoids a test regression in a future patch. Also add debug printing on
this case, so I waste less time debugging folds in the future.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375367 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-20 17:44:17 +00:00
Matt Arsenault
f154896069 AMDGPU: Split flat offsets that don't fit in DAG
We handle it this way for some other address spaces.

Since r349196, SILoadStoreOptimizer has been trying to do this. This
is after SIFoldOperands runs, which can change the addressing
patterns. It's simpler to just split this earlier.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375366 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-20 17:34:44 +00:00
Matt Arsenault
d8b4d6f7e1 AMDGPU: Fix missing OPERAND_IMMEDIATE
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375365 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-20 16:56:10 +00:00
Matt Arsenault
2f75f81688 AMDGPU: Add baseline tests for flat offset splitting
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375364 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-20 16:33:21 +00:00
Matt Arsenault
01d98c6ec5 AMDGPU: Don't re-get the subtarget
It's already available in the class.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375363 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-20 16:26:26 +00:00
George Rimar
38d4353156 [yaml2obj][obj2yaml] - Do not create a symbol table by default.
This patch tries to resolve problems faced in D68943
and uses some of the code written by Konrad Wilhelm Kleine
in that patch.

Previously, yaml2obj tool always created a .symtab section.
This patch changes that. With it we only create it when
have a "Symbols:" tag in the YAML document or when
we need to create it because it is used by another section(s).

obj2yaml follows the new behavior and does not print "Symbols:"
anymore when there is no symbol table.

Differential revision: https://reviews.llvm.org/D69041

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375361 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-20 14:47:17 +00:00
Zinovy Nis
9873f72649 Fix minor warning in DWARFVerifier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375357 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-20 07:55:50 +00:00
Matt Arsenault
b0113baebf AMDGPU: Don't error on calls to null or undef
Calls to constants should probably be generally handled.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375356 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-20 07:46:04 +00:00
Philip Reames
c624032000 [SCEV] Simplify umin/max of zext and sext of the same value
This is a common idiom which arises after induction variables are widened, and we have two or more exit conditions.  Interestingly, we don't have instcombine or instsimplify support for this either.

Differential Revision: https://reviews.llvm.org/D69006



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375349 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-19 17:23:02 +00:00
Simon Pilgrim
f7d6a8bc69 [X86] Pulled out helper to decode target shuffle element sentinel values to 'Zeroable' known undef/zero bits. NFCI.
Renamed 'resolveTargetShuffleAndZeroables' to 'resolveTargetShuffleFromZeroables' to match.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375348 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-19 16:58:24 +00:00
Sanjay Patel
0d04cbb578 [TargetLowering][DAGCombine][MSP430] add/use hook for Shift Amount Threshold (1/2)
Provides a TLI hook to allow targets to relax the emission of shifts, thus enabling
codegen improvements on targets with no multiple shift instructions and cheap selects
or branches.

Contributes to a Fix for PR43559:
https://bugs.llvm.org/show_bug.cgi?id=43559

Patch by: @joanlluch (Joan LLuch)

Differential Revision: https://reviews.llvm.org/D69116

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375347 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-19 16:57:02 +00:00
Nemanja Ivanovic
3166412328 [ARM] Add dependency on GlobalISel for unit tests to fix shared libs build
The unit test uses GlobalISel but the dependency is not listed in the
CMakeLists.txt file which causes failures in shared libs build with GCC.

This just adds the dependency.

Differential revision: https://reviews.llvm.org/D69064


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375346 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-19 16:40:26 +00:00
Sanjay Patel
896dde46ee [MSP430] Shift Amount Threshold in DAGCombine (Baseline Tests); NFC
Patch by: @joanlluch (Joan LLuch)

Differential Revision: https://reviews.llvm.org/D69099

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375345 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-19 16:29:32 +00:00
Simon Pilgrim
200d59f918 [X86][SSE] lowerV16I8Shuffle - tryToWidenViaDuplication - undef unpack args
tryToWidenViaDuplication lowers using the shuffle_v8i16(unpack_v16i8(shuffle_v8i16(x),shuffle_v8i16(x))) pattern, but the unpack only needs the even/odd 16i8 args if the original v16i8 shuffle mask references the even/odd elements - which isn't true for many extension style shuffles.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375342 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-19 13:18:02 +00:00
Simon Pilgrim
39580be1ee [X86][SSE] LowerUINT_TO_FP_i64 - only use HADDPD for size/fast-hops
We were always generating a single source HADDPD, but really we should only do this if shouldUseHorizontalOp says its a good idea.

Differential Revision: https://reviews.llvm.org/D69175

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375341 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-19 11:53:48 +00:00
Sylvestre Ledru
0b2777c548 Explicit in the doc the current list of projects (with easy copy and paste)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375339 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-19 09:55:24 +00:00
Sylvestre Ledru
f878e5cae9 Make it clear in the doc that 'all' in LLVM_ENABLE_PROJECTS does install ALL projects
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375337 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-19 09:27:14 +00:00
Reid Kleckner
8ed36b6cc7 Avoid including CodeView/SymbolRecord.h from MCStreamer.h
Move the types needed out so they can be forward declared instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375325 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-19 01:44:09 +00:00
Matt Arsenault
e9835c0f31 AMDGPU: Remove optnone from a test
It's not clear why the test had this. I'm unable to break the original
case with the original patch reverted with or without optnone.

This avoids a failure in a future commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375321 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-19 01:34:59 +00:00
Reid Kleckner
a83ebc9d3b Prune a LegacyDivergenceAnalysis and MachineLoopInfo include each
Now X86ISelLowering doesn't depend on many IR analyses.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375320 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-19 01:31:09 +00:00
Reid Kleckner
c4185e8c3c Prune Analysis includes from SelectionDAG.h
Only forward declarations are needed here. Follow-on to r375311.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375319 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-19 01:07:48 +00:00
Reid Kleckner
d4448b8ece Move endian constant from Host.h to SwapByteOrder.h, prune include
Works on this dependency chain:
  ArrayRef.h ->
  Hashing.h -> --CUT--
  Host.h ->
  StringMap.h / StringRef.h

ArrayRef is very popular, but Host.h is rarely needed. Move the
IsBigEndianHost constant to SwapByteOrder.h. Clients of that header are
more likely to need it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375316 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-19 00:48:11 +00:00
Reid Kleckner
ccf0b77ef9 Prune two MachineInstr.h includes, fix up deps
MachineInstr.h included AliasAnalysis.h, which includes a world of IR
constructs mostly unneeded in CodeGen. Prune it. Same for
DebugInfoMetadata.h.

Noticed with -ftime-trace.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375311 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-19 00:22:07 +00:00
Matt Arsenault
8672594561 LiveIntervals: Fix handleMoveUp with subreg def moving across a def
If a subregister def was moved across another subregister def and
another use, the main range was not correctly updated. The end point
of the moved interval ended too early and missed the use from theh
other lanes in the subreg def.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375300 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-18 23:24:25 +00:00
Peter Collingbourne
f6288975c0 gn build: Build compiler-rt code with -fvisibility=hidden.
This matches the CMake build.

Differential Revision: https://reviews.llvm.org/D69202

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375299 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-18 22:52:17 +00:00