Commit Graph

157261 Commits

Author SHA1 Message Date
Michal Gorny
5f26e59f29 [cmake] Pass -Wl,-z,nodelete on Linux to prevent unloading
Prevent unloading shared libraries on Linux when dlclose() is called.
This is necessary since command-line option parsing API relies on
registering the global option instances in the option parser instance
which can be loaded in a different shared library.

Given that we can't reliably remove those options when a library is
unloaded, the parser ends up containing dangling references. Since glibc
has relatively complex library unloading rules, some of the LLVM
libraries can be unloaded while others (including the Support library)
stay loaded causing quite a mayhem. To reliably prevent that, just
forbid unloading all libraries -- it's a very bad idea anyway.

While the issue arguably happens only with BUILD_SHARED_LIBS, it may
affect any library reusing llvm::cl interface.

Based on patch provided Ross Hayward on https://bugs.gentoo.org/617154.
Previously hit by Fedora back in Feb 2016:
https://lists.freedesktop.org/archives/mesa-dev/2016-February/107242.html

Differential Revision: https://reviews.llvm.org/D40459

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319069 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-27 18:34:52 +00:00
Craig Topper
359627ff70 [X86] Remove an unused isel pattern that looked for pshufd with v4f32 type.
I don't believe our current lowering/combining would ever produce such a node. We only produce integer typed pshufds.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319068 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-27 18:25:54 +00:00
Sanjay Patel
c7c532a9fd [InstCombine] use 'auto' with 'dyn_cast'; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319067 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-27 18:19:32 +00:00
Craig Topper
8b3bfa3cd5 [X86] Teach combineX86ShuffleChain that AllowIntDomain requires at least SSE2.
I don't have a good test case for this at the moment. I was playing around with a change in legalizing and triggered this code to produce a PSHUFD with sse1 only.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319066 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-27 18:15:14 +00:00
Simon Pilgrim
89f274998d [X86][AVX512] Tag AVX512 PACKSS/PACKUS/PMADDWD/PMADDUBSW instructions with SSE_PACK/SSE_PMADD schedule classes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319065 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-27 18:14:18 +00:00
Krzysztof Parzyszek
ee0ba22d45 [Hexagon] Implement HexagonSubtarget::isHVXVectorType
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319064 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-27 18:12:16 +00:00
Craig Topper
538fe17c99 [X86] Add avx512bw command lines to vselect-packss.ll
This shows several places where we fail to use masked move or blendm.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319063 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-27 18:00:49 +00:00
Jonas Hahnfeld
a43196c145 Delete obsolete function mergeUseListsImpl
mergeUseLists is implemented iteratively since r243590.

Differential Revision: https://reviews.llvm.org/D40491

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319061 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-27 17:55:47 +00:00
Craig Topper
be0b1c9108 [X86] Make getSetCCResultType return vXi1 for any vXi32/vXi64 vector over 512 bits long when AVX512 is enabled.
Similar for vXi16/vXi8 with BWI.

Any vector larger than 512 bits will be split to 512 bits during legalization. But without this we will fold sexts with them before that making it difficult to recover leading to scalarization.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319059 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-27 17:51:55 +00:00
Simon Pilgrim
7090837bc7 [X86][SSE] Fix roundpd instructions to correctly use IIC_SSE_ROUNDPD_* itineraries
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319054 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-27 17:29:49 +00:00
Dmitry Preobrazhensky
6f67bb8d45 [AMDGPU][MC][DISASSEMBLER][GFX9] Corrected decoding of GLOBAL/SCRATCH opcodes
See bug 35433: https://bugs.llvm.org/show_bug.cgi?id=35433

Differential Revision: https://reviews.llvm.org/D40493

Reviewers: artem.tamazov, SamWot, arsenm

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319050 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-27 17:14:35 +00:00
Zaara Syeda
d89f47709a [Power9] Improvements to vector extract with variable index exploitation
This patch extends on to rL307174 to not use the power9 vector extract with
variable index instructions when extracting word element 1. For such cases,
the existing selection of MFVSRWZ provides a better sequence.

Differential Revision: https://reviews.llvm.org/D38287

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319049 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-27 17:11:03 +00:00
Fangrui Song
c66b9564b9 [XRay] Fix typo in docs. NFC
Reviewers: dberris

Differential Revision: https://reviews.llvm.org/D40461

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319047 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-27 16:59:26 +00:00
Simon Pilgrim
c17b615603 [X86][AVX512] Tag AVX512 sqrt instructions with SSE_SQRT schedule classes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319045 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-27 16:43:18 +00:00
Jonas Devlieghere
8856af92ca [llvm-dwarfdump] Display DW_AT_high_pc as absolute value
DWARF4 relative DW_AT_high_pc values are now displayed as absolute
addresses. The relative value is only shown when explicitly dumping the
forms, i.e. in show-form or verbose mode.

```
DW_AT_low_pc	(0x0000000000000049)
DW_AT_high_pc	(0x00000019)
```

becomes

```
DW_AT_low_pc	(0x0000000000000049)
DW_AT_high_pc	(0x0000000000000062)
```

Differential revision: https://reviews.llvm.org/D40317

rdar://35416943

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319044 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-27 16:40:46 +00:00
Sanjay Patel
52a381f749 [InstSimplify] use m_APFloat to simplify fcmp folds; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319043 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-27 16:37:09 +00:00
Sanjay Patel
b34814e683 [InstSimplify] add fcmp with negative constant tests; NFC
This is a superset of the tests proposed with D40012 to show another potential improvement.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319041 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-27 16:08:34 +00:00
Nirav Dave
dbbb6c5fc3 [DAG] Do MergeConsecutiveStores again before Instruction Selection
Summary:

Now that store-merge is only generates type-safe stores, do a second
pass just before instruction selection to allow lowered intrinsics to
be merged as well.

Reviewers: jyknight, hfinkel, RKSimon, efriedma, rnk, jmolloy

Subscribers: javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D33675

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319036 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-27 15:28:15 +00:00
Simon Pilgrim
0782e893a9 [X86] Add INVLPGA to the existing INVLPG scheduling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319031 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-27 14:39:50 +00:00
Petar Jovanovic
a4fca0b4da [mips] fix asmstring of Ext and Ins instructions and mips16 JALRC/JRC
Make the print format consistent with other assembler instructions.

Adding a tab character instead of space in asmstring of Ext and Ins
instructions.
Removing space around the tab character for JALRC and replacing space with
tab in JRC.

Patch by Milos Stojanovic.

Differential Revision: https://reviews.llvm.org/D38144


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319030 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-27 14:25:36 +00:00
Simon Pilgrim
e5c2374c0a [X86] Add scheduling tests for invlpg/invlpga
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319029 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-27 14:23:55 +00:00
Jan Korous
0c9555a244 [Support] Fix locking of shared variable in threadpool
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319027 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-27 13:42:03 +00:00
Vedran Miletic
14242fe7a3 [AMDGPU] Add custom lowering for llvm.log{,10}.{f16,f32} intrinsics
AMDGPU backend errors with "unsupported call to function" upon
encountering a call to llvm.log{,10}.{f16,f32} intrinsics. This patch
adds custom lowering to avoid that error on both R600 and SI.

Reviewers: arsenm, jvesely

Subscribers: tstellar

Differential Revision: https://reviews.llvm.org/D29942


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319025 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-27 13:26:38 +00:00
John Brawn
8ed68b3671 [CGP] Fix handling of null pointer values in optimizeMemoryInst
The current way that trivial addressing modes are detected incorrectly thinks
that null pointers are non-trivial, leading to an infinite loop where we keep
duplicating the same select. Fix this by aware of null when deciding if an
addressing mode is trivial.

Differential Revision: https://reviews.llvm.org/D40447


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319019 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-27 11:29:15 +00:00
Max Kazantsev
7f70b1d682 [NFC] Add missing unit tests for EquivalenceClasses
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319018 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-27 11:20:58 +00:00
Simon Pilgrim
3189f24875 [X86][FMA] Tag all FMA/FMA4 instructions with WriteFMA schedule class
As mentioned on PR17367, many instructions are missing scheduling tags preventing us from setting 'CompleteModel = 1' for better instruction analysis. This patch deals with FMA/FMA4 which is one of the bigger offenders (along with AVX512 in general).

Annoyingly all scheduler models need to define WriteFMA (now that its actually used), even for older targets without FMA/FMA4 support, but that is an existing problem shared by other schedule classes.

Differential Revision: https://reviews.llvm.org/D40351

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319016 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-27 10:41:32 +00:00
Momchil Velikov
2facd581a0 [ARM] Fix an off-by-one error when restoring LR for 16-bit Thumb
The commit https://reviews.llvm.org/rL318143 computes incorrectly to offset to
restore LR from.

The number of tPOP operands is 2 (condition) + 2 (implicit def and use of SP) +
count of the popped registers. We need to load LR from just past the last
register, hence the correct offset should be either getNumOperands() - 4 and
getNumExplicitOperands() - 2 (multiplied by 4).

Differential revision: https://reviews.llvm.org/D40305



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319014 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-27 10:13:14 +00:00
Andrew V. Tischenko
67a7add24b Update BTVER2 sched numbers for SSE42 string instructions.
Differential Revision: https://reviews.llvm.org/D39846


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319013 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-27 09:58:00 +00:00
Craig Topper
cd0e647e13 [SelectionDAG] Teach SplitVecRes_SETCC to call GetSplitVector if the operands have already been split.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319010 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-27 05:52:54 +00:00
Craig Topper
c532db32e1 [SelectionDAG] Fix function name in comment. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319009 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-27 05:52:52 +00:00
Craig Topper
75de121e01 [X86] Fix an assert that was incorrectly checking for BMI instead of AVX512VBMI.
The check is actually unnecessary since AVX512VBMI implies AVX512BW which is the other part of the assert.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319006 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-26 21:14:48 +00:00
Simon Pilgrim
984b922f6a [X86][3DNow] Add 3DNow! instruction itinerary and scheduling classes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319005 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-26 20:50:29 +00:00
Simon Pilgrim
080a6eba24 [X86][SSE] Add SSE42 tests to the clear upper tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319003 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-26 20:03:53 +00:00
Simon Dardis
eba6c93701 [utils][mips] Add support for mips for update_llc_checks.py
Add support for mips, particularly skipping the matching of .frame, .(f)mask
and LLVM's usage of the .set no(reorder|at|macro) directives.

Reviewers: spatel

Differential Revision: https://reviews.llvm.org/D40268


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319001 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-26 19:22:44 +00:00
Simon Pilgrim
f849dab02c [X86][3DNow] Remove unused I3DNow_binop_rm/I3DNow_conv_rm templates. NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319000 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-26 19:22:37 +00:00
Simon Pilgrim
7872ae5176 [X86][MMX] Add IIC_MMX_MOVMSK instruction itinerary class
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318999 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-26 17:56:07 +00:00
Jatin Bhateja
081379e8b4 [SCEV] Adding a check on outgoing branches of a terminator instr for SCEVBackedgeConditionFolder, NFC.
Summary:
For a given loop, getLoopLatch returns a non-null value
when a loop has only one latch block. In the modified
context adding an assertion to check that both the outgoing branches of
a terminator instruction (of latch) does not target same header.
+
few minor code reorganization.

Reviewers: jbhateja

Reviewed By: jbhateja

Subscribers: sanjoy

Differential Revision: https://reviews.llvm.org/D40460

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318997 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-26 15:08:41 +00:00
Oren Ben Simhon
40090f420c Control-Flow Enforcement Technology - Shadow Stack support (LLVM side)
Shadow stack solution introduces a new stack for return addresses only.
The HW has a Shadow Stack Pointer (SSP) that points to the next return address.
If we return to a different address, an exception is triggered.
The shadow stack is managed using a series of intrinsics that are introduced in this patch as well as the new register (SSP).
The intrinsics are mapped to new instruction set that implements CET mechanism.

The patch also includes initial infrastructure support for IBT.

For more information, please see the following:
https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf

Differential Revision: https://reviews.llvm.org/D40223

Change-Id: I4daa1f27e88176be79a4ac3b4cd26a459e88fed4

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318996 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-26 13:02:45 +00:00
Coby Tayree
a897faafb7 [x86][icelake]GFNI
galois field arithmetic (GF(2^8)) insns:
gf2p8affineinvqb
gf2p8affineqb
gf2p8mulb
Differential Revision: https://reviews.llvm.org/D40373


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318993 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-26 09:36:41 +00:00
Jatin Bhateja
0d7d3a3c32 [SCEV] NFC : Removing unnecessary check on outgoing branches of a branch instr.
Summary:
For a given loop, getLoopLatch returns a non-null value
when a loop has only one latch block. In the modified
context a check on both the outgoing branches of a terminator instruction (of latch) to same header is redundant.

Reviewers: jbhateja

Reviewed By: jbhateja

Subscribers: sanjoy

Differential Revision: https://reviews.llvm.org/D40460

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318991 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-26 02:01:01 +00:00
David Blaikie
d4027e09f4 Remove dead code
(this header is not fully implemented (the out of line function
writeTypeRecordKind is called in an inline function but never
implemented - this fails to link under modular code generation) and not
included anywhere)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318987 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-25 20:06:04 +00:00
Craig Topper
a3d58afd6c [X86] Remove GCCBuiltin from intrinsics that are no longer used by clang.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318986 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-25 20:00:37 +00:00
Craig Topper
fd41de87fc [X86] Add separate intrinsics for scalar FMA4 instructions.
Summary:
These instructions zero the non-scalar part of the lower 128-bits which makes them different than the FMA3 instructions which pass through the non-scalar part of the lower 128-bits.

I've only added fmadd because we should be able to derive all other variants using operand negation in the intrinsic header like we do for AVX512.

I think there are still some missed negate folding opportunities with the FMA4 instructions in light of this behavior difference that I hadn't noticed before.

I've split the tests so that we can use different intrinsics for scalar testing between the two. I just copied the tests split the RUN lines and changed out the scalar intrinsics.

fma4-fneg-combine.ll is a new test to make sure we negate the fma4 intrinsics correctly though there are a couple TODOs in it.

Reviewers: RKSimon, spatel

Reviewed By: RKSimon

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D39851

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318984 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-25 18:32:43 +00:00
Craig Topper
47dab13b27 [X86] Don't report gather is legal on Skylake CPUs when AVX2/AVX512 is disabled. Allow gather on SKX/CNL/ICL when AVX512 is disabled by using AVX2 instructions.
Summary:
This adds a new fast gather feature bit to cover all CPUs that support fast gather that we can use independent of whether the AVX512 feature is enabled. I'm only using this new bit to qualify AVX2 codegen. AVX512 is still implicitly assuming fast gather to keep tests working and to match the scatter behavior.

Test command lines have been added for these two cases.

Reviewers: magabari, delena, RKSimon, zvi

Reviewed By: RKSimon

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D40282

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318983 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-25 18:09:37 +00:00
Craig Topper
4a69267ec7 [SelectionDAG] Remove some dead code from vector scalaring
Summary:
Currently ScalarizeVecRes_SETCC checks for the result type being a vector and jumps to ScalarizeVecRes_VSETCC. But if we're scalarizing a vector result, aren't we guaranteed to be looking at a vector type?

This patch deletes the current ScalarizeVecRes_SETCC and renames  ScalarizeVecRes_VSETCC to ScalarizeVecRes_SETCC.

Reviewers: RKSimon, arsenm, eladcohen, zvi

Reviewed By: RKSimon

Subscribers: wdng, llvm-commits

Differential Revision: https://reviews.llvm.org/D40452

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318982 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-25 17:59:00 +00:00
Andrew V. Tischenko
f5c432d9af Add BTVER2 sched support for SHLD/SHRD.
Differential Revision: https://reviews.llvm.org/D40124


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318977 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-25 10:46:53 +00:00
Craig Topper
a535302064 [X86] Simplify some code in combineSetCC. NFCI
Make the condition for doing a std::swap simpler so we don't have to repeat the full checks.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318970 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-25 07:20:24 +00:00
Craig Topper
54fff5c91a [X86] Qualify some vector specific code with VT.isVector(). NFCI
Other checks inside require a build_vector, but we this lets us stop earlier and makes the code more clear.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318969 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-25 07:20:23 +00:00
Craig Topper
ff7ef15ee6 [X86] Support folding to andnps with SSE1 only.
With SSE1 only, we emit FAND and FXOR nodes for v4f32.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318968 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-25 07:20:22 +00:00
Craig Topper
736b29235d [X86] Add some early DAG combines to turn v4i32 AND/OR/XOR into FAND/FOR/FXOR whe only SSE1 is available.
v4i32 isn't a legal type with sse1 only and would end up getting scalarized otherwise.

This isn't completely ideal as it doesn't handle cases like v8i32 that would get split to v4i32. But it at least helps with code written using the clang intrinsic header.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318967 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-25 07:20:21 +00:00