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Author SHA1 Message Date
Craig Topper
634763c0f5 Cleanup places that passed SMLoc by const reference to pass it by value instead. NFC 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248135 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-09-20 23:35:59 +00:00
Sanjoy Das
dabf510ba1 [IndVars] Use C++11 style field initialization; NFCI. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248131 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-09-20 18:42:53 +00:00
Sanjoy Das
ba0b742fe5 [IndVars] Don't add a level of indentation for namespace {. NFC. 
Whitespace-only change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248130 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-09-20 18:42:50 +00:00
Sanjay Patel
aa5c0021e3 add test file ahead of any functional changes for PR22428 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248123 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-09-20 15:58:00 +00:00
Simon Pilgrim
bf48d8543a [X86][SSE] Intrinsics builtins test refresh. NFCI 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248122 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-09-20 15:41:35 +00:00
Igor Breger
b0eb8fb69c AVX512: Implemented encoding and intrinsics for vcmpss/sd. 
Added tests for intrinsics and encoding.

Differential Revision: http://reviews.llvm.org/D12593

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248121 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-09-20 15:15:10 +00:00
Asaf Badouh
fe11ff1d50 [X86][AVX512] extend support in Scalar conversion 
add scalar FP to Int conversion with truncation intrinsics
add scalar conversion FP32 from/to FP64 intrinsics
add rounding mode and SAE mode encoding for these intrinsics

Differential Revision: http://reviews.llvm.org/D12665

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248117 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-09-20 14:31:19 +00:00
Igor Breger
0d48c46954 AVX512: vsqrtss/sd encoding and intrinsics implementation. 
Added tests for intrinsics and encoding.

Differential Revision: http://reviews.llvm.org/D12102

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248116 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-09-20 09:13:41 +00:00
Asaf Badouh
d3db2cf572 [X86][AVX512DQ] Add fpclass instruction 
Differential Revision: http://reviews.llvm.org/D12931

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248115 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-09-20 08:46:07 +00:00
Michael Kuperstein
5610c28853 [X86] Fix sitofp and uitofp instruction matching failures with long double and avx512 
The operation action for i32 and i64 cannot be set to legal, as long double 
needs custom lowering.

Patch by: mitch.l.bodart@intel.com
Differential Revision: http://reviews.llvm.org/D12372


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248114 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-09-20 08:12:17 +00:00
Igor Breger
d425988995 AVX512: Implemented intrinsics for vshuff32x4, vshuff64x2, vshufi64x2, vshufi32x4 
Added tests for intrinsics.

Differential Revision: http://reviews.llvm.org/D12525

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248113 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-09-20 07:18:53 +00:00
Sanjoy Das
115bb95e68 [IndVars] Don't repeat function names in comment; NFC. 
Only changes comments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248112 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-09-20 06:58:03 +00:00
Igor Breger
28cce2ad25 AVX512: Implement instructions encoding, lowering and intrinsics 
vinserti64x4, vinserti64x2, vinserti32x8, vinserti32x4, vinsertf64x4, vinsertf64x2, vinsertf32x8, vinsertf32x4
Added tests for encoding, lowering and intrinsics.

Differential Revision: http://reviews.llvm.org/D11893

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248111 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-09-20 06:52:42 +00:00
Saleem Abdulrasool
2479d65186 ARM: cleanup formatting 
clang-format a line which was poorly formatted.  NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248110 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-09-20 03:19:09 +00:00
Sanjoy Das
8ba782a30c [IndVars] Fix a bug in r248045. 
Because -indvars widens induction variables through arithmetic,
`NeverNegative` cannot be a property of the `WidenIV` (a `WidenIV`
manages information for all transitive uses of an IV being widened,
including uses of `-1 * IV`).  Instead it must live on `NarrowIVDefUse`
which manages information for a specific def-use edge in the transitive
use list of an induction variable.

This change also adds a test case that demonstrates the problem with
r248045.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248107 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-09-20 01:52:18 +00:00
Davide Italiano
d58f92c07d Fixup r248096, commit the *correct* test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248097 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-09-19 20:52:47 +00:00
Davide Italiano
e986a9d52e [obj2yaml] Fix "time of check to time of use" bug. Add a test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248096 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-09-19 20:49:34 +00:00
Simon Pilgrim
0e92420490 [X86][AVX2] Use general sext IR for vpmovsx stack folding tests 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248093 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-09-19 17:04:18 +00:00
Simon Pilgrim
afa71f40bf [X86][SSE] Vectorize CTTZ + CTTZ_ZERO_UNDEF 
Now that we have fast vector CTPOP implementations we can use this to speed up vector CTTZ using the pattern (cttz(x) = ctpop((x & -x) - 1))

Additionally, for AVX512CD that provides lzcnt instructions we can use the pattern (cttz_undef(x) = (width - 1) - ctlz(x & -x))

Differential Revision: http://reviews.llvm.org/D12663

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248091 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-09-19 13:22:57 +00:00
Simon Pilgrim
02dd54df02 [InstCombine] Use SimplifyDemandedVectorEltsLow helper function. NFCI. 
Use the SimplifyDemandedVectorEltsLow helper function introduced in D12680.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248089 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-09-19 11:41:53 +00:00
NAKAMURA Takumi
7a4660aaa9 [CMake] Update LLVM_TEST_DEPENDS not to use macho-dump. It has been unused since r247235. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248088 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-09-19 07:19:30 +00:00
Matt Arsenault
96465eb3e3 AMDGPU: Remove dead code 
getCFGStructurizerRegClass is not used for SI, so
move it into R600 specific stuff.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248087 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-09-19 06:41:10 +00:00
Bob Wilson
976d66dd2d NFC: Fix indentation and add braces to clarify nested of else-statement. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248086 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-09-19 06:20:59 +00:00
Maksim Panchenko
4e9ce340e6 [PrologEpilogInserter] Minor refactoring. 
Differential Revision: http://reviews.llvm.org/D12924


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248084 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-09-19 04:42:15 +00:00
Maksim Panchenko
3d047dfbb7 Test commit. Fix comment. NFC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248082 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-09-19 04:01:19 +00:00
David Majnemer
bdf4ccfe9b [InstCombine] FoldICmpCstShrCst failed for ashr when comparing against -1 
(icmp eq (ashr C1, %V) -1) may have multiple answers if C1 is not a
power of two and has the sign bit set.

This fixes PR24873.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248074 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-09-19 00:48:31 +00:00
David Majnemer
1e4af08410 [InstCombine] FoldICmpCstShrCst didn't handle icmps of -1 in the ashr case correctly 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248073 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-09-19 00:48:26 +00:00
Matt Arsenault
124f7d9b25 AMDGPU: Add failing testcase for live interval construction 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248067 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-09-19 00:03:56 +00:00
Sanjoy Das
9025a1f860 [IndVars] Widen more comparisons for non-negative induction vars 
Summary:
If an induction variable is provably non-negative, its sign extension is
equal to its zero extension.  This means narrow uses like

  icmp slt iNarrow %indvar, %rhs

can be widened into

  icmp slt iWide zext(%indvar), sext(%rhs)

Reviewers: atrick, mcrosier, hfinkel

Subscribers: hfinkel, reames, llvm-commits

Differential Revision: http://reviews.llvm.org/D12745

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248045 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-09-18 21:21:02 +00:00
Luke Larson
204847af9d Fix typo and test commit 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248042 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-09-18 21:15:45 +00:00
Rafael Espindola
26a99b2dc8 This code never uses r_addend, so it can just use Elf_Rel. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248040 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-09-18 21:12:38 +00:00
Chris Bieneman
907451c6d6 [CMake] Adding ALWAYS_GENERATE option to symlink utility functions. 
This implements the behavior required for clang symlinks which should be always generated.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248039 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-09-18 21:08:32 +00:00
Davide Italiano
5310d9c491 [Object/ELF] Change comment to reflect reality. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248032 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-09-18 20:41:15 +00:00
Cong Hou
2f91ab3d22 Update edge weights properly when merging blocks in if-conversion. 
In if-conversion, there is a utility function MergeBlocks() that is used to merge blocks. However, when new edges are built in this function the edge weight is either not provided or not updated properly, leading to a modified CFG with incorrect edge weights. This patch corrects this issue.

Differential Revision: http://reviews.llvm.org/D12513



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248030 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-09-18 20:22:41 +00:00
Eric Christopher
c4db514911 Limit the range of processors supported by ARM fast isel to v6 or 
later as that's all that is tested right now.

Fixes PR24858.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248027 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-09-18 20:08:18 +00:00
Teresa Johnson
c4736349a5 Remove couple of new Bitcode enum vals that snuck in via r247927 (NFC) 
These are meant to be part of the follow on patch I am sending for
review shortly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248023 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-09-18 19:38:53 +00:00
Larisse Voufo
69328805da Clean up: Refactoring the hardcoded value of 6 for FindAvailableLoadedValue()'s parameter MaxInstsToScan. (Complete version of r247497. See D12886) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248022 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-09-18 19:14:35 +00:00
James Y Knight
dc18fbbb2d Make MachineScheduler debug output less confusing. 
At least...a little bit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248020 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-09-18 18:52:20 +00:00
Cong Hou
759d988de3 Scaling up values in ARMBaseInstrInfo::isProfitableToIfCvt() before they are scaled by a probability to avoid precision issue. 
In ARMBaseInstrInfo::isProfitableToIfCvt(), there is a simple cost model in which the number of cycles is scaled by a probability to estimate the cost. However, when the number of cycles is small (which is usually the case), there is a precision issue after the computation. To avoid this issue, this patch scales those cycles by 1024 (chosen to make the multiplication a litter faster) before they are scaled by the probability. Other variables are also scaled up for the final comparison.

Differential Revision: http://reviews.llvm.org/D12742



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248018 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-09-18 18:19:40 +00:00
Matthias Braun
8aa8c4d086 SelectionDAGDumper: Leave out the <multiple use> markers 
They mostly clutter the output while it is still possible to see which
node has multiple users without them.

Differential Revision: http://reviews.llvm.org/D12569

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248013 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-09-18 17:57:33 +00:00
Matthias Braun
780502f6f2 SelectionDAGDumper: Avoid unnecessary newlines 
Before:
  t0 = EntryToken:ch

    t0: <multiple use>
        t0: <multiple use>
      t1 = CopyFromReg:v4f32,ch t0, Register:v4f32  %vreg0

      t25 = IMPLICIT_DEF:v4f32

    t26 = HADDPSrr:v4f32 t1, t25

  t23 = CopyToReg:ch,glue t0, Register:v4f32  %XMM0, t26

    t23: <multiple use>
    t23: <multiple use>
  t24 = RETQ:ch Register:v4f32  %XMM0, t23, t23:1

After:
    t0: <multiple use>
        t0: <multiple use>
      t1 = CopyFromReg:v4f32,ch t0, Register:v4f32  %vreg0
    t26 = X86ISD::FHADD:v4f32 t1, undef:v4f32
  t23 = CopyToReg:ch,glue t0, Register:v4f32  %XMM0, t26
    t23: <multiple use>
    t21 = TargetConstant:i16<0>
    t23: <multiple use>
  t24 = X86ISD::RET_FLAG:ch t23, t21, Register:v4f32  %XMM0, t23:1

Differential Revision: http://reviews.llvm.org/D12568

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248012 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-09-18 17:57:31 +00:00
Matthias Braun
d53e4c92e5 SelectionDAGDumper: Hide [ID=X], [ORD=X] and source locations by default. 
You can show them with the new -dag-dump-verbose switch.

Differential Revision: http://reviews.llvm.org/D12566

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248011 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-09-18 17:57:28 +00:00
Matthias Braun
6c76d11db8 SelectionDAG: Introduce PersistentID to SDNode for assert builds. 
This gives us more human readable numbers to identify nodes in debug
dumps.

Before:
  0x7fcbd9700160: ch = EntryToken

  0x7fcbd985c7c8: i64 = Register %RAX

   ...

      0x7fcbd9700160: <multiple use>
    0x7fcbd985c578: i64,ch = MOV64rm 0x7fcbd985c6a0, 0x7fcbd985cc68, 0x7fcbd985c200, 0x7fcbd985cd90, 0x7fcbd985ceb8, 0x7fcbd9700160<Mem:LD8[@foo]> [ORD=2]

  0x7fcbd985c8f0: ch,glue = CopyToReg 0x7fcbd9700160, 0x7fcbd985c7c8, 0x7fcbd985c578 [ORD=3]

    0x7fcbd985c7c8: <multiple use>
    0x7fcbd985c8f0: <multiple use>
    0x7fcbd985c8f0: <multiple use>
  0x7fcbd985ca18: ch = RETQ 0x7fcbd985c7c8, 0x7fcbd985c8f0, 0x7fcbd985c8f0:1 [ORD=3]

Now:
  t0: ch = EntryToken

  t5: i64 = Register %RAX

    ...

      t0: <multiple use>
    t3: i64,ch = MOV64rm t10, t12, t11, t13, t14, t0<Mem:LD8[@foo]> [ORD=2]

  t6: ch,glue = CopyToReg t0, t5, t3 [ORD=3]

    t5: <multiple use>
    t6: <multiple use>
    t6: <multiple use>
  t7: ch = RETQ t5, t6, t6:1 [ORD=3]

Differential Revision: http://reviews.llvm.org/D12564

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248010 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-09-18 17:41:00 +00:00
Chris Bieneman
f8d6e92d57 [CMake] More cleanup of installing symlinks. 
In order to support building clang out-of-tree the install_symlink script needs to be installed, and it needs to be found by searching the CMAKE_MODULE_PATH.

This change renames install_symlink -> LLVMInstallSymlink so it doesn't conflict with naming from other projects, and adds searching behavior in AddLLVM.cmake

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248009 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-09-18 17:39:58 +00:00
Geoff Berry
068d9ce827 [AArch64] Improved bitfield instruction selection. 
Summary:
For bitfield insert OR matching, check both operands for larger pattern
first before checking for smaller pattern.

Add pattern for unsigned bitfield insert-in-zero done with SHL+AND.

Resolves PR21631.

Reviewers: jmolloy, t.p.northover

Subscribers: aemerson, rengolin, llvm-commits, mcrosier

Differential Revision: http://reviews.llvm.org/D12908

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248006 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-09-18 17:11:53 +00:00
Rafael Espindola
e016c66756 Remove temporary file on signal. 
Without this lld leaves temporary files behind when it crashes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247994 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-09-18 15:17:53 +00:00
Yaron Keren
81a5ddcd9f Simplify SmallBitVector::applyMask by consolidating common code for 32- and 64-bit builds 
and assert when mask is too large to apply in the small case,
previously the extra words were silently ignored.
clang-format the entire function to match current code standards.

This is a rewrite of r247972 which was reverted in r247983 due to
warning and possible UB on 32-bits hosts.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247993 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-09-18 15:08:24 +00:00
Daniel Sanders
45f413067f [mips][microMIPS] Fix an invalid read for lwm32 and reserved reglist values. 
Summary:
Some values of 'reglist' are reserved and cause the disassembler to read past
the end of the Regs array. Treat lwm32's containing reserved values as invalid
instructions.

Reviewers: zoran.jovanovic

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D12959

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247990 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-09-18 14:20:54 +00:00
Chad Rosier
efcddc28d1 [AArch64] Reorder cases to improve readability. NFC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247989 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-09-18 14:15:19 +00:00
Chad Rosier
e732875e6e [AArch64] Remove some redundant cases. NFC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247988 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-09-18 14:13:18 +00:00