Commit Graph

4693 Commits

Author SHA1 Message Date
Igor Breger
2fe1f6e4f3 AVX512: Change encoding of vpshuflw and vpshufhw instructions. Implement WIG as W0 and not W1, like all other instruction have been implemented.
Add encoding tests.

Differential Revision: http://reviews.llvm.org/D13471

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249521 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-07 06:31:18 +00:00
Tom Stellard
63c550368d AMDGPU/SI: Add 64-bit versions of v_nop and v_clrexcp
Summary:
The assembly printing of these is still missing the encoding size
suffix, but this will be fixed in a later commit.

Reviewers: arsenm

Subscribers: arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D13436

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249424 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-06 15:57:53 +00:00
Daniel Sanders
c06b5e8aab [mips][disassembler] Changed CHECK-EB directives to CHECK so div/divu are tested.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249386 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-06 10:08:14 +00:00
Daniel Sanders
502ad00119 [mips][disassembler] Merged disassembler tests into the corresponding ISA/ASE subdirectories.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249384 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-06 10:02:35 +00:00
Daniel Sanders
90e50f7d16 [mips][disassembler] Moved DSP tests into proper place and corrected formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249383 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-06 09:28:48 +00:00
Zoran Jovanovic
d0b3d6159d [mips][microMIPS] Implement JALRC16, JRCADDIUSP and JRC16 instructions
Differential Revision: http://reviews.llvm.org/D11219


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249317 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-05 14:00:09 +00:00
Alexandros Lamprineas
82e78e2e9d [MC layer][AArch64] llvm-mc accepts 4-bit immediate values for
"msr pan, #imm", while only 1-bit immediate values should be valid.
Changed encoding and decoding for msr pstate instructions.

Differential Revision: http://reviews.llvm.org/D13011

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249313 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-05 13:42:31 +00:00
Daniel Sanders
fbdf2017ea [mips] Changed the way symbols are handled in dla and la instructions to allow simple expressions.
Summary:
An instruction like "(d)la $5, symbol+8" previously would have crashed the
assembler as it contains an expression. This is now fixed.
A few tests cases have also been changed to reflect these changes, however
these should only be syntax changes. Some new test cases have also been
added.

Patch by Scott Egerton.

Reviewers: vkalintiris, dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D12760


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249311 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-05 13:19:29 +00:00
Rafael Espindola
0eba49c22e Fix pr24486.
This extends the work done in r233995 so that now getFragment (in addition to
getSection) also works for variable symbols.

With that the existing logic to decide if a-b can be computed works even if
a or b are variables. Given that, the expression evaluation can avoid expanding
variables as aggressively and that in turn lets the relocation code see the
original variable.

In order for this to work with the asm streamer, there is now a dummy fragment
per section. It is used to assign a section to a symbol when no other fragment
exists.

This patch is a joint work by Maxim Ostapenko andy myself.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249303 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-05 12:07:05 +00:00
Joerg Sonnenberger
58b865b86c [SPARCv9] Add support for the rdpr/wrpr instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249262 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-04 09:11:22 +00:00
Igor Breger
295b19789d AVX512: Implemented encoding and intrinsics for VPERMILPS/PD instructions.
Added tests for intrinsics and encoding.

Differential Revision: http://reviews.llvm.org/D12690

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249261 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-04 07:20:41 +00:00
Roman Divacky
87b7b2f3a0 Actually switch the arch when we see .arch. PR21695
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249165 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-02 18:25:25 +00:00
Tim Northover
90161a29d9 ARM: diagnose invalid local fixups on Thumb1
We previously stopped producing Thumb2 relaxations when they weren't supported,
but only diagnosed the case where an actual relocation was produced. We should
also tell people if local symbols aren't going to work rather than silently
overflowing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249164 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-02 18:07:18 +00:00
Joerg Sonnenberger
fd813994db Fix relocation used for GOT references in non-PIC mode. Fix relocations
for "set" pseudo op in PIC mode.

Differential Revision: http://reviews.llvm.org/D13173


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249086 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-01 22:08:20 +00:00
Ulrich Weigand
4e00ed4cbf [SystemZ] Add assembly instructions for obtaining clock values as well as CPU features
Provide assembler support for STCK, STCKF, STCKE, and STFLE.

Author: joncmu
Differential Revision: http://reviews.llvm.org/D13299


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249015 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-01 14:43:48 +00:00
Zoran Jovanovic
7bfea190a4 [mips][microMIPS] Implement CACHEE, WRPGPR and WSBH instructions
Differential Revision: http://reviews.llvm.org/D10337


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249004 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-01 12:49:27 +00:00
Artyom Skrobov
d84fffe1de [ARM] Support for ARMv6-Z / ARMv6-ZK missing
As Richard Barton observed at http://reviews.llvm.org/D12937#inline-107121
TargetParser in LLVM has insufficient support for ARMv6Z and ARMv6ZK.

In particular, there were no tests for TrustZone being supported in these
architectures.

The patch clears a FIXME: left by Saleem Abdulrasool in r201471, and fixes
his test case which hadn't really been testing what it was claiming to test.

Differential Revision: http://reviews.llvm.org/D13236


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248921 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-30 17:25:52 +00:00
Zoran Jovanovic
3b17c1cb31 [mips] Handling of immediates bigger than 16 bits
Differential Revision: http://reviews.llvm.org/D10539


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248706 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-28 11:11:34 +00:00
Tom Stellard
1566e71dbd AMDGPU/SI: Use .hsatext section instead of .text for HSA
Reviewers: arsenm, grosbach, rafael

Subscribers: arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D12424

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248619 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-25 21:41:28 +00:00
Ed Maste
5f57fe0847 Restore test coverage for other than ELFOSABI_NONE
Add a FreeBSD test to restore testing of ELF OSABI other than
ELFOSABI_NONE after r248534.

Differential Revision:	http://reviews.llvm.org/D13146


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248550 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-24 23:01:16 +00:00
Rafael Espindola
5c37d1622d Use ELFOSABI_NONE instead of ELFOSABI_LINUX.
The doesn't seem to be a difference and ELFOSABI_NONE seems to be far more
common:

* Linux doesn't care when loading and puts ELFOSABI_NONE on core dumps.
* Gold and bfd ld produce files with ELFOSABI_NONE.
* Gold and bfd ld seems to ignore EI_OSABI other than for freebsd.
* Gas puts ELFOSABI_NONE in most .o files.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248534 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-24 20:57:24 +00:00
Matt Arsenault
d0edb1f758 AMDGPU: Add s_dcache_* instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248533 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-24 19:52:27 +00:00
Matt Arsenault
1348e9d04d AMDGPU: Add cache invalidation instructions.
These are necessary for implementing mem_fence for
OpenCL 2.0.

The VI assembler tests are disabled since it seems to be
using the wrong encoding or opcode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248532 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-24 19:52:21 +00:00
Matt Arsenault
a16e3ad6da AMDGPU: Run mubuf assembler test for CI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248531 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-24 19:52:15 +00:00
Daniel Sanders
28042167f5 [mips][ias] Implement .cpreturn directive.
Summary:
Based on a patch by David Chisnall. I've modified the original patch as follows:
* Moved the expansion to the TargetStreamers so that the directive isn't
  expanded when emitting assembly.
* Fixed an operand order bug.
* Changed the move instructions from DADDu to OR to match recent changes to GAS.

Reviewers: vkalintiris

Subscribers: llvm-commits, emaste, seanbruno, theraven

Differential Revision: http://reviews.llvm.org/D13017

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248258 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-22 10:50:09 +00:00
Asaf Badouh
648a027c82 [X86][AVX512] add masked version for RSQRT14 & RCP14 Scalar FP
Differential Revision: http://reviews.llvm.org/D12524

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248147 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-21 10:23:53 +00:00
Daniel Sanders
99351d8c0e [mips] Allow constant expressions in second argument of .cpsetup.
Summary:
Also tightened up the test and made a trivial fix to prevent double-newline
after emitting .cpsetup directives.

Reviewers: vkalintiris

Subscribers: seanbruno, emaste, llvm-commits

Differential Revision: http://reviews.llvm.org/D12956

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248143 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-21 09:26:55 +00:00
Igor Breger
b0eb8fb69c AVX512: Implemented encoding and intrinsics for vcmpss/sd.
Added tests for intrinsics and encoding.

Differential Revision: http://reviews.llvm.org/D12593

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248121 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-20 15:15:10 +00:00
Asaf Badouh
fe11ff1d50 [X86][AVX512] extend support in Scalar conversion
add scalar FP to Int conversion with truncation intrinsics
add scalar conversion FP32 from/to FP64 intrinsics
add rounding mode and SAE mode encoding for these intrinsics

Differential Revision: http://reviews.llvm.org/D12665

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248117 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-20 14:31:19 +00:00
Igor Breger
0d48c46954 AVX512: vsqrtss/sd encoding and intrinsics implementation.
Added tests for intrinsics and encoding.

Differential Revision: http://reviews.llvm.org/D12102

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248116 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-20 09:13:41 +00:00
Asaf Badouh
d3db2cf572 [X86][AVX512DQ] Add fpclass instruction
Differential Revision: http://reviews.llvm.org/D12931

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248115 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-20 08:46:07 +00:00
Igor Breger
28cce2ad25 AVX512: Implement instructions encoding, lowering and intrinsics
vinserti64x4, vinserti64x2, vinserti32x8, vinserti32x4, vinsertf64x4, vinsertf64x2, vinsertf32x8, vinsertf32x4
Added tests for encoding, lowering and intrinsics.

Differential Revision: http://reviews.llvm.org/D11893

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248111 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-20 06:52:42 +00:00
Daniel Sanders
45f413067f [mips][microMIPS] Fix an invalid read for lwm32 and reserved reglist values.
Summary:
Some values of 'reglist' are reserved and cause the disassembler to read past
the end of the Regs array. Treat lwm32's containing reserved values as invalid
instructions.

Reviewers: zoran.jovanovic

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D12959

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247990 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-18 14:20:54 +00:00
Joerg Sonnenberger
e301d76124 [SPARC] Add mulscc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247940 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-17 20:54:26 +00:00
Daniel Sanders
92150c7f12 [mips] Add assembler support for the .cprestore directive.
Summary:
This assembler directive is used in O32 PIC to restore the current function's $gp after executing JAL's. The $gp is first stored on the stack at a user-specified offset.
It has the following format: ".cprestore 8" (where 8 is the offset).

This fixes llvm.org/PR20967.

Patch by Toma Tabacu.

Reviewers: seanbruno, tomatabacu

Subscribers: brooks, seanbruno, emaste, llvm-commits

Differential Revision: http://reviews.llvm.org/D6267


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247897 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-17 16:08:39 +00:00
Zoran Jovanovic
facd39580a [mips][microMIPS] Implement TEQ, TGE, TGEU, TLT, TLTU and TNE instructions
Differential Revision: http://reviews.llvm.org/D9658


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247880 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-17 10:14:09 +00:00
Reid Kleckner
cba458eecc Add assembler fatal error for undefined assembler labels in COFF writer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247814 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-16 16:26:29 +00:00
Joerg Sonnenberger
e91a80e5b8 [SPARC] Both GNU and Solaris as support eq as condition code for integer ops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247804 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-16 14:41:36 +00:00
Joerg Sonnenberger
a370ed740f [SPARC] Recognize st/stx operations with %fsr argument too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247794 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-16 13:30:54 +00:00
Zoran Jovanovic
de9de11b23 [mips][microMIPS] Implement PREFX, LHUE, LBE, LBUE, LHE, LWE, SBE, SHE and SWE instructions
Differential Revision: http://reviews.llvm.org/D9189


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247780 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-16 09:14:35 +00:00
Mehdi Amini
793a2b15e7 Make the default triple optional by allowing an empty string
When building LLVM as a (potentially dynamic) library that can be linked against
by multiple compilers, the default triple is not really meaningful.
We allow to explicitely set it to an empty string when configuring LLVM.
In this case, said "target independent" tests in the test suite that are using
the default triple are disabled by matching the newly available feature
"default_triple".

Reviewers: probinson, echristo
Differential Revision: http://reviews.llvm.org/D12660

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247775 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-16 05:34:32 +00:00
Zoran Jovanovic
3cedd0b1a0 [mips][microMIPS] Fix an issue with disassembling lwm32 instruction
Fixed microMIPS disassembler crash on test case generated by llvm-mc-fuzzer.
Differential Revision: http://reviews.llvm.org/D12881


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247698 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-15 15:21:27 +00:00
Zoran Jovanovic
8a2b719477 [mips] Add support for branch-likely pseudo-instructions
Differential Revision: http://reviews.llvm.org/D10537


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247697 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-15 15:06:26 +00:00
Zoran Jovanovic
1b6640a5fc [mips][microMIPS] Implement CACHEE and PREFE instructions for microMIPS32r6
Differential Revision: http://reviews.llvm.org/D11632


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247670 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-15 10:05:10 +00:00
Daniel Sanders
b57c2dc746 [mips] Added support for various EVA ASE instructions.
Summary:
Added support for the following instructions:

CACHEE, LBE, LBUE, LHE, LHUE, LWE, LLE, LWLE, LWRE, PREFE,
SBE, SHE, SWE, SCE, SWLE, SWRE, TLBINV, TLBINVF

This required adding some infrastructure for the EVA ASE.

Patch by Scott Egerton.

Reviewers: vkalintiris, dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11139


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247669 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-15 10:02:16 +00:00
Davide Italiano
125be70dbf [MC] Don't crash on division by zero.
Differential Revision:	http://reviews.llvm.org/D12776


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247471 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-11 20:47:35 +00:00
Daniel Sanders
5ab98c2cdf [mips] Add missing disassembler tests for MIPS64-MIPS64R5.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247422 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-11 16:24:11 +00:00
Daniel Sanders
79f755355c [mips] Add missing MIPS32 - MIPS32R5 disassembler tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247420 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-11 15:28:19 +00:00
Daniel Sanders
b43119d746 [mips] Attempt to fix llvm-s390x-linux1
It doesn't seem to like the '|&' in the test command.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247418 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-11 14:57:54 +00:00
Daniel Sanders
8aa6e22f95 [mips] Add missing MIPS-IV disassembler tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247417 91177308-0d34-0410-b5e6-96231b3b80d8
2015-09-11 14:54:58 +00:00