158094 Commits

Author SHA1 Message Date
Brian M. Rzycki
7cc3dcfb80 [JumpThreading] Preservation of DT and LVI across the pass
Summary:
See D37528 for a previous (non-deferred) version of this
patch and its description.

Preserves dominance in a deferred manner using a new class
DeferredDominance. This reduces the performance impact of
updating the DominatorTree at every edge insertion and
deletion. A user may call DDT->flush() within JumpThreading
for an up-to-date DT. This patch currently has one flush()
at the end of runImpl() to ensure DT is preserved across
the pass.

LVI is also preserved to help subsequent passes such as
CorrelatedValuePropagation. LVI is simpler to maintain and
is done immediately (not deferred). The code to perfom the
preversation was minimally altered and was simply marked
as preserved for the PassManager to be informed.

This extends the analysis available to JumpThreading for
future enhancements. One example is loop boundary threading.

Reviewers: dberlin, kuhar, sebpop

Reviewed By: kuhar, sebpop

Subscribers: hiraditya, llvm-commits

Differential Revision: https://reviews.llvm.org/D40146


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320612 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13 20:52:26 +00:00
Aditya Kumar
2bf4af887e [GVNHoist] Fix: PR35222 gvn-hoist incorrectly erases load
w.r.t. the paper
"A Practical Improvement to the Partial Redundancy Elimination in SSA Form"
(https://sites.google.com/site/jongsoopark/home/ssapre.pdf)

Proper dominance check was missing here, so having a loopinfo should not be required.
Committing this diff as this fixes the bug, if there are
further concerns, I'll be happy to work on them.

Differential Revision: https://reviews.llvm.org/D39781

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320607 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13 19:40:07 +00:00
Adrian Prantl
267645038a Ignore metainstructions during the shrink wrap analysis
Shrink wrapping should ignore DBG_VALUEs referring to frame indices,
since the presence of debug information must not affect code
generation.

Differential Revision: https://reviews.llvm.org/D41187

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320606 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13 19:10:54 +00:00
Jonas Devlieghere
99c0370531 [dsymutil][test] Fix failing test when no lipo binary available
The invocation without -no-output would try to lipo the different debug
objects together. This wouldn't work on platforms that don't provide
that utility.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320605 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13 18:35:39 +00:00
Simon Pilgrim
83f6d00755 [X86] Add JCC/JECXZ/JECXZ/JRCXZ/LOOP schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320603 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13 18:09:45 +00:00
Amaury Sechet
c1f4787343 Regenerate test-shrink.ll test results. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320602 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13 18:04:57 +00:00
Jonas Devlieghere
4cac1c471e [dsymutil] Re-enable threading
Threading was disabled in r317263 because it broke a test in combination
with `-DLLVM_ENABLE_THREADS=OFF`. This was because a ThreadPool warning
was piped to llvm-dwarfdump which was expecting to read an object from
stdin.

This patch re-enables threading and fixes the offending test.
Unfortunately this required more than just moving the ThreadPool out of
the for loop because of the TempFile refactoring that took place in the
meantime.

Differential revision: https://reviews.llvm.org/D41180

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320601 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13 18:03:04 +00:00
Simon Pilgrim
6149067b94 [X86] Add RET/RETF schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320600 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13 17:50:40 +00:00
Simon Pilgrim
d797d31140 [X86] Add POP/PUSH schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320598 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13 17:42:25 +00:00
Brian M. Rzycki
0bcc2cddd4 [Function] Remove trailing end-of-line whitespace. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320595 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13 16:56:18 +00:00
Nemanja Ivanovic
efb650695a Fix link failure on one build bot introduced by r320584.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320589 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13 15:28:01 +00:00
Galina Kistanova
e8e0a7cf7b Reverted r320229. It broke tests on builder llvm-clang-x86_64-expensive-checks-win.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320588 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13 15:26:27 +00:00
Simon Pilgrim
cd1040ad7c [X86] Add PREFETCH schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320587 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13 15:12:02 +00:00
Simon Pilgrim
39485b9013 [X86] Add XCHG schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320586 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13 15:02:10 +00:00
Simon Pilgrim
531cde9dc8 [X86] Add MOVNTI schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320585 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13 14:51:06 +00:00
Nemanja Ivanovic
7b053da09f [PowerPC] MachineSSA pass to reduce the number of CR-logical operations
The initial implementation of an MI SSA pass to reduce cr-logical operations.
Currently, the only operations handled by the pass are binary operations where
both CR-inputs come from the same block and the single use is a conditional
branch (also in the same block).

Committing this off by default to allow for a period of field testing. Will
enable it by default in a follow-up patch soon.

Differential Revision: https://reviews.llvm.org/D30431


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320584 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13 14:47:35 +00:00
Simon Pilgrim
a9fb896797 [X86] Add ENTER/LEAVE schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320583 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13 14:46:33 +00:00
Simon Pilgrim
4a0d45ff9b [X86] Add IMUL schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320582 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13 14:24:04 +00:00
Simon Pilgrim
2057bb76d7 [X86] Add RDMSR/WRMSR, RDPMC + RDTSC/RDTSCP schedule tests
Add missing RDTSCP itinerary

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320581 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13 14:22:04 +00:00
Simon Pilgrim
1cb7e40b26 [X86] Add ARPL/BOUND schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320580 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13 13:54:45 +00:00
Alex Bradbury
a3d1d5695a [RISCV] Define sfence.vma InstAliases to match the GNU RISC-V tools
Unfortunately these aren't defined explicitly in the privileged spec, but the
GNU assembler does accept `sfence.vma` and `sfence.vma rs` as well as the
usual `sfence.vma rs, rt`.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320575 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13 12:46:55 +00:00
Igor Laevsky
a3d1ab8186 [FuzzMutate] Only generate loads and stores to the first class sized types
Differential Revision: https://reviews.llvm.org/D41109



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320573 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13 11:49:04 +00:00
Igor Laevsky
95edead4fe [FuzzMutate] Avoid zero sized aggregates
Differential Revision: https://reviews.llvm.org/D41110



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320572 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13 11:47:35 +00:00
Igor Laevsky
033683a63f [FuzzMutate] Correctly split landingpad blocks
Differential Revision: https://reviews.llvm.org/D41112



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320571 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13 11:45:53 +00:00
Simon Pilgrim
6dc08a0926 [X86][SSE] MOVMSK only uses the sign bit from each vector element
Pass the input vector through SimplifyDemandedBits as we only need the sign bit from each vector element of MOVMSK

We'd probably get more hits if SimplifyDemandedBits was better at handling vectors...

Differential Revision: https://reviews.llvm.org/D41119

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320570 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13 11:43:14 +00:00
Alex Bradbury
d475c17e7b [RISCV] Implement floating point assembler pseudo instructions
Adds the assembler aliases for the floating point instructions
which can be mapped to a single canonical instruction. The missing
pseudo instructions (flw, fld, fsw, fsd) are marked as TODO. Other
things, like for example PCREL_LO, have to be implemented first.

This patch builds upon D40902.

Differential Revision: https://reviews.llvm.org/D41071

Patch by Mario Werner.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320569 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13 11:37:19 +00:00
Igor Laevsky
fcf12e077b Reintroduce r320049, r320014 and r319894.
OpenGL issues should be fixed by now.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320568 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13 11:21:18 +00:00
Roger Ferrer Ibanez
bc4037e1bb [DAG] Promote ADDCARRY / SUBCARRY
Add missing case that was not implemented yet.

Differential Revision: https://reviews.llvm.org/D38942



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320567 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13 10:45:21 +00:00
Francis Visoiu Mistrih
d347e9783d [CodeGen] Print jump-table index operands as %jump-table.0 in both MIR and debug output
Work towards the unification of MIR and debug output by printing `%jump-table.0` instead of `<jt#0>`.

Only debug syntax is affected.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320566 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13 10:30:59 +00:00
Francis Visoiu Mistrih
2b16863067 [CodeGen] Print target index operands as target-index(target-specific) + 8 in both MIR and debug output
Work towards the unification of MIR and debug output by printing `target-index(target-specific) + 8` instead of `<ti#0+8>` and `target-index(target-specific) + 8` instead of `<ti#0-8>`.

Only debug syntax is affected.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320565 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13 10:30:51 +00:00
Francis Visoiu Mistrih
c84690975a [CodeGen] Print constant pool index operands as %const.0 + 8 in both MIR and debug output
Work towards the unification of MIR and debug output by printing
`%const.0 + 8` instead of `<cp#0+8>` and `%const.0 - 8` instead of
`<cp#0-8>`.

Only debug syntax is affected.

Differential Revision: https://reviews.llvm.org/D41116

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320564 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13 10:30:45 +00:00
Stefan Maksimovic
061f5ff24a [mips] Provide additional DSP bitconvert patterns
Previously, v2i16 -> f32 bitcast could not be matched.
Add patterns to support matching this and similar types of bitcasts.

Differential revision: https://reviews.llvm.org/D40959


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320562 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13 10:13:35 +00:00
Pavel Labath
1f8ac167fe [Testing/Support] Make the HasValue matcher composable
Summary:
This makes it possible to run an arbitrary matcher on the value
contained within the Expected<T> object.

To do this, I've needed to fully spell out the matcher, instead of using
the shorthand MATCHER_P macro.

The slight gotcha here is that standard template deduction will fail if
one tries to match HasValue(47) against an Expected<int &> -- the
workaround is to use HasValue(testing::Eq(47)).

The explanations produced by this matcher have changed a bit, since now
we delegate to the nested matcher to print the value. Since these don't
put quotes around the value, I've changed our PrintTo methods to match.

Reviewers: zturner

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D41065

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320561 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13 10:00:38 +00:00
Alex Bradbury
6d0dcae300 [RISCV][NFC] Update RISCVInstrInfoC.td to match usual instruction naming convention
When an instruction mnemonic contains a '.', we usually name the instruction
with a _ in that place. e.g. fadd.s -> FADD_S.

This patch updates RISCVInstrInfoC.td to do the same, e.g. c.nop -> C_NOP.

Also includes some minor formatting changes in RISCVInstrInfoC.td to better
align it with the formatting conventions in the rest of the backend.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320560 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13 09:57:25 +00:00
Alex Bradbury
786bced330 [RISCV][NFC] Put isSImm6 and simm6 td definition in correct sorted position
We sort these helper functions and td definitions by bit width. simm6 was
previously out-of-order with respect to the others.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320559 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13 09:41:21 +00:00
Alex Bradbury
5774b87aa7 [RISCV] MC layer support for the remaining RVC instructions
Differential Revision: https://reviews.llvm.org/D40003

Patch by Shiva Chen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320558 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13 09:32:55 +00:00
Gadi Haber
4258537d45 [X86][BMI]: Adding full coverage of MC encoding for the BMI isa set.<NFC>
NFC.
Adding MC regressions tests to cover the BMI1 and BMI2 ISA sets both 32 and 64 bit.
This patch is part of a larger task to cover MC encoding of all X86 ISA Sets.
started in revision: https://reviews.llvm.org/D39952

Reviewers: zvi, craig.topper, m_zuckerman, RKSimon
Differential Revision: https://reviews.llvm.org/D41106

Change-Id: I033ce137b5b82d36e1e601cd5e0534637b43a4a9

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320557 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13 09:13:53 +00:00
Alex Bradbury
93b8ba08eb [cmake] Fix host tools build in when LLVM_EXPERIMENTAL_TARGETS_TO_BUILD is set
r320413 triggered cmake configure failures when building with 
-DLLVM_OPTIMIZED_TABLEGEN=True and with LLVM_EXPERIMENTAL_TARGETS_TO_BUILD set 
(e.g. to RISCV). This is because that patch moved to passing through 
LLVM_TARGETS_TO_BUILD, and at that point LLVM_EXPERIMENTAL_TARGETS_TO_BUILD 
has been merged in to it. LLVM_EXPERIMENTAL_TARGETS_TO_BUILD must be also be 
passed through to avoid errors like below:

-- Constructing LLVMBuild project information
CMake Error at CMakeLists.txt:682 (message):
  The target `RISCV' does not exist.

      It should be one of


  AArch64;AMDGPU;ARM;BPF;Hexagon;Lanai;Mips;MSP430;NVPTX;PowerPC;Sparc;SystemZ;X86;XCore


-- Configuring incomplete, errors occurred!

See the thread
http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20171211/509225.html 
for discussion of this fix.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320556 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13 09:02:13 +00:00
Serguei Katkov
407ce54852 Revert "[CGP] Enable select in complex addr mode"
Causes: Assertion `ScaledReg == nullptr' failed.

This actually a revert of rL320551.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320553 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13 07:39:35 +00:00
Craig Topper
56d08f7e75 [Targets] Don't automatically include the scheduler class enum from *GenInstrInfo.inc with GET_INSTRINFO_ENUM. Make targets request is separately.
Most of the targets don't need the scheduler class enum.

I have an X86 scheduler model change that causes some names in the enum to become about 18000 characters long. This is because using instregex in scheduler models causes the scheduler class to get named with every instruction that matches the regex concatenated together. MSVC has a limit of 4096 characters for an identifier name. Rather than trying to come up with way to reduce the name length, I'm just going to sidestep the problem by not including the enum in X86.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320552 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13 07:26:17 +00:00
Serguei Katkov
596e2d5bc4 [CGP] Enable select in complex addr mode
Enable select instruction handling in complex addr modes.

Reviewers: john.brawn, reames, aaboud
Reviewed By: reames
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D40634


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320551 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13 06:57:59 +00:00
Dean Michael Berris
69956ecc21 [XRay][compiler-rt] Reduce XRay log spam
This change makes XRay print the log file output only when the verbosity
level is higher than 0. It reduces the log spam in the default case when
we want XRay running silently, except when there are actual
fatal/serious errors.

We also update the documentation to show how to get the information
after the change to the default behaviour.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320550 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13 06:37:13 +00:00
Serguei Katkov
88e328af9d [NFC] Refactor SafepointIRVerifier
Now two classes are responsible for verification: one of them can track GC
pointers and know whether a pointer is relocated or not and another based on
that information can verify uses of GC pointers.

Patch Author: Daniil Suchkov
Reviewers: mkazantsev, anna, apilipenko
Reviewed By: mkazantsev
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D40885


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320549 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13 05:32:46 +00:00
Mohammad Shahid
fb6004239d [SLP] Vectorize jumbled memory loads.
Summary:
This patch tries to vectorize loads of consecutive memory accesses, accessed
in non-consecutive or jumbled way. An earlier attempt was made with patch D26905
which was reverted back due to some basic issue with representing the 'use mask' of
jumbled accesses.

This patch fixes the mask representation by recording the 'use mask' in the usertree entry.

Change-Id: I9fe7f5045f065d84c126fa307ef6ebe0787296df

Reviewers: mkuper, loladiro, Ayal, zvi, danielcdh

Reviewed By: Ayal

Subscribers: mgrang, dcaballe, hans, mzolotukhin

Differential Revision: https://reviews.llvm.org/D36130

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320548 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13 03:08:29 +00:00
Florian Hahn
bb04a0eeec [CallSiteSplitting] Refactor creating callsites.
Summary:
This change makes the call site creation more general if any of the
arguments is predicated on a condition in the call site's predecessors.

If we find a callsite, that potentially can be split, we collect the set
of conditions for the call site's predecessors (currently only 2
predecessors are allowed). To do that, we traverse each predecessor's
predecessors as long as it only has single predecessors and record the
condition, if it is relevant to the call site. For each condition, we
also check if the condition is taken or not. In case it is not taken,
we record the inverse predicate.

We use the recorded conditions to create the new call sites and split
the basic block.

This has 2 benefits: (1) it is slightly easier to see what is going on
(IMO) and (2) we can easily extend it to handle more complex control
flow.

Reviewers: davidxl, junbuml

Reviewed By: junbuml

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D40728

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320547 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13 03:05:20 +00:00
Matthias Braun
fa621d294f Rename LiveIntervalAnalysis.h to LiveIntervals.h
Headers/Implementation files should be named after the class they
declare/define.

Also eliminated an `#include "llvm/CodeGen/LiveIntervalAnalysis.h"` in
favor of `class LiveIntarvals;`

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320546 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13 02:51:04 +00:00
Matthias Braun
f09cbb9774 Remove unnecessary includes; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320545 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13 02:51:01 +00:00
Evgeniy Stepanov
3220c51b4c [hwasan] Inline instrumentation & fixed shadow.
Summary: This brings CPU overhead on bzip2 down from 5.5x to 2x.

Reviewers: kcc, alekseyshl

Subscribers: kubamracek, hiraditya, llvm-commits

Differential Revision: https://reviews.llvm.org/D41137

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320538 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13 01:16:34 +00:00
Michael Trent
87e8c32e0f reverting out -r320532 because a warning is breaking the lld build
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320534 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13 00:36:13 +00:00
Michael Trent
2aa4a861a6 Updated llvm-objdump to display local relocations in Mach-O binaries
Summary:
llvm-objdump's Mach-O parser was updated in r306037 to display external
relocations for MH_KEXT_BUNDLE file types. This change extends the Macho-O
parser to display local relocations for MH_PRELOAD files. When used with
the -macho option relocations will be displayed in a historical format.

rdar://35778019

Reviewers: enderby

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D41061

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320532 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-12 23:53:46 +00:00