185227 Commits

Author SHA1 Message Date
Kerry McLaughlin
48d00babac [SVE][Inline-Asm] Add constraints for SVE predicate registers
Summary:
Adds the following inline asm constraints for SVE:
  - Upl: One of the low eight SVE predicate registers, P0 to P7 inclusive
  - Upa: SVE predicate register with full range, P0 to P15

Reviewers: t.p.northover, sdesmalen, rovka, momchil.velikov, cameron.mcinally, greened, rengolin

Reviewed By: rovka

Subscribers: javed.absar, tschuett, rkruppe, psnobl, cfe-commits, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D66524

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371967 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-16 09:45:27 +00:00
Nico Weber
911a837b3d gn build: Merge r371965
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371966 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-16 09:43:26 +00:00
Nico Weber
7020cdb536 gn build: Merge r371959
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371961 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-16 07:34:23 +00:00
Sjoerd Meijer
71dc0b23c7 [AArch64] Some more FP16 FMA pattern matching
After our previous machinecombiner exercises (rL371321, rL371818, rL371833), we
were still missing a few FP16 FMA patterns.

Differential Revision: https://reviews.llvm.org/D67576

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371960 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-16 07:32:13 +00:00
Jonas Paulsson
0af6488be2 [SystemZ] Merge the SystemZExpandPseudo pass into SystemZPostRewrite.
SystemZExpandPseudo:s only job was to expand LOCRMux instructions into jump
sequences. This needs to be done if expandLOCRPseudo() or expandSELRPseudo()
fails to find a legal opcode (all registers "high" or "low"). This task has
now been moved to SystemZPostRewrite while removing the SystemZExpandPseudo
pass.

It is in fact preferred to expand these pseudos directly after register
allocation in SystemZPostRewrite since the hinted register combinations are
then not subject to later optimizations.

Review: Ulrich Weigand
https://reviews.llvm.org/D67432

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371959 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-16 07:29:37 +00:00
Matt Arsenault
7511280318 AMDGPU/GlobalISel: Remove illegal select tests
These fail in a release build.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371955 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-16 04:21:10 +00:00
Matt Arsenault
4cfc531c99 AMDGPU/GlobalISel: Select SMRD loads for more types
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371954 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-16 00:54:07 +00:00
Matt Arsenault
796815a826 AMDGPU/GlobalISel: RegBankSelect for kill
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371953 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-16 00:48:37 +00:00
Matt Arsenault
54dea4c5ee AMDGPU/GlobalISel: Legalize s1 source G_[SU]ITOFP
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371952 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-16 00:37:10 +00:00
Matt Arsenault
8917673a2f AMDGPU/GlobalISel: Set type on vgpr live in special arguments
Fixes assertion with workitem ID intrinsics used in non-kernel
functions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371951 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-16 00:33:00 +00:00
Matt Arsenault
83c97ac441 AMDGPU/GlobalISel: Select S16->S32 fptoint
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371950 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-16 00:32:56 +00:00
Matt Arsenault
cadee98a6c AMDGPU/GlobalISel: Select s32->s16 G_[US]ITOFP
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371949 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-16 00:29:12 +00:00
Matt Arsenault
832d1e1170 AMDGPU/GlobalISel: Fix VALU s16 fneg
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371948 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-16 00:20:54 +00:00
Stefan Stipanovic
e342d834af [Attributor] Heap-To-Stack Conversion
D53362 gives a prototype heap-to-stack conversion pass. With addition of new attributes in the attributor, this can now be revisted and improved. This will place it in the Attributor to make it easier to use new attributes (eg. nofree, nosync, willreturn, etc.) and other attributor features.

Reviewers: jdoerfert, uenoku, hfinkel, efriedma

Subscribers: lebedev.ri, xbolva00, hiraditya, llvm-commits

Differential Revision: https://reviews.llvm.org/D65408

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371942 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-15 21:47:41 +00:00
Sanjay Patel
3050f70ce7 [InstCombine] remove unneeded one-use checks for icmp fold
This fold and several others were added in:
rL125734
...with no explanation for the one-use checks other than the code
comments about register pressure.

Given that this is IR canonicalization, we shouldn't be worried
about register pressure though; the backend should be able to
adjust for that as needed.

There are similar checks as noted with the TODO comments. I'm
hoping to remove those restrictions too, but if any of these
does cause a regression, it should be easier to correct by making
small, individual commits.

This is part of solving PR43310 the theoretically right way:
https://bugs.llvm.org/show_bug.cgi?id=43310
...ie, if we don't cripple basic transforms, then we won't
need to add special-case code to detect larger patterns.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371940 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-15 20:56:34 +00:00
Sanjay Patel
81ce279f2b [InstCombine] add icmp tests with extra uses; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371939 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-15 20:13:27 +00:00
Jinsong Ji
137a26a97a [PowerPC][NFC] Add a testcase for fdiv expansion.
Pre-commit for following patch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371938 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-15 20:02:25 +00:00
Simon Pilgrim
21ae772991 [GlobalISel] findGISelOptimalMemOpLowering - remove dead initalization. NFCI.
Fixes static analyzer warning that "Value stored to 'NewTySize' during its initialization is never read".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371937 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-15 16:56:06 +00:00
Simon Pilgrim
81bcd7a858 [LoadStoreVectorizer] vectorizeLoadChain - ensure we find a valid Type down the load chain. NFCI.
Silence static analyzer uninitialized variable warning by setting the LoadTy to null and then asserting we find a real value.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371936 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-15 16:44:35 +00:00
Simon Pilgrim
5c8f5359c9 InterleavedLoadCombine - merge isa<> and dyn_cast<> duplicates. NFCI.
Silence static analyzer null dereference warning of *dyn_cast<BinaryOperator> by merging with the isa<BinaryOperator> above.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371935 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-15 16:20:12 +00:00
Simon Pilgrim
07c764097f [DebugInfo] Don't dereference a dyn_cast<PDBSymbolData> result. NFCI.
The static analyzer is warning about a potential null dereference - but as we're in DataMemberLayoutItem we should be able to guarantee that the Symbol is a PDBSymbolData type, allowing us to use cast<PDBSymbolData> - and if not assert will fire for us.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371933 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-15 15:38:26 +00:00
David Green
f343dcd487 [ARM] Masked loads and stores
Masked loads and store fit naturally with MVE, the instructions being easily
predicated. This adds lowering for the simple cases of masked loads and stores.
It does not yet deal with widening/narrowing or pre/post inc, and so is
currently behind an option.

The llvm masked load intrinsic will accept a "passthru" value, dictating the
values used for the zero masked lanes. In MVE the instructions write 0 to the
zero predicated lanes, so we need to match a passthru that isn't 0 (or undef)
with a select instruction to pull in the correct data after the load.

Differential Revision: https://reviews.llvm.org/D67186


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371932 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-15 14:14:47 +00:00
Sanjay Patel
71f28d66dd [SLP] limit vectorization of Constant subclasses (PR33958)
This is a fix for:
https://bugs.llvm.org/show_bug.cgi?id=33958

It seems universally true that we would not want to transform this kind of
sequence on any target, but if that's not correct, then we could view this
as a target-specific cost model problem. We could also white-list ConstantInt,
ConstantFP, etc. rather than blacklist Global and ConstantExpr.

Differential Revision: https://reviews.llvm.org/D67362

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371931 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-15 13:03:24 +00:00
David Green
2d52f8b93f [ARM] Simplify and update vmla test. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371930 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-15 11:53:05 +00:00
James Molloy
305c516b15 [CodeEmitter] Improve testing for APInt encoding
I missed Artem's comment in D67487 before committing.

Differential Revision: https://reviews.llvm.org/D67487

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371929 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-15 08:44:40 +00:00
James Molloy
41e3905aa8 [CodeEmitter] Support instruction widths > 64 bits
Some VLIW instruction sets are Very Long Indeed. Using uint64_t constricts the Inst encoding to 64 bits (naturally).

This change switches CodeEmitter to a mode that uses APInts when Inst's bitwidth is > 64 bits (NFC for existing targets).

When Inst.BitWidth > 64 the prototype changes to:

  void TargetMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,
                                                  SmallVectorImpl<MCFixup> &Fixups,
                                                  APInt &Inst,
                                                  APInt &Scratch,
                                                  const MCSubtargetInfo &STI);

The Inst parameter returns the encoded instruction, the Scratch parameter is used internally for manipulating operands and is exposed so that the underlying storage can be reused between calls to getBinaryCodeForInstr. The goal is to elide any APInt constructions that we can.

Similarly the operand encoding prototype changes to:

  getMachineOpValue(const MCInst &MI, const MCOperand &MO, APInt &op, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI);

That is, the operand is passed by reference as APInt rather than returned as uint64_t.

To reiterate, this APInt mode is enabled only when Inst.BitWidth > 64, so this change is NFC for existing targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371928 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-15 08:35:08 +00:00
Simon Pilgrim
88ae6d603d [TargetLowering] SimplifyDemandedBits - add EXTRACT_SUBVECTOR support.
Call SimplifyDemandedBits on the source vector.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371923 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-14 16:38:26 +00:00
Roman Lebedev
b29a186992 [InstSimplify] simplifyUnsignedRangeCheck(): handle few tautological cases (PR43251)
Summary:
This is split off from D67356, since these cases produce a constant,
no real need to keep them in instcombine.

Alive proofs:
https://rise4fun.com/Alive/u7Fk
https://rise4fun.com/Alive/4lV

https://bugs.llvm.org/show_bug.cgi?id=43251

Reviewers: spatel, nikic, xbolva00

Reviewed By: spatel

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D67498

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371921 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-14 13:47:27 +00:00
Mingjie Xing
ff031dcbec [ScheduleDAGMILive] Fix typo in comment.
Differential Revision: https://reviews.llvm.org/D67478

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371916 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-14 03:27:38 +00:00
Johannes Doerfert
60c9595c32 [Attributor][Fix] Use right type to replace expressions
Summary: This should be obsolete once the functionality in D66967 is integrated.

Reviewers: uenoku, sstefan1

Subscribers: hiraditya, bollu, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D67231

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371915 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-14 02:57:50 +00:00
Fangrui Song
f6dc13fa4d [llvm-objcopy] Ignore -B --binary-architecture=
GNU objcopy documents that -B is only useful with architecture-less
input (i.e. "binary" or "ihex"). After D67144, -O defaults to -I, and
-B is essentially a NOP.

* If -O is binary/ihex, GNU objcopy ignores -B.
* If -O is elf*, -B provides the e_machine field in GNU objcopy.

So to convert a blob to an ELF, `-I binary -B i386:x86-64 -O elf64-x86-64` has to be specified.

`-I binary -B i386:x86-64 -O elf64-x86-64` creates an ELF with its
e_machine field set to EM_NONE in GNU objcopy, but a regular x86_64 ELF
in elftoolchain elfcopy. Follow the elftoolchain approach (ignoring -B)
to simplify code. Users that expect their command line portable should
specify -B.

Reviewed By: jhenderson

Differential Revision: https://reviews.llvm.org/D67215

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371914 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-14 01:36:31 +00:00
Fangrui Song
9c01fe0563 [llvm-objcopy] Default --output-target to --input-target when unspecified
Fixes PR42171.

In GNU objcopy, if -O (--output-target) is not specified, the value is
copied from -I (--input-target).

```
objcopy -I binary -B i386:x86-64 a.txt b       # b is copied from a.txt
llvm-objcopy -I binary -B i386:x86-64 a.txt b  # b is an x86-64 object file
```

This patch changes our behavior to match GNU. With this change, we can
delete code related to -B handling (D67215).

Reviewed By: jakehehrlich

Differential Revision: https://reviews.llvm.org/D67144

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371913 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-14 01:36:16 +00:00
Fangrui Song
c66dffe703 [llvm-ar] Uncapitalize error messages and delete full stop
Most GNU binutils don't append full stops in error messages. This
convention has been adopted by a bunch of LLVM binary utilities. Make
llvm-ar follow the convention as well.

Reviewed By: grimar

Differential Revision: https://reviews.llvm.org/D67558

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371912 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-14 01:18:47 +00:00
Michael Pozulp
78308f70b2 [llvm-objcopy] Add support for response files in llvm-strip and llvm-objcopy
Summary: Addresses https://bugs.llvm.org/show_bug.cgi?id=42671

Reviewers: jhenderson, espindola, alexshap, rupprecht

Reviewed By: jhenderson

Subscribers: seiya, emaste, arichardson, jakehehrlich, MaskRay, abrachet, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D65372

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371911 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-14 01:14:43 +00:00
David Blaikie
5ca8fbd7ef Bugpoint: Remove some unnecessary c_str conversions on the journey to StringRef
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371910 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-14 00:32:13 +00:00
Jonas Devlieghere
aaf4ee2197 [Reproducer] Add reproducer dump command.
This adds a reproducer dump commands which makes it possible to inspect
a reproducer from inside LLDB. Currently it supports the Files, Commands
and Version providers. I'm planning to add support for the GDB Remote
provider in a follow-up patch.

Differential revision: https://reviews.llvm.org/D67474

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371909 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-13 23:27:31 +00:00
Thomas Lively
f308fdbdc6 [WebAssembly] Narrowing and widening SIMD ops
Summary:
Implements target-specific LLVM intrinsics and clang builtins for
these new SIMD operations, as described at https://github.com/WebAssembly/simd/blob/master/proposals/simd/SIMD.md#integer-to-integer-narrowing.

Reviewers: aheejin

Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, sunfish, cfe-commits, llvm-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D67425

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371906 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-13 22:54:41 +00:00
Amara Emerson
233794f3c7 [GlobalISel] Fix insertion point of new instructions to be after PHIs.
For some reason we sometimes insert new instructions one instruction before
the first non-PHI when legalizing. This can result in having non-PHI
instructions before PHIs, which mean that PHI elimination doesn't catch them.

Differential Revision: https://reviews.llvm.org/D67570

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371901 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-13 21:49:24 +00:00
Steven Wu
c3a231df10 [NFC][libLTO] Rearrange declaration in lto.h
Summary:
Rearrange the function declaration in lto.h so they falls in the correct
doxygen group.

Reviewers: tejohnson, bd1976llvm, deadalnix

Reviewed By: tejohnson

Subscribers: mehdi_amini, inglorion, jkorous, dexonsmith, ributzka, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D67565

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371900 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-13 21:19:12 +00:00
Sanjoy Das
7cc478846a Add dependency from Orc to Passes
Summary: Orc uses registerFunctionAnalyses that's defined in Passes.

Reviewers: dblaikie

Subscribers: mcrosier, bixia, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D67477

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371898 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-13 21:07:56 +00:00
Francis Visoiu Mistrih
7ab0a1882b [llvm-opt-report] Improve error handling
* std::move the error extracted from the parsing creation to avoid asserts
* print a newline after the error message
* create the parser from the metadata

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371895 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-13 20:52:04 +00:00
Jessica Paquette
23e464e395 [AArch64][GlobalISel] Tail call memory intrinsics
Because memory intrinsics are handled differently than other calls, we need to
check them for tail call eligiblity in the legalizer. This allows us to still
inline them when it's beneficial to do so, but also tail call when possible.

This adds simple tail calling support for when the intrinsic is followed by a
return.

It ports the attribute checks from `TargetLowering::isInTailCallPosition` into
a similarly-named function in LegalizerHelper.cpp. The target-specific
`isUsedByReturnOnly` hook is not ported here.

Update tailcall-mem-intrinsics.ll to show that GlobalISel can now tail call
memory intrinsics.

Update legalize-memcpy-et-al.mir to have a case where we don't tail call.

Differential Revision: https://reviews.llvm.org/D67566

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371893 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-13 20:25:58 +00:00
Jan Korous
b64af0b5e2 [Support] Add overload writeFileAtomically(std::function Writer)
Differential Revision: https://reviews.llvm.org/D67424

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371890 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-13 20:08:27 +00:00
DeForest Richards
32baccf419 [Docs] Bug fix for reference to nonexistent document
This commit fixes a bug in which the toctree contained a reference to a non-existent document.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371889 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-13 20:05:57 +00:00
Kevin P. Neal
3faa9ad7e9 [FPEnv] Document that constrained FP intrinsics cannot be mixed with non-constrained
Reviewed by:	andrew.w.kaylor, cameron.mcinally, uweigand
Approved by:	andrew.w.kaylor
Differential Revision:	https://reviews.llvm.org/D67360


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371888 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-13 19:36:19 +00:00
Sebastian Pop
c72d55a2df [aarch64] move custom isel of extract_vector_elt to td file - NFC
In preparation for def-pat selection of dot product instructions,
this patch moves the custom instruction selection of extract_vector_elt
to the td file. Without this change it is impossible to catch a pattern that
starts with an extract_vector_elt: the custom cpp code is executed first
ahead of the patterns in the td files that are only executed at the end of
the switch statement in SelectCode(Node).

With this patch applied, it becomes possible to select a different pattern
that starts with extract_vector_elt by selecting a higher complexity than
this pattern.

The patch has been tested on aarch64-linux with make check-all.

Differential Revision: https://reviews.llvm.org/D67497

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371887 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-13 19:28:30 +00:00
Tim Northover
65e57a3b1a AArch64: fix EXPENSIVE_CHECKS for arm64_32.
For some reason I'd decided to mark the end-result of a GOT load as
dead. It's clearly not (necessarily).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371883 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-13 18:55:38 +00:00
Sanjay Patel
942cafda25 [SLP] add test for vectorization of constant expressions; NFC
Goes with D67362.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371879 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-13 18:33:02 +00:00
Roman Lebedev
874e266750 [NFC][InstSimplify] Add some more tests for D67498/D67502
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371877 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-13 17:58:24 +00:00
Alexander Timofeev
f884885482 Revert for: [AMDGPU]: PHI Elimination hooks added for custom COPY insertion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371873 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-13 17:37:30 +00:00