163514 Commits

Author SHA1 Message Date
Simon Pilgrim
83e2d95494 [X86][SKX] Setup WriteFAdd and remove unnecessary InstRW scheduler overrides.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330813 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-25 10:51:19 +00:00
Simon Pilgrim
beba25ef7b [X86][SNB] Remove unnecessary WriteFBlendLd InstRW scheduler overrides.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330812 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-25 10:50:39 +00:00
Andrea Di Biagio
b7acab1156 [llvm-mca] run clang-format on a bunch of files. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330811 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-25 10:27:30 +00:00
Simon Dardis
5ce6b66393 [mips] Fix the definition of sync, synci
Also, fix the disassembly of synci for microMIPS.

Reviewers: abeserminji, smaksimovic, atanasyan

Differential Revision: https://reviews.llvm.org/D45870


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330810 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-25 10:19:22 +00:00
Andrea Di Biagio
e508042fca [llvm-mca] Default to the native host cpu if flag -mcpu is not specified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330809 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-25 10:18:25 +00:00
Andrea Di Biagio
8155479799 [llvm-mca] Remove method Instruction::isZeroLatency(). NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330807 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-25 09:38:58 +00:00
Florian Hahn
7fa40771cd [LoopInterchange] Use getExitBlock()/getExitingBlock instead of manual impl.
This also means we have to check if the latch is the exiting block now,
as `transform` expects the latches to be the exiting blocks too.

https://bugs.llvm.org/show_bug.cgi?id=36586

Reviewers: efriedma, davide, karthikthecool

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D45279


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330806 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-25 09:35:54 +00:00
Sander de Smalen
4dbfefddbb [AArch64][SVE] Asm: Add AsmOperand classes for SVE gather/scatter addressing modes.
This patch adds parsing support for 'vector + shift/extend' and
corresponding asm operand classes, needed for implementing SVE's
gather/scatter addressing modes.

The added combinations of vector (ZPR) and Shift/Extend are:

Unscaled:
  ZPR64ExtLSL8:           signed 64-bit offsets  (z0.d)
  ZPR32ExtUXTW8:        unsigned 32-bit offsets  (z0.s, uxtw)
  ZPR32ExtSXTW8:          signed 32-bit offsets  (z0.s, sxtw)

Unpacked and unscaled:
  ZPR64ExtUXTW8:        unsigned 32-bit offsets  (z0.d, uxtw)
  ZPR64ExtSXTW8:          signed 32-bit offsets  (z0.d, sxtw)

Unpacked and scaled:
  ZPR64ExtUXTW<scale>:  unsigned 32-bit offsets  (z0.d, uxtw #<shift>)
  ZPR64ExtSXTW<scale>:    signed 32-bit offsets  (z0.d, sxtw #<shift>)

Scaled:
  ZPR32ExtUXTW<scale>:  unsigned 32-bit offsets  (z0.s, uxtw #<shift>)
  ZPR32ExtSXTW<scale>:    signed 32-bit offsets  (z0.s, sxtw #<shift>)
  ZPR64ExtLSL<scale>:   unsigned 64-bit offsets  (z0.d,  lsl #<shift>)
  ZPR64ExtLSL<scale>:     signed 64-bit offsets  (z0.d,  lsl #<shift>)


Patch [1/3] in series to add support for SVE's gather load instructions
that use scalar+vector addressing modes:
- Patch [1/3]: https://reviews.llvm.org/D45951
- Patch [2/3]: https://reviews.llvm.org/D46023
- Patch [3/3]: https://reviews.llvm.org/D45958

Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, t.p.northover, echristo, evandro, javed.absar

Reviewed By: fhahn

Differential Revision: https://reviews.llvm.org/D45951



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330805 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-25 09:26:47 +00:00
Bjorn Pettersson
925ebe7327 [DebugInfo] Invalidate debug info in ReassociatePass::RewriteExprTree
Summary:
When Reassociate is rewriting an expression tree it may
reuse old binary expression nodes, for new expressions.
Whenever an expression node is reused, but with a non-trivial
change in the result, we need to invalidate any debug info
that is associated with the node.

If for example rewriting
  x = mul a, b
  y = mul c, x
into
  x = mul c, b
  y = mul a, x
we still get the same result for 'y', but 'x' is a new expression.
All debug info referring to 'x' must be invalidated (marked as
optimized out) since we no longer calculate the expected value.

As a side-effect this patch avoid (at least some) problems where
reassociate could end up creating IR with debug-use before def.
Earlier the dbg.value nodes where left untouched in the IR, while
the reused binary nodes where sinked to just before the root node
of the rewritten expression tree. See PR27273 for more info about
such problems.

Reviewers: dblaikie, aprantl, dexonsmith

Reviewed By: aprantl

Subscribers: JDevlieghere, llvm-commits

Tags: #debug-info

Differential Revision: https://reviews.llvm.org/D45975

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330804 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-25 09:23:56 +00:00
Craig Topper
57fd3bde97 [TableGen] Fix bad indentation in tablegen output file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330801 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-25 06:24:51 +00:00
David Bolvansky
f861cfb472 Merging r46043:
------------------------------------------------------------------------


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330799 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-25 04:33:36 +00:00
Craig Topper
54a51fd6b1 [X86] Auto-generate complete checks. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330797 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-25 03:40:45 +00:00
Geoff Berry
b99fab9a2a [DivRemPairs] Fix non-determinism in use list order.
Summary:
Use a MapVector instead of a DenseMap for RemMap since it is iteratated
over and the order of iteration can effect the order that new
instructions are created.  This can in turn effect the use list order of
div/rem input values if multiple new instructions are created that share
any input values.

Reviewers: spatel

Subscribers: mcrosier, llvm-commits

Differential Revision: https://reviews.llvm.org/D45858

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330792 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-25 02:17:56 +00:00
Chandler Carruth
685477eba1 [PM/LoopUnswitch] Begin teaching SimpleLoopUnswitch to use the new
update API for dominators rather than doing manual, hacky updates.

This is just the first step, but in some ways the most important as it
moves the non-trivial unswitching to update the domtree rather than
fully recalculating it each time.

Subsequent patches should remove the custom update logic used by the
trivial unswitch and replace it with uses of the update API.

This also fixes a number of bugs I was seeing when testing non-trivial
unswitch due to it querying the quasi-correct dominator tree. Now the
tree is 100% correct and safe to query. That said, there are still more
bugs I can see with non-trivial unswitch just running over the test
suite, so more bugfix patches are needed as well.

Thanks to both Sanjoy and Fedor for reviews and testing!

Differential Revision: https://reviews.llvm.org/D45943

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330787 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-25 00:18:07 +00:00
Jessica Paquette
bd42bc726f [MachineOutliner] Check for explicit uses of LR/W30 in MI operands
Before, the outliner would grab ADRPs that used LR/W30. This patch fixes
that by checking for explicit uses of those registers before the special-casing
for ADRPs.

This also adds a test that ensures that those sorts of ADRPs won't be outlined.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330783 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-24 22:38:15 +00:00
Craig Topper
df527edd37 [DAGCombiner][X86] When promoting loads don't use ZEXTLOAD even its legal
We were previously prefering ZEXTLOAD over EXTLOAD if it is legal. This triggers during X86's promotion of i16->i32. Not sure about other targets.

Using ZEXTLOAD can prevent folding it to SEXTLOAD later if we were to promote a sign extended operand like we would need for SRA. However, X86 doesn't currently promote i16 SRA. I was looking into doing that which is how I found this issue.

This is also blocking our ability to fold 4 byte aligned EXTLOADs with "loadi32". This is what caused most of the test changes here.

Differential Revision: https://reviews.llvm.org/D45585#inline-402825

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330781 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-24 22:35:27 +00:00
Reid Kleckner
16e61f3c89 Fix path separator checks on Windows
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330779 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-24 22:03:07 +00:00
Warren Ristow
17c3c08083 [X86] Account for partial stack slot spills (PR30821)
Previously, _any_ store or load instruction was considered to be
operating on a spill if it had a frameindex as an operand, and thus
was fair game for optimisations such as "StackSlotColoring". This
usually works, except on architectures where spills can be partially
restored, for example on X86 where a spilt vector can have a single
component loaded (zeroing the rest of the target register). This can be
mis-interpreted and the zero extension unsoundly eliminated, see
pr30821.

To avoid this, this commit optionally provides the caller to
isLoadFromStackSlot and isStoreToStackSlot with the number of bytes
spilt/loaded by the given instruction. Optimisations can then determine
that a full spill followed by a partial load (or vice versa), for
example, cannot necessarily be commuted.

Patch by Jeremy Morse!

Differential Revision: https://reviews.llvm.org/D44782


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330778 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-24 22:01:50 +00:00
Alexander Shaposhnikov
86e361fbbc [llvm-objcopy] Adjust the help message
Capitalize the first letter, 
make the text a bit more consistent.
NFC.

Differential revision: https://reviews.llvm.org/D46025



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330777 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-24 21:44:13 +00:00
Reid Kleckner
1305929829 Bring back APInt self-move assignment check for MSVC only
Summary:
It was removed about a year ago in r300477. Bring it back, along with
its unittest, when the MSVC STL is in use. The MSVC STL performs
self-assignment in std::shuffle. These days, llvm::sort calls
std::shuffle when expensive checks are enabled to help find
non-determinism bugs.

Reviewers: craig.topper, chandlerc

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D46028

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330776 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-24 21:41:50 +00:00
Tom Stellard
e843f71e41 AMDGPU: Remove deprecated llvm.AMDGPU.kilp intrinsic
Summary: This is no longer used by mesa since its 18.0.0 release.

Reviewers: nhaehnle

Reviewed By: nhaehnle

Subscribers: arsenm, kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye

Differential Revision: https://reviews.llvm.org/D45988

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330775 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-24 21:37:57 +00:00
Tom Stellard
5011204f5c AMDGPU/GlobalISel: Fall-back to SelectionDAG for non-void functions
Reviewers: arsenm, nhaehnle

Reviewed By: nhaehnle

Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D45843

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330774 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-24 21:29:36 +00:00
Mandeep Singh Grang
727ef0e543 [docs] Add a note on non-deterministic sorting order of equal elements
Reviewers: RKSimon, t.p.northover, dexonsmith

Reviewed By: RKSimon

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D45831

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330773 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-24 21:25:57 +00:00
Roman Lebedev
ebab8e7d8d [X86][AArch64][NFC] Add tests for masked merge unfolding with %y = const
The fold was added in D45733.

This appears to be a regression.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330771 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-24 21:23:22 +00:00
Daniel Neilson
608fcd9862 [CaptureTracking] Fixup const correctness of DomTree arg (NFC)
Summary:
The PointerMayBeCapturedBefore function's DomTree arg should be
const instead of non-const. There are no non-const uses of it
in the function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330769 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-24 21:12:45 +00:00
Sanjay Patel
98befe3296 [InstCombine] move tests for select with bit-test of condition; NFC
These are all but 1 of the select-of-constant tests that appear 
to be transformed within foldSelectICmpAnd() and the block above 
it predicated by decomposeBitTestICmp().

As discussed in D45862 (and can be seen in several tests here),
we probably want to stop doing those transforms because they
can increase the instruction count without benefitting other
passes or codegen.

The 1 test not included here is a urem test where the bit hackery
allows us to remove a urem. To preserve killing that urem, we 
should do some stronger known-bits analysis or pattern matching of 
'urem x, (select-of-pow2-constants)'.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330768 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-24 21:06:06 +00:00
Tom Stellard
1fb60f8e00 AMDGPU/GlobalISel: Add support for amdgpu_ps calling convention
Reviewers: arsenm

Reviewed By: arsenm

Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D45837

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330767 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-24 20:51:28 +00:00
Chandler Carruth
8801c5f87b [wasm] Fix uninitialized memory introduced in r330749.
Found with MSan. This was causing all the WASM MC tests to fail about
10% of the time.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330764 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-24 20:30:56 +00:00
Rafael Espindola
46e550273c [bugpoint] Fix crash when testing for miscompilation.
Method BugDriver::performFinalCleanups(...) would delete Module object
it worked on, which was also deleted by its caller
(e.g. TestCodeGenerator(...)). Changed the code to avoid double delete
and make Module ownership slightly clearer.

Patch by Andrzej Janik.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330763 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-24 20:15:27 +00:00
Sam McCall
620db41ce7 [Support] fix countLeadingZeros for types shorter than int
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330762 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-24 20:08:05 +00:00
Shoaib Meenai
210f16960b [cmake] Fix libc++ detection
-stdlib=libc++ is added to both the compilation and the link flags, but
the logic for adding it was only checking if it was supported during
compilation and not linking. This could lead to false positives, for
example when using clang with libstdc++ (where the compiler would
support -stdlib=libc++ but then linking would fail because of libc++
actually being unavailable).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330761 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-24 19:47:39 +00:00
Simon Pilgrim
c8da0cf0f0 [X86][SKX] Setup WriteFMul and remove unnecessary InstRW scheduler overrides.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330760 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-24 19:22:01 +00:00
Vedant Kumar
422ac9ee80 [test] Update llc checks for CodeGen/X86/avg.ll
The output of update_llc_test_checks.py on this test file has changed,
so the test file should be updated to minimize source changes in future
patches.

The test updates for this file appear to be limited to relaxations of
the form:

  -; SSE2-NEXT:    movq %rdi, -{{[0-9]+}}(%rsp) # 8-byte Spill
  +; SSE2-NEXT:    movq %rdi, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill

This was suggested in https://reviews.llvm.org/D45995.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330758 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-24 19:20:18 +00:00
Andrea Di Biagio
33b053f159 [llvm-mca] Remove unused flag -verbose. NFC
I forgot to remove it at r329794.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330757 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-24 19:14:56 +00:00
Simon Pilgrim
4882062d7b [X86] Split off PHMINPOSUW to their own schedule class
This also fixes Jaguar's schedule which was treating it as the WriteVecIMul default. 

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330756 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-24 18:49:25 +00:00
Joel E. Denny
c2a684aafa [lit] Report line number for failed RUN command
When debugging test failures with -vv (or -v in the case of the
internal shell), this makes it easier to locate the RUN line that
failed.  For example, clang's test/Driver/linux-ld.c has 892 total RUN
lines, and clang's test/Driver/arm-cortex-cpus.c has 424 RUN lines
after concatenation for line continuations.

When reading the generated shell script, this also makes it easier to
locate the RUN line that produced each command.

To support reporting RUN line numbers in the case of the internal
shell, this patch extends the internal shell to support the null
command, ":", except pipelines are not supported.

Reviewed By: asmith, delcypher

Differential Revision: https://reviews.llvm.org/D44598

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330755 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-24 18:43:25 +00:00
Stanislav Mekhanoshin
dbe20f7ece [AMDGPU] Truncate packed inline constant
If a packed inline constant is sign extended it must be truncated
after the shift. I.e. a constant (0xH0000, 0xHBC00), will be represented
as 0xFFFFFFFFBC000000 in the IR because the immediate is sign extended
to 64 bit. After the value shifted right by 16 to use it in a low part
with op_sel_hi it becomes 0xFFFFFFFFBC00 and does not qualify as inline
constant any longer.

Fixed the error and added verification code. Without the fix and with
the verification bug is causing pk_max_f16_literal.ll to fail.

Differential Revision: https://reviews.llvm.org/D45987

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330752 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-24 18:17:55 +00:00
Simon Pilgrim
37c88ba012 [XOP] v4i32 IFMA 'VPMACS' instructions should use the WritePMULLD schedule class
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330751 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-24 18:13:57 +00:00
Sam Clegg
194a4e0c23 [WebAssembly] Use section index in relocation section header
Rather than referring to sections my their code, use the
absolute index of the target section within the module.

See https://github.com/WebAssembly/tool-conventions/issues/52

Differential Revision: https://reviews.llvm.org/D45980

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330749 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-24 18:11:36 +00:00
Florian Hahn
0e90219cfd [LoopInterchange] Add REQUIRES: asserts to test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330748 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-24 18:10:52 +00:00
Simon Pilgrim
9596ad894f [AVX512] VPERMQ/VPERMPD/VPERMIL single op shuffles are not variable shuffles
These variants all take an immediate shuffle mask value and should be scheduled as such.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330747 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-24 17:59:54 +00:00
Nico Weber
f8dd899c6c Let TableGen write output only if it changed, instead of doing so in cmake.
Removes one subprocess and one temp file from the build for each tablegen
invocation.

No intended behavior change.

https://reviews.llvm.org/D45899


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330742 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-24 17:29:05 +00:00
Simon Dardis
f2df8a65f4 Reland "[mips] Guard traps for microMIPS correctly"
This is part of fixing the instruction predicates for MIPS.

Reviewers: atanasyan, abeserminji

Differential Revision: https://reviews.llvm.org/D44212


This patch relands r327409, hopefully without the problematic part of the
tests that cause FileCheck to assert on the windows expensive checks bot.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330741 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-24 17:11:37 +00:00
Diego Caballero
e8b06de378 [LV][VPlan] Detect outer loops for explicit vectorization.
Patch #2 from VPlan Outer Loop Vectorization Patch Series #1
(RFC: http://lists.llvm.org/pipermail/llvm-dev/2017-December/119523.html).

This patch introduces the basic infrastructure to detect, legality check
and process outer loops annotated with hints for explicit vectorization.
All these changes are protected under the feature flag
-enable-vplan-native-path. This should make this patch NFC for the existing
inner loop vectorizer.

Reviewers: hfinkel, mkuper, rengolin, fhahn, aemerson, mssimpso.

Differential Revision: https://reviews.llvm.org/D42447


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330739 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-24 17:04:17 +00:00
Florian Hahn
5e83467a58 [LoopInterchange] Make isProfitableForVectorization slightly more conservative.
After D43236, we started interchanging loops with empty dependence
matrices.  In isProfitableForVectorization, we try to determine if
interchanging makes the loop dependences more friendly to the
vectorizer. If there are no dependences, we should not interchange,
based on that heuristic.

Reviewers: efriedma, mcrosier, karthikthecool, blitz.opensource

Reviewed By: mcrosier

Differential Revision: https://reviews.llvm.org/D45208


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330738 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-24 16:55:32 +00:00
Simon Pilgrim
59def0db59 [X86][F16C] Add WriteCvtF2FSt scheduling class
Fixes the classification of VCVTPS2PHmr/VCVTPS2PHYmr which were tagged as WriteCvtF2FLd_WriteRMW (PR36887)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330737 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-24 16:43:07 +00:00
Fangrui Song
7fe67cc2ad [ADT] Remove ilist_default_traits
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330736 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-24 16:32:55 +00:00
Simon Pilgrim
f862b68e42 [X86][BtVer2] Fix VCVTPS2PHmr/VCVTPS2PHYmr latencies
These are stores, not loads, so don't need to account for load latency.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330735 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-24 16:26:51 +00:00
Simon Pilgrim
7d78f54577 [X86][IVB] Add F16C resource tests.
Note this is IvyBridge (which shares the model) NOT SandyBridge.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330734 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-24 16:22:59 +00:00
Andrea Di Biagio
9830843b26 [llvm-mca] Default the output asm dialect used by the instruction printer to the input asm dialect.
The instruction printer used by llvm-mca to generate the performance report now
defaults the output assembly format to the format used for the input assembly
file.

On x86, the asm format can be either AT&T or Intel, depending on the
presence/absence of directive `.intel_syntax`.

Users can still specify a different assembly dialect with the command line flag
-output-asm-variant=<uint>.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330733 91177308-0d34-0410-b5e6-96231b3b80d8
2018-04-24 16:19:08 +00:00