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32 Commits

Author SHA1 Message Date
Evan Cheng
ffbaccae02 No more noResults. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40132 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-21 00:34:19 +00:00
Evan Cheng
64d80e3387 Change instruction description to split OperandList into OutOperandList and 
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr  : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr  : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-19 01:14:50 +00:00
Andrew Lenharth
15b7823006 Use this nifty Constraints thing and fix the inverted conditional moves 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36191 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-17 04:07:59 +00:00
Andrew Lenharth
f81173f70e Add all that branch mangling niftiness 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31313 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-10-31 16:49:55 +00:00
Andrew Lenharth
f2b806a1aa Let the alpha breakage begin. First Formals and RET. next Calls 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28753 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-06-12 18:09:24 +00:00
Andrew Lenharth
017c556efc Alpha Scheduling classes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26643 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-09 17:16:45 +00:00
Andrew Lenharth
77f0885fa3 Add immediate forms of cmov and remove some cruft 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25882 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-01 19:37:33 +00:00
Andrew Lenharth
9e234856fe minor renaming 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25640 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-26 03:24:15 +00:00
Andrew Lenharth
cd1544eede allow R28 to be used for frame calculations without entirely removing it from circulation 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25639 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-26 03:22:07 +00:00
Andrew Lenharth
739027ee4c stack and rpcc 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25369 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-16 21:22:38 +00:00
Andrew Lenharth
feab2f837c Move brcond over and fix some imm patterns. This may be the last change before changing the default alpha isel. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25057 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-01 22:16:14 +00:00
Andrew Lenharth
eececbab32 add br pattern, unify JSR and BSR ISel instrs, and add BSR support for DAG 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25011 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-25 17:36:48 +00:00
Andrew Lenharth
b6718607c5 Unify the patterns for loads and stores. Now offset addressing should be 
supported.  This almost completes memory operations.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25002 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-24 07:34:33 +00:00
Andrew Lenharth
9fa4d4c7c4 move loads and stores over. Smart addr selection comming 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25000 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-24 03:41:56 +00:00
Andrew Lenharth
cfb2815695 OK, this does wonders for broken stuff 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24624 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-06 20:40:34 +00:00
Andrew Lenharth
eda80a0dec added instructions with inverted immediates 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24614 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-06 00:33:53 +00:00
Andrew Lenharth
5de36f95da These never trigger, but whatever 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24612 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-05 23:19:44 +00:00
Andrew Lenharth
7f0db91f86 All sorts of stuff. 
Getting in on the custom lowering thing, yay
evilness with fp setcc, yuck
trivial int select, hmmm
in memory args for functions, yay
DIV and REM, always handy.  They should be custom lowered though.

Lots more stuff compiles now (go go single source!).  Of course, none of it
probably works, but that is what the nightly tester can find out :)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24533 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-11-30 07:19:56 +00:00
Andrew Lenharth
50b37845ef massive DAGISel patch. lots and lots more stuff compiles now 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24483 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-11-22 04:20:06 +00:00
Andrew Lenharth
51b8d54922 continued readcyclecounter support 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24300 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-11-11 16:47:30 +00:00
Andrew Lenharth
5cefc5e64d whatever. Intermediate patch to see what breaks. Seems ok. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24260 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-11-09 19:17:08 +00:00
Andrew Lenharth
641b64aa4b Simplify instinfo, set random bits on more fp insts, and fix 1 opcode 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24014 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-26 17:41:46 +00:00
Andrew Lenharth
756fbeb905 Well, the Constant matching pattern works. Can't say much about calls or globals yet. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23884 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-22 22:06:58 +00:00
Andrew Lenharth
1f347a318c Inst cleanup. As a bonus, operands are in the correct order for cmovs. Expect new stuff to pass in the JIT tonight 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23852 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-20 23:58:36 +00:00
Andrew Lenharth
964b6aacb4 added a few 1 operand form stuff. Seems to break regalloc on alpha. sigh 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23849 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-20 19:39:24 +00:00
Andrew Lenharth
4907d22a90 ret 0; works, not much else 
still lots of uglyness.
Maybe calls will come soon.
Fixing the return value of things will be necessary to make alpha work.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23832 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-20 00:28:31 +00:00
Andrew Lenharth
98169be50b support bsr, and more .td simplification 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22543 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-07-28 18:14:47 +00:00
Andrew Lenharth
f3f951af3f simpilfy instruction encoding (and make the lines way shorter, aka Misha happification) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22499 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-07-22 20:50:29 +00:00
Misha Brukman
2a8350a25c Make the rest of file header comments consistent in format and style 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20048 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-02-05 02:24:26 +00:00
Andrew Lenharth
3e98fde96b initial fp support 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19847 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-01-26 21:54:09 +00:00
Andrew Lenharth
2d6f022a98 Clean ups, and taught the instruction selector about immediate forms 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19816 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-01-24 19:44:07 +00:00
Andrew Lenharth
304d0f3076 Let me introduce you to the early stages of the llvm backend for the alpha processor 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19764 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-01-22 23:41:55 +00:00