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Author SHA1 Message Date
George Burgess IV
91f4bc63a8 [Analysis] Make LocationSizes carry an 'imprecise' bit 
There are places where we need to merge multiple LocationSizes of
different sizes into one, and get a sensible result.

There are other places where we want to optimize aggressively based on
the value of a LocationSizes (e.g. how can a store of four bytes be to
an area of storage that's only two bytes large?)

This patch makes LocationSize hold an 'imprecise' bit to note whether
the LocationSize can be treated as an upper-bound and lower-bound for
the size of a location, or just an upper-bound.

This concludes the series of patches leading up to this. The most recent
of which is r344108.

Fixes PR36228.

Differential Revision: https://reviews.llvm.org/D44748


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344114 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-10-10 06:39:40 +00:00
Max Kazantsev
625a776545 [NFC] Make a variable const 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344113 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-10-10 04:19:38 +00:00
Nemanja Ivanovic
0bb919938f [PowerPC][NFC] Add a test case for extract and store patterns 
An upcoming patch will change the codegen for these patterns. This test case is
added now so that the patch can show the differences in codegen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344112 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-10-10 04:18:35 +00:00
Dylan McKay
44cb934125 [AVR] Fix the 'call.ll' CodeGen test 
Commit r343851 changed the format of the generated instructions.

An unnecessary load has been removed. Previously, a value would be moved
from r24 into a temporary register just to be copied into r30 before the
indirect call. Now, codegen immediately loads r24 into r30, saving a
MOVW instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344111 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-10-10 03:21:42 +00:00
QingShan Zhang
64c3a57bec [PowerPC] Fix the assert of ISD::SIGN_EXTEND_INREG when type is v2i16 and v2i8 
For ISD::SIGN_EXTEND_INREG operation of v2i16 and v2i8 types will cause assert because they are registered as custom operation. 
So that the type legalization phase will enter the custom hook, which do not handle ISD::SIGN_EXTEND_INREG operation and fall throw into unreachable assert.

Patch By: wuzish (Zixuan Wu)
Differential Revision: https://reviews.llvm.org/D52449


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344109 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-10-10 02:33:48 +00:00
George Burgess IV
952e752071 [Analysis] Make LocationSize pretty-printing more descriptive 
This is the third patch in a series intended to make
https://reviews.llvm.org/D44748 more easily reviewable. Please see that
patch for more context. The second being r344013.

The intent is to make the output of printing a LocationSize more
precise. The main motivation for this is that we plan to add a bit to
distinguish whether a given LocationSize is an upper-bound or is
precise; making that information available in pretty-printing is nice.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344108 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-10-10 01:35:22 +00:00
Thomas Lively
de0558be12 [WebAssembly] Fix fneg lowering 
Summary:
Subtraction from zero and floating point negation do not have the same
semantics, so fix lowering.

Reviewers: aheejin, dschuff

Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D52948

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344107 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-10-10 01:09:09 +00:00
Heejin Ahn
bca81ff3be [WebAssembly] Improve comments for SIMD instruction definitions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344106 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-10-10 01:04:02 +00:00
George Karpenkov
96ce5eaa49 [sancov] Generalize the code to get the previous instruction to multiple architectures 
sancov subtracts one from the address to get the previous instruction,
which makes sense on x86_64, but not on other platforms.
This change ensures that the offset is correct for different platforms.
The logic for computing the offset is copied from sanitizer_common.

Differential Revision: https://reviews.llvm.org/D53039

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344103 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-10-10 00:57:24 +00:00
Fangrui Song
42f63b6f96 [opt] Change the parameter of OptTable::PrintHelp from Name to Usage and don't append "[options] <inputs>" 
Summary:
Before, "[options] <inputs>" is unconditionally appended to the `Name` parameter. It is more flexible to change its semantic to `Usage` and let user customize the usage line.

% llvm-objcopy
...
USAGE: llvm-objcopy <input> [ <output> ] [options] <inputs>

With this patch:

% llvm-objcopy
...
USAGE: llvm-objcopy input [output]

Reviewers: rupprecht, alexshap, jhenderson

Reviewed By: rupprecht

Subscribers: jakehehrlich, mehdi_amini, steven_wu, dexonsmith, llvm-commits

Differential Revision: https://reviews.llvm.org/D51009

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344097 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-10-10 00:15:31 +00:00
Zachary Turner
98649f627c [git-llvm] Fix some issues surrouding EOL conversion on Windows. 
This patch fixes three issues.

The first is that we didn't consider files which are explicitly
set to eolstyle CRLF in the repo, and there are a handful of
these.

Second is that dos2unix doesn't have a -q option in GnuWin32,
so this codepath wasn't working properly.

Finally with newer versions of Python (or newer versions of Git,
or some combination of the two) patches can't be applied when
we treat stdin as text, because Python silently undoes all the
work we did to convert the newlines to LF using dos2unix by
using universal_newlines=True and then converting them *back*
to CRLF.  So we need to add a way to force stdin to be treated
as binary, and use it when LF-newlines are required.

Differential Revision: https://reviews.llvm.org/D51444

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344095 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-10-09 23:42:28 +00:00
Thomas Lively
ce40693045 [WebAssembly] Handle V128 register class in explicit locals pass 
Summary:
Also add tests to catch crashes in passes that are not normally run in
tests.

Reviewers: aheejin, dschuff

Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D52959

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344094 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-10-09 23:33:16 +00:00
Nemanja Ivanovic
53979264b2 [DAGCombiner] Expand combining of FP logical ops to sign-setting FP ops 
We already do the following combines:
(bitcast int (and (bitcast fp X to int), 0x7fff...) to fp) -> fabs X
(bitcast int (xor (bitcast fp X to int), 0x8000...) to fp) -> fneg X

When the target has "bit preserving fp logic". This patch just extends it
to also combine:
(bitcast int (or (bitcast fp X to int), 0x8000...) to fp) -> fneg (fabs X)

As some targets have fnabs and even those that don't can efficiently lower
both the fabs and the fneg.

Differential revision: https://reviews.llvm.org/D44548


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344093 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-10-09 23:20:11 +00:00
Rong Xu
dcc47f96ca [X86] Fix sanitizer bot failure from 344085 
Fix the memory issue exposed by sanitizer.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344092 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-10-09 23:10:56 +00:00
Nemanja Ivanovic
2e2e17dd9c [PowerPC][NFC] Commit nabs test case in preparation for committing D44548 
This just adds the test case so that the different code gen is clearly visible
when the DAG Combine lands.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344091 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-10-09 23:02:53 +00:00
Justin Bogner
a219e952b7 [LV] Move test for r343954 into x86 subdirectory 
This test uses an x86 triple, so it needs to be in the x86 specific
test directory.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344087 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-10-09 22:40:04 +00:00
Heejin Ahn
048b539912 [WebAssembly] Improve readability of SIMD instructions (NFC) 
Summary:
- Categorize instructions into the categories as in the SIMD spec
- Move SIMD-related definition to WebAssemblyInstrSIMD.td
- Put definition and use of patterns together
- Add newlines here and there

Reviewers: tlively

Subscribers: dschuff, sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D53045

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344086 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-10-09 22:23:39 +00:00
Rong Xu
c97898e765 Recommit r343993: [X86] condition branches folding for three-way conditional codes 
Fix the memory issue exposed by sanitizer.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344085 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-10-09 22:03:40 +00:00
Cameron McInally
fe584de305 [FPEnv] PatternMatcher support for checking FNEG ignoring signed zeros 
https://reviews.llvm.org/D52934



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344084 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-10-09 21:48:00 +00:00
Sanjay Patel
1dd3c06445 [InstCombine] reverse 'trunc X to <N x i1>' canonicalization 
icmp ne (and X, 1), 0 --> trunc X to N x i1

Ideally, we'd do the same for scalars, but there will likely be 
regressions unless we add more trunc folds as we're doing here 
for vectors.

The motivating vector case is from PR37549:
https://bugs.llvm.org/show_bug.cgi?id=37549

define <4 x float> @bitwise_select(<4 x float> %x, <4 x float> %y, <4 x float> %z, <4 x float> %w) {
  %c = fcmp ole <4 x float> %x, %y
  %s = sext <4 x i1> %c to <4 x i32>
  %s1 = shufflevector <4 x i32> %s, <4 x i32> undef, <4 x i32> <i32 0, i32 0, i32 1, i32 1>
  %s2 = shufflevector <4 x i32> %s, <4 x i32> undef, <4 x i32> <i32 2, i32 2, i32 3, i32 3>
  %cond = or <4 x i32> %s1, %s2
  %condtr = trunc <4 x i32> %cond to <4 x i1>
  %r = select <4 x i1> %condtr, <4 x float> %z, <4 x float> %w
  ret <4 x float> %r
}

Here's a sampling of the vector codegen for that case using 
mask+icmp (current behavior) vs. trunc (with this patch):

AVX before:

vcmpleps	%xmm1, %xmm0, %xmm0
vpermilps	$80, %xmm0, %xmm1 ## xmm1 = xmm0[0,0,1,1]
vpermilps	$250, %xmm0, %xmm0 ## xmm0 = xmm0[2,2,3,3]
vorps	%xmm0, %xmm1, %xmm0
vandps	LCPI0_0(%rip), %xmm0, %xmm0
vxorps	%xmm1, %xmm1, %xmm1
vpcmpeqd	%xmm1, %xmm0, %xmm0
vblendvps	%xmm0, %xmm3, %xmm2, %xmm0

AVX after:

vcmpleps	%xmm1, %xmm0, %xmm0
vpermilps	$80, %xmm0, %xmm1 ## xmm1 = xmm0[0,0,1,1]
vpermilps	$250, %xmm0, %xmm0 ## xmm0 = xmm0[2,2,3,3]
vorps	%xmm0, %xmm1, %xmm0
vblendvps	%xmm0, %xmm2, %xmm3, %xmm0

AVX512f before:

vcmpleps	%xmm1, %xmm0, %xmm0
vpermilps	$80, %xmm0, %xmm1 ## xmm1 = xmm0[0,0,1,1]
vpermilps	$250, %xmm0, %xmm0 ## xmm0 = xmm0[2,2,3,3]
vorps	%xmm0, %xmm1, %xmm0
vpbroadcastd	LCPI0_0(%rip), %xmm1 ## xmm1 = [1,1,1,1]
vptestnmd	%zmm1, %zmm0, %k1
vblendmps	%zmm3, %zmm2, %zmm0 {%k1}

AVX512f after:

vcmpleps	%xmm1, %xmm0, %xmm0
vpermilps	$80, %xmm0, %xmm1 ## xmm1 = xmm0[0,0,1,1]
vpermilps	$250, %xmm0, %xmm0 ## xmm0 = xmm0[2,2,3,3]
vorps	%xmm0, %xmm1, %xmm0
vpslld	$31, %xmm0, %xmm0
vptestmd	%zmm0, %zmm0, %k1
vblendmps	%zmm2, %zmm3, %zmm0 {%k1}

AArch64 before:

fcmge	v0.4s, v1.4s, v0.4s
zip1	v1.4s, v0.4s, v0.4s
zip2	v0.4s, v0.4s, v0.4s
orr	v0.16b, v1.16b, v0.16b
movi	v1.4s, #1
and	v0.16b, v0.16b, v1.16b
cmeq	v0.4s, v0.4s, #0
bsl	v0.16b, v3.16b, v2.16b

AArch64 after:

fcmge	v0.4s, v1.4s, v0.4s
zip1	v1.4s, v0.4s, v0.4s
zip2	v0.4s, v0.4s, v0.4s
orr	v0.16b, v1.16b, v0.16b
bsl	v0.16b, v2.16b, v3.16b

PowerPC-le before:

xvcmpgesp 34, 35, 34
vspltisw 0, 1
vmrglw 3, 2, 2
vmrghw 2, 2, 2
xxlor 0, 35, 34
xxlxor 35, 35, 35
xxland 34, 0, 32
vcmpequw 2, 2, 3
xxsel 34, 36, 37, 34

PowerPC-le after:

xvcmpgesp 34, 35, 34
vmrglw 3, 2, 2
vmrghw 2, 2, 2
xxlor 0, 35, 34
xxsel 34, 37, 36, 0

Differential Revision: https://reviews.llvm.org/D52747



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344082 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-10-09 21:26:01 +00:00
Zachary Turner
6b971fb369 [PDB] Fix another bug in globals stream name lookup. 
When we're on the last bucket the computation is tricky.
We were failing when the last bucket contained multiple
matches.  Added a new test for this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344081 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-10-09 21:19:03 +00:00
Jake Ehrlich
10e3a5f0a7 [llvm-objcopy] Make -S an alias for --strip-all 
-S should be an alias for --strip-all not --strip-all-gnu

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344080 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-10-09 21:14:09 +00:00
Adrian Prantl
0f4106775e llvm-dwarfdump: Extend --name to also search DW_AT_linkage_name. 
rdar://problem/45132695

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344079 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-10-09 20:51:33 +00:00
Lang Hames
5148047f08 [ORC] Promote and rename private symbols inside the CompileOnDemand layer, 
rather than require them to have been promoted before being passed in.

Dropping this precondition is better for layer composition (CompileOnDemandLayer
was the only one that placed pre-conditions on the modules that could be added).
It also means that the promoted private symbols do not show up in the target
JITDylib's symbol table. Instead, they are confined to the hidden implementation
dylib that contains the actual definitions.

For the 403.gcc testcase this cut down the public symbol table size from ~15,000
symbols to ~4000, substantially reducing symbol dependence tracking costs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344078 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-10-09 20:44:32 +00:00
Nemanja Ivanovic
7df2b65a85 [PowerPC] Implement hasBitPreservingFPLogic for types that can be supported 
This is the PPC-specific non-controversial part of
https://reviews.llvm.org/D44548 that simply enables this combine for PPC
since PPC has these instructions.
This commit will allow the target-independent portion to be truly target
independent.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344077 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-10-09 20:35:15 +00:00
Craig Topper
b5c5010513 [X86] When lowering unsigned v2i64 setcc without SSE42, flip the sign bits in the v2i64 type then bitcast to v4i32. 
This may give slightly better opportunities for DAG combine to simplify with the operations before the setcc. It also matches the type the xors will eventually be promoted to anyway so it saves a legalization step.

Almost all of the test changes are because our constant pool entry is now v2i64 instead of v4i32 on 64-bit targets. On 32-bit targets getConstant should be emitting a v4i32 build_vector and a v4i32->v2i64 bitcast.

There are a couple test cases where it appears we now combine a bitwise not with one of these xors which caused a new constant vector to be generated. This prevented a constant pool entry from being shared. But if that's an issue we're concerned about, it seems we need to address it another way that just relying a bitcast to hide it.

This came about from experiments I've been trying with pushing the promotion of and/or/xor to vXi64 later than LegalizeVectorOps where it is today. We run LegalizeVectorOps in a bottom up order. So the and/or/xor are promoted before their users are legalized. The bitcasts added for the promotion act as a barrier to computeKnownBits if we try to use it during vector legalization of a later operation. So by moving the promotion out we can hopefully get better results from computeKnownBits/computeNumSignBits like in LowerTruncate on AVX512. I've also looked at running LegalizeVectorOps in a top down order like LegalizeDAG, but thats showing some other issues.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344071 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-10-09 19:05:50 +00:00
Sam Clegg
36b0632ee0 [SLPVectorizer] Check that lowered type is floating point before calling isFabsFree 
In the case of soft-fp (e.g. fp128 under wasm) the result of
getTypeLegalizationCost() can be an integer type even if the input is
floating point (See LegalizeTypeAction::TypeSoftenFloat).

Before calling isFabsFree() (which asserts if given a non-fp
type) we need to check that that result is fp.  This is safe since in
fabs is certainly not free in the soft-fp case.

Fixes PR39168

Differential Revision: https://reviews.llvm.org/D52899

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344069 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-10-09 18:41:17 +00:00
Wolfgang Pieb
6c508a5190 [DWARF] Make llvm-dwarfdump display the .debug_loc.dwo section. Fixes PR38991. 
Reviewer: dblaikie

Differential Revision: https://reviews.llvm.org/D52444


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344068 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-10-09 18:38:55 +00:00
Sanjay Patel
4db5dbc637 [InstCombine] add tests for extract subvector shuffles; NFC 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344067 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-10-09 18:37:20 +00:00
Adrian Prantl
0a3d7dbe84 Add missing space 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344064 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-10-09 18:12:04 +00:00
Zachary Turner
dccf3ce84a [PDB] Fix failure on big endian machines. 
We changed an ArrayRef<uint8_t> to an ArrayRef<uint32_t>, but
it needs to be an ArrayRef<support::ulittle32_t>.

We also change ArrayRef<> to FixedStreamArray<>.  Technically
an ArrayRef<> will work, but it can cause a copy in the underlying
implementation if the memory is not contiguous, and there's no
reason not to use a FixedStreamArray<>.

Thanks to nemanjai@ and thakis@ for helping me track this down
and confirm the fix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344063 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-10-09 17:58:51 +00:00
Craig Topper
81b8d4b9e2 [X86] Autogenerate complete checks. NFC 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344060 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-10-09 17:52:07 +00:00
Sanjay Patel
0bcf39f903 [AArch64][x86] add tests for bitcasted fnabs; NFC 
Alternate target coverage for  D44548.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344059 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-10-09 17:20:26 +00:00
Sanjay Patel
dd6a1fbcd5 [InstCombine] make helper function 'static'; NFC 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344056 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-10-09 15:29:26 +00:00
Guillaume Chatelet
6a2b073367 Fix function case. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344051 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-10-09 14:51:33 +00:00
Guillaume Chatelet
437c485aa9 [llvm-exegesis] Fix invalid return type and add a Dump function. 
Reviewers: courbet

Subscribers: tschuett, llvm-commits

Differential Revision: https://reviews.llvm.org/D53020

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344050 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-10-09 14:51:29 +00:00
Sanjay Patel
968d0cc02d [x86] use demanded bits to simplify masked store codegen 
As noted in D52747, if we prefer IR to use trunc for bool vectors rather 
than and+icmp, we can expose codegen shortcomings as seen here with masked store.

Replace a hard-coded PCMPGT simplification with the more general demanded bits call
to improve things.

Differential Revision: https://reviews.llvm.org/D52964


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344048 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-10-09 14:04:14 +00:00
Simon Pilgrim
e574f76b8f [SelectionDAG] Add SIGN_EXTEND_VECTOR_INREG and CONCAT_VECTORS support to SimplifyDemandedBits 
Fix for AVX1 masked load/store regression on D52964

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344043 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-10-09 13:13:35 +00:00
Simon Atanasyan
244c796c89 [mips] Fix FDE/CFI encoding in case of N32 ABI 
For O32 and N32 ABI FDE/CFI encoding should be `DW_EH_PE_sdata4` and only
N64 ABI uses `DW_EH_PE_sdata8`. To cover all cases this patch check code
pointer size and setup a correct FDE/CFI encoding type.

Differential revision: https://reviews.llvm.org/D52876

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344040 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-10-09 11:29:51 +00:00
Simon Atanasyan
00973e3c15 [mips] Set pointer size to 4 bytes for N32 ABI 
CodePointerSize and CalleeSaveStackSlotSize values are used in DWARF
generation. In case of MIPS it's incorrect to check for Triple::isMIPS64()
only this function returns true for N32 ABI too.

Now we do not have a method to recognize N32 if it's specified by a command
line option and is not a part of a target triple. So we check for
Triple::GNUABIN32 only. It's better than nothing.

Differential revision: https://reviews.llvm.org/D52874

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344039 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-10-09 11:29:45 +00:00
Nemanja Ivanovic
4313690118 Fix buildbot failures with the newly added test case (triple was missing). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344037 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-10-09 11:17:47 +00:00
Nemanja Ivanovic
edb9a19f38 [PowerPC] Remove self-copies in pre-emit peephole 
There are occasionally instances where AADB rewrites registers in such a way
that a reg-reg copy becomes a self-copy. Such an instruction is obviously
redundant and can be removed. This patch does precisely that.

Note that this will not remove various nop's that we insert (which are
themselves just self-copies). The reason those are left alone is that all of
them have their own opcodes (that just encode to a self-copy).

What prompted this patch is the fact that these self-copies sometimes end up
using registers that make the instruction a priority-setting nop, thereby
having a significant effect on performance.

Differential revision: https://reviews.llvm.org/D52432


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344036 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-10-09 10:54:04 +00:00
Guillaume Chatelet
6027f5ef52 [llvm-exegesis] Fix wrong index type. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344032 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-10-09 10:06:19 +00:00
Guillaume Chatelet
6844640a5e [llvm-exegesis] Fix unused lambda capture. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344029 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-10-09 09:33:29 +00:00
Guillaume Chatelet
9925bf1d88 [llvm-exegesis][NFC] Use accessors for Operand. 
Summary:
This moves checking logic into the accessors and makes the structure smaller.
It will also help when/if Operand are generated from the TD files.

Subscribers: tschuett, courbet, llvm-commits

Differential Revision: https://reviews.llvm.org/D52982

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344028 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-10-09 08:59:10 +00:00
Aleksandr Urakov
3659c41ec5 [ADT] Force the alignment of the data field of IntervalMap 
Summary:
This patch forces the alignment of the `data` field of `IntervalMap`.
It is because x86 MSVC doesn't apply automatically
(without `__declspec(align(...))`) alignments more than 4 bytes,
even if `alignof` has returned so. Consider the example:

https://godbolt.org/z/zIPa_G

Here `alignof` for both `S0` and `S1` returns `8`, but only `S1` is really
aligned on x86. The explanation of this behavior is here:

https://docs.microsoft.com/en-us/cpp/build/conflicts-with-the-x86-compiler

Reviewers: bkramer, stoklund, hans, rnk

Reviewed By: rnk

Subscribers: dexonsmith, llvm-commits

Differential Revision: https://reviews.llvm.org/D52613

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344027 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-10-09 08:50:50 +00:00
Aleksandr Urakov
8cc4d7e1c6 Revert "[ADT] Change the IntervalMap alignment assert for x86 MSVC" 
This reverts commit 7f9eb168a9.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344020 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-10-09 07:44:17 +00:00
Simon Pilgrim
729310ff09 [X86][AVX1] Enable *_EXTEND_VECTOR_INREG lowering of 256-bit vectors 
As discussed on D52964, this adds 256-bit *_EXTEND_VECTOR_INREG lowering support for AVX1 targets to help improve SimplifyDemandedBits handling.

Differential Revision: https://reviews.llvm.org/D52980

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344019 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-10-09 07:42:01 +00:00
Aleksandr Urakov
7f9eb168a9 [ADT] Change the IntervalMap alignment assert for x86 MSVC 
Summary:
This patch forces the alignment of the `data` field of `IntervalMap`.
It is because x86 MSVC doesn't apply automatically
(without `__declspec(align(...))`) alignments more than 4 bytes,
even if `alignof` has returned so. Consider the example:

https://godbolt.org/z/zIPa_G

Here `alignof` for both `S0` and `S1` returns `8`, but only `S1` is really
aligned on x86. The explanation of this behavior is here:

https://docs.microsoft.com/en-us/cpp/build/conflicts-with-the-x86-compiler

Reviewers: bkramer, stoklund, hans, rnk

Reviewed By: rnk

Subscribers: dexonsmith, llvm-commits

Differential Revision: https://reviews.llvm.org/D52613

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344018 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-10-09 07:33:09 +00:00
Chandler Carruth
c179d7b006 [CFG Printer] Add support for writing the dot files with a custom 
prefix.

Use this to direct these files to a specific location in the test suite
so that we don't write files out to random directories (or fail if the
working directory isn't writable).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344014 91177308-0d34-0410-b5e6-96231b3b80d8
 2018-10-09 04:30:23 +00:00