149944 Commits

Author SHA1 Message Date
Quentin Colombet
9f43f266be [RABasic] Properly initialize the pass
Use the initializeXXX method to initialize the RABasic pass in the
pipeline. This enables us to take advantage of the .mir infrastructure.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304602 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-02 22:46:26 +00:00
Xinliang David Li
13596b2bfe Fix debug build test failure
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304600 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-02 22:38:48 +00:00
Xinliang David Li
118cef0ca3 [PartialInlining] Minor cost anaysis tuning
Also added a test option and 2 cost analysis related tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304599 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-02 22:08:04 +00:00
David Blaikie
ffc893deb7 FunctionAttrs: Skip it if the effective SCC (ignoring optnone functions) is empty
Minor optimization but mostly simplifies my debugging so I'm not dealing
with empty SCCNodeSets while investigating issues in this optimization.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304597 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-02 21:24:17 +00:00
Matthias Braun
465de97122 RegisterScavenging: Move scavenging logic from PEI to RegisterScavenging; NFC
These parts do not depend on any PrologEpilogInserter logic and
therefore better fits RegisterScaveging.cpp.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304596 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-02 21:02:03 +00:00
Zachary Turner
efbf6a8cda Fix build error on gcc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304595 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-02 21:00:22 +00:00
Jun Bum Lim
2961ee384e [InlineCost] Enable the new switch cost heuristic
Summary:
This is to enable the new switch inline cost heuristic (r301649) by removing the
old heuristic as well as the flag itself.
In my experiment for LLVM test suite and spec2000/2006, +17.82% performance and
8% code size reduce was observed in spec2000/vertex with O3 LTO in AArch64.
No significant code size / performance regression was found in O3/O2/Os. No
significant complain was reported from the llvm-dev thread.

Reviewers: hans, chandlerc, eraman, haicheng, mcrosier, bmakam, eastig, ddibyend, echristo

Reviewed By: echristo

Subscribers: javed.absar, kristof.beyls, echristo, aemerson, rengolin, mehdi_amini

Differential Revision: https://reviews.llvm.org/D32653

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304594 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-02 20:42:54 +00:00
Alexey Bataev
37aaa827f4 [SLP] Improve comments and naming of functions/variables/members, NFC.
Summary:
Fixed some comments, added an additional description of the algorithms,
improved readability of the code.

Reviewers: anemet

Subscribers: llvm-commits, mzolotukhin

Differential Revision: https://reviews.llvm.org/D33320

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304593 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-02 20:39:27 +00:00
Ahmed Bougacha
3f86a859d8 [X86] Correctly broadcast NaN-like integers as float on AVX.
Since r288804, we try to lower build_vectors on AVX using broadcasts of
float/double.  However, when we broadcast integer values that happen to
have a NaN float bitpattern, we lose the NaN payload, thereby changing
the integer value being broadcast.

This is caused by ConstantFP::get, to which we pass the splat i32 as
a float (by bitcasting it using bitsToFloat).  ConstantFP::get takes
a double parameter, so we end up lossily converting a single-precision
NaN to double-precision.

Instead, avoid any kinds of conversions by directly building an APFloat
from the splatted APInt.

Note that this also fixes another piece of code (broadcast of
subvectors), that currently isn't susceptible to the same problem.

Also note that we could really just use APInt and ConstantInt
throughout: the constant pool type doesn't matter much.  Still, for
consistency, use the appropriate type.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304590 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-02 20:02:59 +00:00
Zachary Turner
c0160aa0c7 Fix build error with clang and gcc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304589 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-02 20:00:10 +00:00
Zachary Turner
42d60ef585 [CodeView] Support CodeView subsections in any order.
Previously we would expect certain subsections to appear
in a certain order because some subsections would reference
other subsections, but in practice we need to support
arbitrary orderings since some object file and PDB file
producers generate them this way.  This also paves the
way for supporting Yaml <-> Object File conversion of
CodeView, since Object Files typically have quite a
large number of subsections in their debug info.

Differential Revision: https://reviews.llvm.org/D33807

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304588 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-02 19:49:14 +00:00
Petr Hosek
e84c1d83ad [CMake][runtimes] Add install target for runtimes builtins
This adds an install-builtins target to avoid having to list all
builtins targets explicitly.

Differential Revision: https://reviews.llvm.org/D32710

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304587 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-02 19:38:11 +00:00
Amaury Sechet
43a958c91e Regenerate expectation for wide-fma-contraction.ll . NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304586 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-02 19:15:04 +00:00
Keno Fischer
a1a34351e6 [SROA] Fix crash due to bad bitcast
Summary:
As shown in the test case, SROA was crashing when trying to split
stores (to the alloca) of loads (from anywhere), because it assumed
the pointer operand to the loads and stores had to have the same
address space. This isn't the case. Make sure to use the correct
pointer type for both the load and the store.

Reviewed By: yaxunl
Differential Revision: https://reviews.llvm.org/D32593

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304585 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-02 19:04:17 +00:00
Evgeniy Stepanov
03ceeb1a86 [CFI] Remove LinkerSubsectionsViaSymbols.
Since D17854 LinkerSubsectionsViaSymbols is unnecessary.

It is interfering with ThinLTO implementation of CFI-ICall, where
the aliases used on the !LinkerSubsectionsViaSymbols branch are
needed to export jump tables to ThinLTO backends.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304582 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-02 18:45:14 +00:00
David Blaikie
6cc5d91953 BitcodeWriter: Removing unnecessary std::function in favor of template
More cleanup from post-commit discussion on r304516

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304579 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-02 18:25:29 +00:00
Evgeniy Stepanov
93d430ca14 Skip CFI for dead functions.
Differential Revision: https://reviews.llvm.org/D33805

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304578 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-02 18:24:23 +00:00
Evgeniy Stepanov
a667b70dbe Move summary dead stripping before regular LTO.
This way dead stripping results are recorded in combined summary and
can be used in regular LTO passes.

Differential Revision: https://reviews.llvm.org/D33615

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304577 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-02 18:24:17 +00:00
Sanjay Patel
f1a1cf19c1 [x86] fix formatting; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304576 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-02 18:14:31 +00:00
Matt Arsenault
7796b916f8 AMDGPU: Register AMDGPUAlwaysInline
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304574 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-02 18:02:42 +00:00
Reid Kleckner
8147ef1372 Re-land "COFF: migrate def parser from LLD to LLVM"
This reverts commit r304561 and re-lands r303490 & co.

The fix was to use "SymbolName" when translating LLD's internal export
list to lib/Object's short export struct. The SymbolName reflects the
actual symbol name, which may include fastcall and stdcall mangling bits
not included in the /EXPORT or .def file EXPORTS name:

@@ -434,8 +434,7 @@ std::vector<COFFShortExport> createCOFFShortExportFromConfig() {
   std::vector<COFFShortExport> Exports;
   for (Export &E1 : Config->Exports) {
     COFFShortExport E2;
-    E2.Name = E1.Name;
+    // Use SymbolName, which will have any stdcall or fastcall qualifiers.
+    E2.Name = E1.SymbolName;
     E2.ExtName = E1.ExtName;
     E2.Ordinal = E1.Ordinal;
     E2.Noname = E1.Noname;

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304573 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-02 17:53:06 +00:00
Konstantin Zhuravlyov
e0fcf72467 AMDGPU: Make auto waitcnt before barrier a feature
Differential Revision: https://reviews.llvm.org/D33793


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304571 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-02 17:40:26 +00:00
Sanjay Patel
d496b07e32 [TargetLowering] fix formatting; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304569 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-02 17:35:02 +00:00
Craig Topper
23873bb3a1 [LazyValueInfo] Fix formatting NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304567 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-02 17:28:12 +00:00
David Blaikie
29e59c38ab Tidy up a bit of r304516, use SmallVector::assign rather than for loop
This might give a few better opportunities to optimize these to memcpy
rather than loops - also a few minor cleanups (StringRef-izing,
templating (to avoid std::function indirection), etc).

The SmallVector::assign(iter, iter) could be improved with the use of
SFINAE, but the (iter, iter) ctor and append(iter, iter) need it to and
don't have it - so, workaround it for now rather than bothering with the
added complexity.

(also, as noted in the added FIXME, these assign ops could potentially
be optimized better at least for non-trivially-copyable types)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304566 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-02 17:24:26 +00:00
Philip Reames
4b07d035e2 Verify a couple more fields in STATEPOINT instructions
While doing so, clarify the comments and update them to reflect current reality.

Note: I'm going to let this sit for a week or so before adding further verification.  I want to give this time to cycle through bots and merge it into our downstream tree before pushing this further.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304565 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-02 17:02:33 +00:00
Philip Reames
bfffaf778f Add placeholder for more extensive verification of psuedo ops
This initial patch doesn't actually do much useful. It's just to show where the new code goes. Once this is in, I'll extend the verification logic to check more useful properties.

For those curious, the more complicated version of this patch already found one very suspicious thing.

Differential Revision: https://reviews.llvm.org/D33819



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304564 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-02 16:36:37 +00:00
Craig Topper
fd6a4a56bb [LazyValueInfo] Make solveBlockValueBinaryOp take a BinaryOperator* instead of Instruction*. This removes a cast of getOpcode to BinaryOps.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304563 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-02 16:33:13 +00:00
Sanjay Patel
448aa4eba4 [InstCombine] fix icmp with not op and constant to work with splat vector constant
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304562 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-02 16:29:41 +00:00
Reid Kleckner
afe7c5a7a6 Revert "COFF: migrate def parser from LLD to LLVM"
This reverts commits r303490, r303491, r303493, and r303494.

This caused http://crbug.com/728726. Essentially, exporting stdcall
functions doesn't appear to work after this change. Reduced test case
soon.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304561 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-02 16:26:24 +00:00
Craig Topper
1c790aea33 [LazyValueInfo] Fix typo in comment. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304560 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-02 16:21:13 +00:00
Craig Topper
cbb8bc969e [InstSimplify][ConstantFolding] Teach constant folding how to handle icmp null, (inttoptr x) as well as it handles icmp (inttoptr x), null
Summary:
The constant folding code currently assumes that the constant expression will always be on the left and the simple null will be on the right. But that's not true at least on the path from InstSimplify.

This patch adds support to ConstantFolding to detect the reversed case.

Reviewers: spatel, dberlin, majnemer, davide, joey

Reviewed By: joey

Subscribers: joey, llvm-commits

Differential Revision: https://reviews.llvm.org/D33801

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304559 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-02 16:17:32 +00:00
Sanjay Patel
17c16d5b42 [InstCombine] improve perf by not creating a known non-canonical instruction
Op1 (RHS) is a constant, so putting it on the LHS makes us churn through visitICmp
an extra time to canonicalize it:

INSTCOMBINE ITERATION #1 on cmpnot
IC: ADDING: 3 instrs to worklist
IC: Visiting:   %notx = xor i8 %x, -1
IC: Visiting:   %cmp = icmp sgt i8 %notx, 42
IC: Old =   %cmp = icmp sgt i8 %notx, 42
    New =   <badref> = icmp sgt i8 -43, %x
IC: ADD:   %cmp = icmp sgt i8 -43, %x
IC: ERASE   %1 = icmp sgt i8 %notx, 42
IC: ADD:   %notx = xor i8 %x, -1
IC: DCE:   %notx = xor i8 %x, -1
IC: ERASE   %notx = xor i8 %x, -1
IC: Visiting:   %cmp = icmp sgt i8 -43, %x
IC: Mod =   %cmp = icmp sgt i8 -43, %x
    New =   %cmp = icmp slt i8 %x, -43
IC: ADD:   %cmp = icmp slt i8 %x, -43
IC: Visiting:   %cmp = icmp slt i8 %x, -43
IC: Visiting:   ret i1 %cmp

If we create the swapped ICmp directly, we go faster:

INSTCOMBINE ITERATION #1 on cmpnot
IC: ADDING: 3 instrs to worklist
IC: Visiting:   %notx = xor i8 %x, -1
IC: Visiting:   %cmp = icmp sgt i8 %notx, 42
IC: Old =   %cmp = icmp sgt i8 %notx, 42
    New =   <badref> = icmp slt i8 %x, -43
IC: ADD:   %cmp = icmp slt i8 %x, -43
IC: ERASE   %1 = icmp sgt i8 %notx, 42
IC: ADD:   %notx = xor i8 %x, -1
IC: DCE:   %notx = xor i8 %x, -1
IC: ERASE   %notx = xor i8 %x, -1
IC: Visiting:   %cmp = icmp slt i8 %x, -43
IC: Visiting:   ret i1 %cmp




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304558 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-02 16:11:14 +00:00
Amaury Sechet
ec35ada3f4 Update select.ll expected results. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304557 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-02 16:07:43 +00:00
Sanjay Patel
eece7bcb17 [InstCombine] fix/add tests for icmp with not ops; NFC
The existing test was not minimal, and there was no coverage
for the variants with a constant or vector types.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304555 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-02 15:35:45 +00:00
Alexander Timofeev
dfdb788875 AMDGPUAnnotateUniformValue should always treat volatile loads as divergent
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304554 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-02 15:25:52 +00:00
Geoff Berry
7df090cb2b [AArch64][Falkor] Model immediate forwarding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304552 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-02 14:27:41 +00:00
Mark Searles
48e0515b4f [AMDGPU] Turn on the new waitcnt insertion pass. Adjust tests.
-enable-si-insert-waitcnts=1 becomes the default
-enable-si-insert-waitcnts=0 to use old pass

Differential Revision: https://reviews.llvm.org/D33730

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304551 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-02 14:19:25 +00:00
Zoran Jovanovic
9c2941a24c [mips][microMIPS] Extending size reduction pass with LBU16, LHU16, SB16 and SH16
Author: milena.vujosevic.janicic
Reviewers: sdardis
The patch extends size reduction pass for MicroMIPS.
The following instructions are examined and transformed, if possible:
LBU instruction is transformed into 16-bit instruction LBU16
LHU instruction is transformed into 16-bit instruction LHU16
SB instruction is transformed into 16-bit instruction SB16
SH instruction is transformed into 16-bit instruction SH16
Differential Revision: https://reviews.llvm.org/D33091


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304550 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-02 14:14:21 +00:00
Krzysztof Parzyszek
c4071bcc5b [Hexagon] Return 0 from getDotNewPredOp when .new opcode does not exist
This allows using this function to test if an instruction can be converted
to a .new form.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304549 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-02 14:07:06 +00:00
Amaury Sechet
f4b4c0031c Regenerate sse3.ll test results. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304548 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-02 14:02:49 +00:00
Amaury Sechet
38e075d56e Regenerate and-sink.ll test results. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304547 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-02 14:02:46 +00:00
Amaury Sechet
397f7b2eea Regenerate shrink-compare.ll test results. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304546 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-02 14:02:43 +00:00
Benjamin Kramer
2118193ddf [OrderedBasicBlock] Return false for comesBefore(A, A)
So far it would return true for the first uncached query, then cached
queries return false.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304545 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-02 13:10:31 +00:00
Alex Lorenz
c9c72aa1f6 [lit][macOS] Add a utility function to find the platform SDK version
on macOS

This function will be used to tie Clang's Integeration tests to a particular
SDK version. See https://reviews.llvm.org/D32178 for more context.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304541 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-02 11:21:37 +00:00
Benjamin Kramer
f4cc8004bc [X86] Don't fold into memory operands into insertps in the generated folding tables.
insertps behaves differently, the register form selects from an input
register based on the immediate operand while the memory form just loads
the given address. We have custom code to change the immediate in cases
where that's legal, so completely remove insertps from the generated
tables.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304540 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-02 10:50:22 +00:00
John Brawn
0f1cadd920 [GlobalMerge] Don't merge globals that may be preempted
When a global may be preempted it needs to be accessed directly, instead of
indirectly through a MergedGlobals symbol, for the preemption to work.

This fixes PR33136.

Differential Revision: https://reviews.llvm.org/D33727


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304537 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-02 10:24:14 +00:00
Diana Picus
899f9e9ab6 [ARM] GlobalISel: Support struct params/returns
Very very similar to the support for arrays. As with arrays, we don't
support returning large structs that wouldn't fit in R0-R3. Most
front-ends would likely use sret arguments for that anyway.

The only significant difference is that when splitting a struct, we need
to make sure we set the correct original alignment on each member,
otherwise it may get split incorrectly between stack and registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304536 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-02 10:16:48 +00:00
Amaury Sechet
4253871909 nits in TargetLowering.cpp . NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304532 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-02 09:18:18 +00:00
Javed Absar
8f528aa2a7 [ARM] Cortex-A57 scheduling model for ARM backend (AArch32)
This patch implements the Cortex-A57 scheduling model.
The main code is in ARMScheduleA57.td, ARMScheduleA57WriteRes.td.
Small changes in cpp,.h files to support required scheduling predicates.

Scheduling model implemented according to:
 http://infocenter.arm.com/help/topic/com.arm.doc.uan0015b/Cortex_A57_Software_Optimization_Guide_external.pdf.

Patch by : Andrew Zhogin (submitted on his behalf, as requested).
Rewiewed by: Renato Golin, Diana Picus, Javed Absar, Kristof Beyls.
Differential Revision: https://reviews.llvm.org/D28152




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304530 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-02 08:53:19 +00:00