Evan Cheng
76a4023096
Honor user-defined section specification of a global, ignores whether its initializer is null.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42182 91177308-0d34-0410-b5e6-96231b3b80d8
2007-09-21 00:41:19 +00:00
Devang Patel
0f0daea654
Do not override user specified section.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42179 91177308-0d34-0410-b5e6-96231b3b80d8
2007-09-20 23:07:37 +00:00
Dan Gohman
92dfe2001e
Remove isReg, isImm, and isMBB, and change all their users to use
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isRegister, isImmediate, and isMachineBasicBlock, which are equivalent,
and more popular.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41958 91177308-0d34-0410-b5e6-96231b3b80d8
2007-09-14 20:33:02 +00:00
Evan Cheng
fdd9f006bc
Fix comments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41947 91177308-0d34-0410-b5e6-96231b3b80d8
2007-09-14 01:57:02 +00:00
Bill Wendling
fe4afb17d3
Enable indirect encoding for the personality function
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41873 91177308-0d34-0410-b5e6-96231b3b80d8
2007-09-11 23:55:40 +00:00
Evan Cheng
071a279e94
Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41863 91177308-0d34-0410-b5e6-96231b3b80d8
2007-09-11 19:55:27 +00:00
Duncan Sands
f7331b3dd7
Fold the adjust_trampoline intrinsic into
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init_trampoline. There is now only one
trampoline intrinsic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41841 91177308-0d34-0410-b5e6-96231b3b80d8
2007-09-11 14:10:23 +00:00
Chris Lattner
bf8ae84a21
Add some notes about better flag handling.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41808 91177308-0d34-0410-b5e6-96231b3b80d8
2007-09-10 21:43:18 +00:00
Bill Wendling
82d25148a7
Add missing index versions of instructions to the map.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41776 91177308-0d34-0410-b5e6-96231b3b80d8
2007-09-07 22:01:02 +00:00
Owen Anderson
718cb665ca
Add lengthof and endof templates that hide a lot of sizeof computations.
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Patch by Sterling Stein!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41758 91177308-0d34-0410-b5e6-96231b3b80d8
2007-09-07 04:06:50 +00:00
Bill Wendling
399ea50dc3
LVXL and STVXL are also a load and store resp.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41733 91177308-0d34-0410-b5e6-96231b3b80d8
2007-09-05 23:47:12 +00:00
Bill Wendling
c3536b8ecb
Add the 64-bit versions of the DS* Altivec instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41717 91177308-0d34-0410-b5e6-96231b3b80d8
2007-09-05 04:05:20 +00:00
Evan Cheng
67c906dce7
Fix for PR1613: added 64-bit rotate left PPC instructions and patterns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41711 91177308-0d34-0410-b5e6-96231b3b80d8
2007-09-04 20:20:29 +00:00
Dale Johannesen
eaf089430e
Enhance APFloat to retain bits of NaNs (fixes oggenc).
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Use APFloat interfaces for more references, mostly
of ConstantFPSDNode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41632 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-31 04:03:46 +00:00
Evan Cheng
35b35c5c32
Add a variant of foldMemoryOperand to fold any load / store, not just load / store from / to stack slots.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41597 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-30 05:52:20 +00:00
Bill Wendling
b8a80f03bf
Use i64 on a PPC64 machine
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41590 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-30 00:59:19 +00:00
Chris Lattner
48884cd80b
rename isOperandValidForConstraint to LowerAsmOperandForConstraint,
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changing the interface to allow for future changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41384 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-25 00:47:38 +00:00
Chris Lattner
90e167a908
Disable EH generation until PPC works 100%.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41360 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-24 16:00:15 +00:00
Chris Lattner
aabd0359a3
new example
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41318 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-23 15:16:03 +00:00
Dale Johannesen
48bd15ed72
Fix arguments for some Altivec instructions. From SWB.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40957 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-09 00:49:19 +00:00
Dale Johannesen
84109cd015
Fix spelling of mtvscr and mfvscr.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40908 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-07 23:08:00 +00:00
Dale Johannesen
8c1e6a119a
long double patch 2 of N. Handle it in TargetData.
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(I've tried to get the info right for all targets,
but I'm not expert on all of them - check yours.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40792 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-03 20:20:50 +00:00
Dan Gohman
61e729e2e9
More explicit keywords.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40757 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-02 21:21:54 +00:00
Evan Cheng
caf778ab3b
Some out operands were incorrectly specified as input operands.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40697 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-01 23:07:38 +00:00
Evan Cheng
66ffe6be0c
Vector fneg must be expanded into fsub -0.0, X.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40586 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-30 07:51:22 +00:00
Duncan Sands
36397f5034
Support for trampolines, except for X86 codegen which is
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still under discussion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40549 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-27 12:58:54 +00:00
Dan Gohman
b8275a3f6f
Don't ignore the return value of AsmPrinter::doInitialization and
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AsmPrinter::doFinalization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40487 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-25 19:33:14 +00:00
Nick Lewycky
e2b905232f
Fix debug info and globals filled with zeros.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40483 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-25 03:48:45 +00:00
Evan Cheng
ffbaccae02
No more noResults.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40132 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-21 00:34:19 +00:00
Evan Cheng
8bd6035750
Added -print-emitted-asm to print out JIT generated asm to cerr.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40123 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-20 21:56:13 +00:00
Evan Cheng
d5f181a665
Oops. These stores actually produce results.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40074 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-20 00:20:46 +00:00
Evan Cheng
64d80e3387
Change instruction description to split OperandList into OutOperandList and
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InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19 01:14:50 +00:00
Anton Korobeynikov
2365f51ed0
Long live the exception handling!
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This patch fills the last necessary bits to enable exceptions
handling in LLVM. Currently only on x86-32/linux.
In fact, this patch adds necessary intrinsics (and their lowering) which
represent really weird target-specific gcc builtins used inside unwinder.
After corresponding llvm-gcc patch will land (easy) exceptions should be
more or less workable. However, exceptions handling support should not be
thought as 'finished': I expect many small and not so small glitches
everywhere.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39855 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-14 14:06:15 +00:00
Dale Johannesen
e7e7d0d7e3
Skeleton of post-RA scheduler; doesn't do anything yet.
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Change name of -sched option and DEBUG_TYPE to
pre-RA-sched; adjust testcases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39816 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-13 17:13:54 +00:00
Lauro Ramos Venancio
75ce010f7b
Assert when TLS is not implemented.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39737 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-11 17:19:51 +00:00
Dan Gohman
532dc2e1f2
Change getCopyToParts and getCopyFromParts to always use target-endian
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register ordering, for both physical and virtual registers. Update the PPC
target lowering for calls to expect registers for the call result to
already be in target order.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38471 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-09 20:59:04 +00:00
Chris Lattner
87bdba6d6a
The various "getModuleMatchQuality" implementations should return
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zero if they see a target triple they don't understand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38463 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-09 17:25:29 +00:00
Evan Cheng
06aae67b83
Do away with ImmutablePredicateOperand.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37961 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-06 23:22:46 +00:00
Gabor Greif
a99be51bf5
Here is the bulk of the sanitizing.
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Almost all occurrences of "bytecode" in the sources have been eliminated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37913 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-05 17:07:56 +00:00
Evan Cheng
7e36966de4
PPC conditional branch predicate does not change after isel.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37893 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-05 07:09:50 +00:00
John Criswell
e644ef7b09
Convert .cvsignore files
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37801 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-29 16:35:07 +00:00
Evan Cheng
2bda17c922
Prevent PPC::BCC first operand, the PRED number, from being isel'd into a LI instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37790 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-29 01:25:06 +00:00
Dan Gohman
ea859be53c
Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from
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TargetLowering to SelectionDAG so that they have more convenient
access to the current DAG, in preparation for the ValueType routines
being changed from standalone functions to members of SelectionDAG for
the pre-legalize vector type changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37704 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-22 14:59:07 +00:00
Chris Lattner
3ee774091b
describe an argument, hide it.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37650 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-19 05:46:06 +00:00
Chris Lattner
52387be1e0
If a function is vararg, never pass inreg arguments in registers. Thanks to
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Anton for half of this patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37641 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-19 00:13:10 +00:00
Dan Gohman
51eaa86758
Rename MVT::getVectorBaseType to MVT::getVectorElementType.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37579 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-14 22:58:02 +00:00
Dale Johannesen
13e8b51e3e
Handle blocks with 2 unconditional branches in AnalyzeBranch.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37571 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-13 17:59:52 +00:00
Evan Cheng
bfd2ec4a8e
Add a utility routine to check for unpredicated terminator instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37528 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-08 21:59:56 +00:00
Nicolas Geoffray
2fb813d70b
Implementation of compilation callback in PPC ELF32
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37340 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-29 16:33:18 +00:00
Dale Johannesen
e6e435498c
name change requested by review of previous patch
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37289 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-22 18:31:04 +00:00