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Author SHA1 Message Date
Artur Pilipenko a4e52312e8 [DAGCombiner] Support {a|s}ext, {a|z|s}ext load nodes in load combine 
Resubmit r295336 after the bug with non-zero offset patterns on BE targets is fixed (r296336).

Support {a|s}ext, {a|z|s}ext load nodes as a part of load combine patters.

Reviewed By: filcab

Differential Revision: https://reviews.llvm.org/D29591


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296651 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-03-01 18:12:29 +00:00
Matt Arsenault eaeac1f1aa AMDGPU: Re-do update for branch-relaxation test 
Modify the test so that it is still testing something
closer to what it was intended to originally.

I think the original intent was to test the situation where
there was a branch on execz and then unconditional branch
required relaxing.With the change in r296539,
there was no longer and execz branch.

Change the test so that there is now an execz branch inserted.
There is no longer an unconditional branch after the execz branch,
so this might need to be tricked in some other way to keep that
there.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296574 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-03-01 03:36:04 +00:00
Daniel Berlin f5d4310169 Update AMDGPU test branch-relaxation.ll for changes after post-dom fixes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296539 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-02-28 23:35:24 +00:00
Nirav Dave bfdb3f2a5a In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled. 
Recommiting after fixup of 32-bit aliasing sign offset bug in DAGCombiner.

    * Simplify Consecutive Merge Store Candidate Search

    Now that address aliasing is much less conservative, push through
    simplified store merging search and chain alias analysis which only
    checks for parallel stores through the chain subgraph. This is cleaner
    as the separation of non-interfering loads/stores from the
    store-merging logic.

    When merging stores search up the chain through a single load, and
    finds all possible stores by looking down from through a load and a
    TokenFactor to all stores visited.

    This improves the quality of the output SelectionDAG and the output
    Codegen (save perhaps for some ARM cases where we correctly constructs
    wider loads, but then promotes them to float operations which appear
    but requires more expensive constant generation).

    Some minor peephole optimizations to deal with improved SubDAG shapes (listed below)

    Additional Minor Changes:

      1. Finishes removing unused AliasLoad code

      2. Unifies the chain aggregation in the merged stores across code
         paths

      3. Re-add the Store node to the worklist after calling
         SimplifyDemandedBits.

      4. Increase GatherAllAliasesMaxDepth from 6 to 18. That number is
         arbitrary, but seems sufficient to not cause regressions in
         tests.

      5. Remove Chain dependencies of Memory operations on CopyfromReg
         nodes as these are captured by data dependence

      6. Forward loads-store values through tokenfactors containing
          {CopyToReg,CopyFromReg} Values.

      7. Peephole to convert buildvector of extract_vector_elt to
         extract_subvector if possible (see
         CodeGen/AArch64/store-merge.ll)

      8. Store merging for the ARM target is restricted to 32-bit as
         some in some contexts invalid 64-bit operations are being
         generated. This can be removed once appropriate checks are
         added.

    This finishes the change Matt Arsenault started in r246307 and
    jyknight's original patch.

    Many tests required some changes as memory operations are now
    reorderable, improving load-store forwarding. One test in
    particular is worth noting:

      CodeGen/PowerPC/ppc64-align-long-double.ll - Improved load-store
      forwarding converts a load-store pair into a parallel store and
      a memory-realized bitcast of the same value. However, because we
      lose the sharing of the explicit and implicit store values we
      must create another local store. A similar transformation
      happens before SelectionDAG as well.

    Reviewers: arsenm, hfinkel, tstellarAMD, jyknight, nhaehnle

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296476 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-02-28 14:24:15 +00:00
Matt Arsenault dd2186aaab AMDGPU: Use v_med3_{f16|i16|u16} 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296401 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-02-27 22:40:39 +00:00
Matt Arsenault 27f4f2f4bc AMDGPU: Support v2i16/v2f16 packed operations 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296396 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-02-27 22:15:25 +00:00
Matt Arsenault a4e4156e12 AMDGPU: Support inlineasm for packed instructions 
Add packed types as legal so they may be used with inlineasm.
Keep all operations expanded for now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296379 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-02-27 20:52:10 +00:00
Matt Arsenault 132ab30572 AMDGPU: Don't fold immediate if clamp/omod are set 
Doesn't fix any practical problems because clamp/omod
are currently folded after peephole optimizer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296375 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-02-27 20:21:31 +00:00
Matt Arsenault dd23defd5c AMDGPU: Fold omod into instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296372 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-02-27 19:35:42 +00:00
Matt Arsenault 29df731fe5 AMDGPU: Add f16 to shader calling conventions 
Mostly useful for writing tests for f16 features.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296370 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-02-27 19:24:47 +00:00
Nirav Dave b89cc7e5e3 Revert "In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled." 
This reverts commit r296252 until 256-bit operations are more efficiently generated in X86.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296279 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-02-26 01:27:32 +00:00
Nirav Dave 32147cef64 In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled. 
Recommiting after fixup of 32-bit aliasing sign offset bug in DAGCombiner.

    * Simplify Consecutive Merge Store Candidate Search

    Now that address aliasing is much less conservative, push through
    simplified store merging search and chain alias analysis which only
    checks for parallel stores through the chain subgraph. This is cleaner
    as the separation of non-interfering loads/stores from the
    store-merging logic.

    When merging stores search up the chain through a single load, and
    finds all possible stores by looking down from through a load and a
    TokenFactor to all stores visited.

    This improves the quality of the output SelectionDAG and the output
    Codegen (save perhaps for some ARM cases where we correctly constructs
    wider loads, but then promotes them to float operations which appear
    but requires more expensive constant generation).

    Some minor peephole optimizations to deal with improved SubDAG shapes (listed below)

    Additional Minor Changes:

      1. Finishes removing unused AliasLoad code

      2. Unifies the chain aggregation in the merged stores across code
         paths

      3. Re-add the Store node to the worklist after calling
         SimplifyDemandedBits.

      4. Increase GatherAllAliasesMaxDepth from 6 to 18. That number is
         arbitrary, but seems sufficient to not cause regressions in
         tests.

      5. Remove Chain dependencies of Memory operations on CopyfromReg
         nodes as these are captured by data dependence

      6. Forward loads-store values through tokenfactors containing
          {CopyToReg,CopyFromReg} Values.

      7. Peephole to convert buildvector of extract_vector_elt to
         extract_subvector if possible (see
         CodeGen/AArch64/store-merge.ll)

      8. Store merging for the ARM target is restricted to 32-bit as
         some in some contexts invalid 64-bit operations are being
         generated. This can be removed once appropriate checks are
         added.

    This finishes the change Matt Arsenault started in r246307 and
    jyknight's original patch.

    Many tests required some changes as memory operations are now
    reorderable, improving load-store forwarding. One test in
    particular is worth noting:

      CodeGen/PowerPC/ppc64-align-long-double.ll - Improved load-store
      forwarding converts a load-store pair into a parallel store and
      a memory-realized bitcast of the same value. However, because we
      lose the sharing of the explicit and implicit store values we
      must create another local store. A similar transformation
      happens before SelectionDAG as well.

    Reviewers: arsenm, hfinkel, tstellarAMD, jyknight, nhaehnle

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296252 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-02-25 11:43:58 +00:00
Wei Ding 5d1e915557 AMDGPU : Replace FMAD with FMA when denormals are enabled. 
Differential Revision: http://reviews.llvm.org/D29958

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296186 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-02-24 23:00:29 +00:00
Stanislav Mekhanoshin fef0dbe59c Revert "Correct register pressure calculation in presence of subregs" 
This reverts commit r296009. It broke one out of tree target and also
does not account for all partial lines added or removed when calculating
PressureDiff.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296182 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-02-24 21:56:16 +00:00
Sanjay Patel 9a9478ccb0 [DAGCombiner] add missing folds for scalar select of {-1,0,1} 
The motivation for filling out these select-of-constants cases goes back to D24480, 
where we discussed removing an IR fold from add(zext) --> select. And that goes back to:
https://reviews.llvm.org/rL75531
https://reviews.llvm.org/rL159230

The idea is that we should always canonicalize patterns like this to a select-of-constants 
in IR because that's the smallest IR and the best for value tracking. Note that we currently 
do the opposite in some cases (like the cases in *this* patch). Ie, the proposed folds in 
this patch already exist in InstCombine today:
https://github.com/llvm-mirror/llvm/blob/master/lib/Transforms/InstCombine/InstCombineSelect.cpp#L1151

As this patch shows, most targets generate better machine code for simple ext/add/not ops 
rather than a select of constants. So the follow-up steps to make this less of a patchwork 
of special-case folds and missing IR canonicalization:

1. Have DAGCombiner convert any select of constants into ext/add/not ops.
2  Have InstCombine canonicalize in the other direction (create more selects).

Differential Revision: https://reviews.llvm.org/D30180


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296137 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-02-24 17:17:33 +00:00
Stanislav Mekhanoshin 0bf4d71d50 Correct register pressure calculation in presence of subregs 
If a subreg is used in an instruction it counts as a whole superreg
for the purpose of register pressure calculation. This patch corrects
improper register pressure calculation by examining operand's lane mask.

Differential Revision: https://reviews.llvm.org/D29835

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296009 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-02-23 20:19:44 +00:00
Jan Vesely dae323db22 AMDGPU/SI: Fix trunc i16 pattern 
Hit on ASICs that support 16bit instructions.

Differential Revision: https://reviews.llvm.org/D30281

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295990 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-02-23 16:12:21 +00:00
Matt Arsenault 32a81bbff2 AMDGPU: Add another BFE pattern 
This is the pattern that falls out of the instruction's
definition if offset == 0.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295912 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-02-23 00:23:43 +00:00
Matt Arsenault cd39b42cab AMDGPU: Use clamp with f64 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295908 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-02-22 23:53:37 +00:00
Matt Arsenault e184e01dd7 AMDGPU: Fold FP clamp as modifier bit 
The manual is unclear on the details of this. It's not
clear to me if denormals are not allowed with clamp,
or if that is only omod. Not allowing denorms for
fp16 or fp64 isn't useful so I also question if that
is really a restriction. Same with whether this is valid
without IEEE mode enabled.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295905 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-02-22 23:27:53 +00:00
Wei Ding 1cfed01e02 AMDGPU : Update TrapCode based on Trap Handler ABI. 
Differential Revision: http://reviews.llvm.org/D30232

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295904 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-02-22 23:22:19 +00:00
Matt Arsenault c2d34b5027 AMDGPU: Add replacement bfe intrinsics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295899 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-02-22 23:04:58 +00:00
Matt Arsenault 206dfa3c0d AMDGPU: Don't add emergency stack slot if all spills are SGPR->VGPR 
This should avoid reporting any stack needs to be allocated in the
case where no stack is truly used. An unused stack slot is still
left around in other cases where there are real stack objects
but no spilling occurs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295891 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-02-22 22:23:32 +00:00
Matt Arsenault c1d17d5f71 AMDGPU: Don't look at chain users when adjusting writemask 
Fixes not adjusting using new intrinsics with chains.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295878 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-02-22 21:16:41 +00:00
Matt Arsenault 138d429065 AMDGPU: Always allocate emergency stack slot at offset 0 
This allows us to ensure that 0 is never a valid pointer
to a user object, and ensures that the offset is always legal
without needing a register to access it. This comes at the cost
of usable offsets and wasted stack space.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295877 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-02-22 21:05:25 +00:00
Matt Arsenault 1b020b3be5 AMDGPU: Change exp with compr bit printing 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295873 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-02-22 20:37:12 +00:00
Wei Ding 9b1c9472f5 Revert "AMDGPU : Update TrapCode based on Trap Handler ABI." 
This reverts commit r295867.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295871 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-02-22 20:29:22 +00:00
Wei Ding d70493f450 AMDGPU : Update TrapCode based on Trap Handler ABI. 
Differential Revision: http://reviews.llvm.org/D30232

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295867 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-02-22 20:05:06 +00:00
Bill Seurer 6ef315bddb [DAGCombiner] revert r295336 
r295336 causes a bootstrapped clang to fail for many compilations on
powerpc BE.  See 
http://lab.llvm.org:8011/builders/clang-ppc64be-linux-multistage/builds/2315
for example.

Reverting as per the developer's request.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295849 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-02-22 16:27:33 +00:00
Matt Arsenault 7d65faa5cc AMDGPU: Add cvt.pkrtz intrinsic 
Convert llvm.SI.packf16 test uses

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295797 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-02-22 00:27:34 +00:00
Matt Arsenault 7d9379397a AMDGPU: Remove some uses of llvm.SI.export in tests 
Merge some of the old, smaller tests into more complete versions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295792 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-02-22 00:02:21 +00:00
Matt Arsenault 6de2a82753 AMDGPU: Remove llvm.AMDGPU.clamp intrinsic 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295789 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-02-21 23:46:04 +00:00
Matt Arsenault aac82e218f AMDGPU: Redefine clamp node as clamp 0.0-1.0 
Change implementation to use max instead of add.
min/max/med3 do not flush denormals regardless of the mode,
so it is OK to use it whether or not they are enabled.

Also allow using clamp with f16, and use knowledge
of dx10_clamp.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295788 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-02-21 23:35:48 +00:00
Matt Arsenault 8a7ccd7129 AMDGPU: Remove dead declarations in tests 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295757 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-02-21 19:31:33 +00:00
Matt Arsenault f2616d2fd3 AMDGPU: Remove llvm.AMDGPU.flbit intrinsic 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295754 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-02-21 19:27:33 +00:00
Matt Arsenault bcb6a77aca AMDGPU: Don't use stack space for SGPR->VGPR spills 
Before frame offsets are calculated, try to eliminate the
frame indexes used by SGPR spills. Then we can delete them
after.

I think for now we can be sure that no other instruction
will be re-using the same frame indexes. It should be easy
to notice if this assumption ever breaks since everything
asserts if it tries to use a dead frame index later.

The unused emergency stack slot seems to still be left behind,
so an additional 4 bytes is still wasted.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295753 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-02-21 19:12:08 +00:00
NAKAMURA Takumi 7cca07f9d6 llvm/test/CodeGen/AMDGPU/r600.alu-limits.ll should require +Asserts. This would run into infinite loop anyways with -Asserts. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295591 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-02-19 02:31:06 +00:00
Matt Arsenault 83c857cd3a AMDGPU: Merge initial gfx9 support 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295554 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-02-18 18:29:53 +00:00
Jan Vesely aa04f11f4a AMDGPU/R600: Assert on infinite loop in EmitClauseMarkers 
Differential Revision: https://reviews.llvm.org/D29792

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295539 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-02-18 04:24:10 +00:00
Justin Bogner a39b1ce61f Verifier: Disallow a line number without a file in DISubprogram 
A line number doesn't make much sense if you don't say where it's
from. Add a verifier check for this and update some tests that had
bogus debug info.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295516 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-02-17 23:57:42 +00:00
Matt Arsenault 0f6af2352e AMDGPU: Fix crashes on invalid icmp/fcmp intrinsics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295489 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-02-17 19:49:10 +00:00
Matt Arsenault 0b229143d8 AMDGPU: Remove llvm.AMDGPU.cube intrinsic 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295359 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-02-16 19:09:04 +00:00
Matt Arsenault 81cfbfa738 AMDGPU: Remove llvm.AMDGPU.rsq intrinsic 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295358 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-02-16 19:08:58 +00:00
Artur Pilipenko e97e1b5918 [DAGCombiner] Support {a|s}ext, {a|z|s}ext load nodes in load combine 
Resubmit -r295314 with PowerPC and AMDGPU tests updated.

Support {a|s}ext, {a|z|s}ext load nodes as a part of load combine patters.

Reviewed By: filcab

Differential Revision: https://reviews.llvm.org/D29591


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295336 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-02-16 17:07:27 +00:00
Matt Arsenault 61239b090d AMDGPU: Remove llvm.SI.sendmsg 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295270 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-02-16 02:01:17 +00:00
Matt Arsenault a0240d6d1a AMDGPU: Remove SI_fs_constant and SI_fs_interp intrinsics 
Update test uses with expansion in terms of new intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295269 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-02-16 02:01:13 +00:00
Matt Arsenault a93bc6c253 AMDGPU: Consolidate sendmsg/sendmsghalt handling and tests 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295244 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-02-15 22:17:09 +00:00
Kyle Butt a466b368fe Codegen: Make chains from trellis-shaped CFGs 
Lay out trellis-shaped CFGs optimally.
A trellis of the shape below:

  A     B
  |\   /|
  | \ / |
  |  X  |
  | / \ |
  |/   \|
  C     D

would be laid out A; B->C ; D by the current layout algorithm. Now we identify
trellises and lay them out either A->C; B->D or A->D; B->C. This scales with an
increasing number of predecessors. A trellis is a a group of 2 or more
predecessor blocks that all have the same successors.

because of this we can tail duplicate to extend existing trellises.

As an example consider the following CFG:

    B   D   F   H
   / \ / \ / \ / \
  A---C---E---G---Ret

Where A,C,E,G are all small (Currently 2 instructions).

The CFG preserving layout is then A,B,C,D,E,F,G,H,Ret.

The current code will copy C into B, E into D and G into F and yield the layout
A,C,B(C),E,D(E),F(G),G,H,ret

define void @straight_test(i32 %tag) {
entry:
  br label %test1
test1: ; A
  %tagbit1 = and i32 %tag, 1
  %tagbit1eq0 = icmp eq i32 %tagbit1, 0
  br i1 %tagbit1eq0, label %test2, label %optional1
optional1: ; B
  call void @a()
  br label %test2
test2: ; C
  %tagbit2 = and i32 %tag, 2
  %tagbit2eq0 = icmp eq i32 %tagbit2, 0
  br i1 %tagbit2eq0, label %test3, label %optional2
optional2: ; D
  call void @b()
  br label %test3
test3: ; E
  %tagbit3 = and i32 %tag, 4
  %tagbit3eq0 = icmp eq i32 %tagbit3, 0
  br i1 %tagbit3eq0, label %test4, label %optional3
optional3: ; F
  call void @c()
  br label %test4
test4: ; G
  %tagbit4 = and i32 %tag, 8
  %tagbit4eq0 = icmp eq i32 %tagbit4, 0
  br i1 %tagbit4eq0, label %exit, label %optional4
optional4: ; H
  call void @d()
  br label %exit
exit:
  ret void
}

here is the layout after D27742:
straight_test:                          # @straight_test
; ... Prologue elided
; BB#0:                                 # %entry ; A (merged with test1)
; ... More prologue elided
	mr 30, 3
	andi. 3, 30, 1
	bc 12, 1, .LBB0_2
; BB#1:                                 # %test2 ; C
	rlwinm. 3, 30, 0, 30, 30
	beq	 0, .LBB0_3
	b .LBB0_4
.LBB0_2:                                # %optional1 ; B (copy of C)
	bl a
	nop
	rlwinm. 3, 30, 0, 30, 30
	bne	 0, .LBB0_4
.LBB0_3:                                # %test3 ; E
	rlwinm. 3, 30, 0, 29, 29
	beq	 0, .LBB0_5
	b .LBB0_6
.LBB0_4:                                # %optional2 ; D (copy of E)
	bl b
	nop
	rlwinm. 3, 30, 0, 29, 29
	bne	 0, .LBB0_6
.LBB0_5:                                # %test4 ; G
	rlwinm. 3, 30, 0, 28, 28
	beq	 0, .LBB0_8
	b .LBB0_7
.LBB0_6:                                # %optional3 ; F (copy of G)
	bl c
	nop
	rlwinm. 3, 30, 0, 28, 28
	beq	 0, .LBB0_8
.LBB0_7:                                # %optional4 ; H
	bl d
	nop
.LBB0_8:                                # %exit ; Ret
	ld 30, 96(1)                    # 8-byte Folded Reload
	addi 1, 1, 112
	ld 0, 16(1)
	mtlr 0
	blr

The tail-duplication has produced some benefit, but it has also produced a
trellis which is not laid out optimally. With this patch, we improve the layouts
of such trellises, and decrease the cost calculation for tail-duplication
accordingly.

This patch produces the layout A,C,E,G,B,D,F,H,Ret. This layout does have
back edges, which is a negative, but it has a bigger compensating
positive, which is that it handles the case where there are long strings
of skipped blocks much better than the original layout. Both layouts
handle runs of executed blocks equally well. Branch prediction also
improves if there is any correlation between subsequent optional blocks.

Here is the resulting concrete layout:

straight_test:                          # @straight_test
; BB#0:                                 # %entry ; A (merged with test1)
	mr 30, 3
	andi. 3, 30, 1
	bc 12, 1, .LBB0_4
; BB#1:                                 # %test2 ; C
	rlwinm. 3, 30, 0, 30, 30
	bne	 0, .LBB0_5
.LBB0_2:                                # %test3 ; E
	rlwinm. 3, 30, 0, 29, 29
	bne	 0, .LBB0_6
.LBB0_3:                                # %test4 ; G
	rlwinm. 3, 30, 0, 28, 28
	bne	 0, .LBB0_7
	b .LBB0_8
.LBB0_4:                                # %optional1 ; B (Copy of C)
	bl a
	nop
	rlwinm. 3, 30, 0, 30, 30
	beq	 0, .LBB0_2
.LBB0_5:                                # %optional2 ; D (Copy of E)
	bl b
	nop
	rlwinm. 3, 30, 0, 29, 29
	beq	 0, .LBB0_3
.LBB0_6:                                # %optional3 ; F (Copy of G)
	bl c
	nop
	rlwinm. 3, 30, 0, 28, 28
	beq	 0, .LBB0_8
.LBB0_7:                                # %optional4 ; H
	bl d
	nop
.LBB0_8:                                # %exit

Differential Revision: https://reviews.llvm.org/D28522

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295223 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-02-15 19:49:14 +00:00
Stanislav Mekhanoshin aae13371be [AMDGPU] Revert failed scheduling 
This patch reverts region's scheduling to the original untouched state
in case if we have have decreased occupancy.

In addition it switches to use TargetRegisterInfo occupancy callback
for pressure limits instead of gradually increasing limits which were
just passed by. We are going to stay with the best schedule so we do
not need to tolerate worsened scheduling anymore.

Differential Revision: https://reviews.llvm.org/D29971

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295206 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-02-15 17:19:50 +00:00
Stanislav Mekhanoshin 237ec36765 [AMDGPU] Fix MaxWorkGroupsPerCU for large workgroups 
This patch corrects the maximum workgroups per CU if we have big
workgroups (more than 128). This calculation contributes to the
occupancy calculation in respect to LDS size.

Differential Revision: https://reviews.llvm.org/D29974

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295134 91177308-0d34-0410-b5e6-96231b3b80d8
 2017-02-15 01:03:59 +00:00