166941 Commits

Author SHA1 Message Date
Florian Hahn
a5ec686ea5 Revert rL337292 due to another MSVC STL problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337303 91177308-0d34-0410-b5e6-96231b3b80d8
2018-07-17 17:12:50 +00:00
Simon Pilgrim
cc5fc42033 [llvm-mca][x86] Add BSWAP resource tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337302 91177308-0d34-0410-b5e6-96231b3b80d8
2018-07-17 17:10:47 +00:00
Sam Clegg
cf065f7118 [WebAssembly] Update WebAssemblyLowerEmscriptenEHSjLj to handle separate compilation
Previously we were assuming whole program compilation. Now that
separate compilation is a thing we need to update this pass.
Firstly, it can no longer assert on the existence of malloc and free.
This functions might not be in the current translation unit.  If we
need them then we will generate not imports for them.

Secondly the global helper function we create should be marked as
weak since we will be generating a separate copy in each translation
unit.

Finally the names of the symbols used must be unique and fixed since
they need to agree across translation units.

Differential Revision: https://reviews.llvm.org/D49263

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337301 91177308-0d34-0410-b5e6-96231b3b80d8
2018-07-17 16:40:03 +00:00
Craig Topper
e40f77a66b [X86] Remove some standalone patterns in favor of the patterns in the MOVLPD instruction definitions.
Previously we passed 'null_frag' into the instruction definition. The multiclass is shared with MOVHPD which doesn't use null_frag. It turns out by passing X86Movsd it produces patterns equivalent to some standalone patterns.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337299 91177308-0d34-0410-b5e6-96231b3b80d8
2018-07-17 16:24:33 +00:00
Simon Pilgrim
b31fad1c7b [llvm-mca][x86] Add displacement-only and additional scale=1 LEA tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337298 91177308-0d34-0410-b5e6-96231b3b80d8
2018-07-17 16:17:33 +00:00
Simon Pilgrim
c1bbb5ef59 [llvm-mca][x86] Add LEA resource tests (PR32326)
Add llvm-mca tests demonstrating how LEA instructions are currently modelled. Once this is working on btver2 I'll copy the test file to the other target directories.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337297 91177308-0d34-0410-b5e6-96231b3b80d8
2018-07-17 16:13:29 +00:00
Matt Davis
95e53c2889 [llvm-mca][docs] Revert mca internals docs.
We're going to work on this in a separate review focusing more on documenting
the View and probably removing some of the less-interesting/less-useful pieces.

This reverts r337219,337225



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337295 91177308-0d34-0410-b5e6-96231b3b80d8
2018-07-17 16:11:54 +00:00
Andrea Di Biagio
1885077d4c [Tablegen][PredicateExpander] Fix a bug in expandCheckImmOperand.
Function `expandCheckImmOperand` should always check if the input machine
instruction is passed by reference before calling method `getOperand()` on it.

Found while working on a patch that relies on `expandCheckImmOperand` to expand
a scheduling predicate.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337294 91177308-0d34-0410-b5e6-96231b3b80d8
2018-07-17 16:11:37 +00:00
Sander de Smalen
eabdfbb4b2 [AArch64][SVE]: Integer multiply-add/subtract instructions.
This patch adds support for the following instructions:
  MLA  mul-add, writing addend       (Zda = Zda +   Zn * Zm)
  MLS  mul-sub, writing addend       (Zda = Zda +  -Zn * Zm)
  MAD  mul-add, writing multiplicant (Zdn =  Za +  Zdn * Zm)
  MSB  mul-sub, writing multiplicant (Zdn =  Za + -Zdn * Zm)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337293 91177308-0d34-0410-b5e6-96231b3b80d8
2018-07-17 15:41:58 +00:00
Florian Hahn
a5d6389938 Recommit r334887: [SmallSet] Add SmallSetIterator.
Spell out destructor, copy/move constructor and assignment operators for
MSVC STL, where set<T>::const_iterator is not trivially copy constructible.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337292 91177308-0d34-0410-b5e6-96231b3b80d8
2018-07-17 15:24:19 +00:00
Petar Jovanovic
87d8be53fd [Mips][FastISel] Fix handling of icmp with i1 type
The Mips FastISel back-end does not extend i1 values while lowering icmp.
Ensure that we bail into DAG ISel when handling this case.

Patch by Dragan Mladjenovic.

Differential Revision: https://reviews.llvm.org/D49290


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337288 91177308-0d34-0410-b5e6-96231b3b80d8
2018-07-17 14:57:46 +00:00
Florian Hahn
35603461c5 [IPSCCP] Run Solve each time we resolved an undef in a function.
Once we resolved an undef in a function we can run Solve, which could
lead to finding a constant return value for the function, which in turn
could turn undefs into constants in other functions that call it, before
resolving undefs there.

Computationally the amount of work we are doing stays the same, just the
order we process things is slightly different and potentially there are
a few less undefs to resolve.

We are still relying on the order of functions in the IR, which means
depending on the order, we are able to resolve the optimal undef first
or not. For example, if @test1 comes before @testf, we find the constant
return value of @testf too late and we cannot use it while solving
@test1.

This on its own does not lead to more constants removed in the
test-suite, probably because currently we have to be very lucky to visit
applicable functions in the right order.

Maybe we manage to come up with a better way of resolving undefs in more
'profitable' functions first.

Reviewers: efriedma, mssimpso, davide

Reviewed By: efriedma, davide

Differential Revision: https://reviews.llvm.org/D49385


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337283 91177308-0d34-0410-b5e6-96231b3b80d8
2018-07-17 14:04:59 +00:00
Sander de Smalen
73739643d7 [AArch64][SVE] Asm: FP fused multiply-add/subtract instructions.
This patch adds support for the following instructions:

  FMLA    mul-add, writing addend                (Zda =  Zda +   Zn * Zm)
  FNMLA   negated mul-add, writing addend        (Zda = -Zda +  -Zn * Zm)

  FMLS    mul-sub, writing addend                (Zda =  Zda +  -Zn * Zm)
  FNMLS   negated mul-sub, writing addend        (Zda = -Zda +   Zn * Zm)

  FMAD    mul-add, writing multiplicant          (Zdn =  Za  +  Zdn * Zm)
  FNMAD   negated mul-add, writing multiplicant  (Zdn = -Za  + -Zdn * Zm)

  FMSB    mul-sub, writing multiplicant          (Zdn =  Za  + -Zdn * Zm)
  FNMSB   negated mul-sub, writing multiplicant  (Zdn = -Za  +  Zdn * Zm)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337282 91177308-0d34-0410-b5e6-96231b3b80d8
2018-07-17 13:58:46 +00:00
Simon Pilgrim
de720479bb [SLPVectorizer] Don't attempt horizontal reduction on pointer types (PR38191)
TTI::getMinMaxReductionCost typically can't handle pointer types - until this is changed its better to limit horizontal reduction to integer/float vector types only.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337280 91177308-0d34-0410-b5e6-96231b3b80d8
2018-07-17 13:43:33 +00:00
Tim Renouf
79ed3bcca7 More fixes for subreg join failure in RegCoalescer
Summary:
Part of the adjustCopiesBackFrom method wasn't correctly dealing with SubRange
intervals when updating.

2 changes. The first to ensure that bogus SubRange Segments aren't propagated when
encountering Segments of the form [1234r, 1234d:0) when preparing to merge value
numbers. These can be removed in this case.

The second forces a shrinkToUses call if SubRanges end on the copy index
(instead of just the parent register).

V2: Addressed review comments, plus MIR test instead of ll test

Subscribers: MatzeB, qcolombet, nhaehnle

Differential Revision: https://reviews.llvm.org/D40308

Change-Id: I1d2b2b4beea802fce11da01edf71feb2064aab05

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337273 91177308-0d34-0410-b5e6-96231b3b80d8
2018-07-17 12:38:39 +00:00
Sander de Smalen
5431fe06df [AArch64][SVE] Asm: Support for predicated FP operations (FP immediate)
This patch completes support for the following floating point
instructions that take FP immediates:
  FADD*  (addition)
  FSUB   (subtract)
  FSUBR  (subtract reverse form)
  FMUL*  (multiplication)
  FMAX*  (maximum)
  FMAXNM (maximum number)
  FMIN   (maximum)
  FMINNM (maximum number)

All operations are predicated and take a FP immediate operand,
e.g.

  fadd z0.h, p0/m, z0.h, #0.5
  fmin z0.s, p0/m, z0.s, #1.0
        ^___________^ (tied)

* Instructions added in a previous patch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337272 91177308-0d34-0410-b5e6-96231b3b80d8
2018-07-17 12:36:08 +00:00
Chen Zheng
1c105a00ab [NFC][testcases] add testcases for folding srem whose operands are negatived.
Finish same optimization for add instruction in D49216 and sdiv instruction in 
D49382. This patch is for srem instruction.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337270 91177308-0d34-0410-b5e6-96231b3b80d8
2018-07-17 12:31:54 +00:00
Joerg Sonnenberger
7d1879721b Don't assert that a size_t fits into 64bit.
Avoids tautological compare warnings on 32bit platforms.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337269 91177308-0d34-0410-b5e6-96231b3b80d8
2018-07-17 12:30:34 +00:00
whitequark
938172a55a [LLVM-C] Fix name mangling on AggressiveInstCombine
Similarly to rL336736, at least one more C API function does not
properly get declared as extern "C" due to a missing header, causing
name mangling and linking errors.

This patch fixes calls to LLVMAddAggressiveInstCombinerPass().

Differential Revision: https://reviews.llvm.org/D49416

Reviewed By: whitequark

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337264 91177308-0d34-0410-b5e6-96231b3b80d8
2018-07-17 11:13:58 +00:00
whitequark
1907eb80ac [LLVM-C] Add target triple normalization to the C API.
rL333307 was introduced to remove automatic target triple
normalization when calling sys::getDefaultTargetTriple(), arguing
that users of the latter already called Triple::normalize()
if necessary. However, users of the C API currently have no way of
doing target triple normalization.

This patch introduces an LLVMNormalizeTargetTriple function to
the C API which wraps Triple::normalize() and can be used on
the result of LLVMGetDefaultTargetTriple to achieve the same effect.

Differential Revision: https://reviews.llvm.org/D49414

Reviewed By: whitequark

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337263 91177308-0d34-0410-b5e6-96231b3b80d8
2018-07-17 10:57:39 +00:00
Benjamin Kramer
f948d85a47 [llvm-objcopy] Run not with any python, but the python configured in lit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337262 91177308-0d34-0410-b5e6-96231b3b80d8
2018-07-17 10:30:56 +00:00
Sander de Smalen
ca47e5e767 [AArch64][SVE] Asm: Support for predicated FP operations.
This patch adds support for the following floating point
instructions:
  FABD   (absolute difference)
  FADD   (addition)
  FSUB   (subtract)
  FSUBR  (subtract reverse form)
  FDIV   (divide)
  FDIVR  (divide reverse form)
  FMAX   (maximum)
  FMAXNM (maximum number)
  FMIN   (minimum)
  FMINNM (minimum number)
  FSCALE (adjust exponent)
  FMULX  (multiply extended)

All operations are predicated and binary form, e.g.

  fadd z0.h, p0/m, z0.h, z1.h
        ^___________^ (tied)

Supporting 16, 32 and 64-bit FP elements.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337259 91177308-0d34-0410-b5e6-96231b3b80d8
2018-07-17 09:48:57 +00:00
Simon Pilgrim
ead04a9559 [DAGCombiner] Call SimplifyDemandedVectorElts from EXTRACT_VECTOR_ELT
If we are only extracting vector elements via EXTRACT_VECTOR_ELT(s) we may be able to use SimplifyDemandedVectorElts to avoid unnecessary vector ops.

Differential Revision: https://reviews.llvm.org/D49262

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337258 91177308-0d34-0410-b5e6-96231b3b80d8
2018-07-17 09:45:35 +00:00
Simon Pilgrim
15fa57ae79 Fix MSVC "result of 32-bit shift implicitly converted to 64 bits" warning. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337257 91177308-0d34-0410-b5e6-96231b3b80d8
2018-07-17 09:39:55 +00:00
Sander de Smalen
6151dbec93 [AArch64][SVE] Asm: Support for SPLICE instruction.
The SPLICE instruction splices two vectors into one vector using a
predicate. It copies the active elements from the first vector, and
then fills the remaining elements with the low-numbered elements from
the second vector.

The instruction has the following form, e.g.

  splice z0.b, p0, z0.b, z1.b

for 8-bit elements. It also supports 16, 32 and
64-bit elements.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337253 91177308-0d34-0410-b5e6-96231b3b80d8
2018-07-17 08:52:45 +00:00
Sander de Smalen
46f56568b2 [AArch64][SVE] Asm: Support for EXT instruction.
This patch adds an instruction that allows extracting
a vector from a pair of vectors, given an immediate index
that describes the element position to extract from.

The instruction has the following assembly:
  ext z0.b, z0.b, z1.b, #imm

where #imm is an immediate between 0 and 255.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337251 91177308-0d34-0410-b5e6-96231b3b80d8
2018-07-17 08:39:48 +00:00
Craig Topper
7468eaa74b [X86] Properly qualify some MOVSS/MOVSD patterns with OptSize.
These are integer versions of patterns that I already fixed for floating point.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337240 91177308-0d34-0410-b5e6-96231b3b80d8
2018-07-17 06:24:16 +00:00
Daniel Cederman
00e3426bc2 [Sparc] Do not depend on icc for ta 1
The ta instruction will always trap, regardless of the value
of the integer condition codes. TRAPri is marked as using icc,
so we cannot use a pattern for TRAPri to implement ta 1, as
verify-machineinstrs can complain that icc is not defined.
Instead we implement ta 1 the same way as ta 5.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337236 91177308-0d34-0410-b5e6-96231b3b80d8
2018-07-17 05:49:33 +00:00
Craig Topper
7904f0b1e7 [X86] Add full set of patterns for turning ceil/floor/trunc/rint/nearbyint into rndscale with loads, broadcast, and masking.
This amounts to pretty ridiculous number of patterns. Ideally we'd canonicalize the X86ISD::VRNDSCALE earlier to reuse those patterns. I briefly looked into doing that, but some strict FP operations could still get converted to rint and nearbyint during isel. It's probably still worthwhile to look into. This patch is meant as a starting point to work from.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337234 91177308-0d34-0410-b5e6-96231b3b80d8
2018-07-17 05:48:48 +00:00
Craig Topper
605986cfaf [X86] Add test cases for selecting floor/ceil/trunc/rint/nearbyint to rndscale with masking, loading, and broadcasting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337233 91177308-0d34-0410-b5e6-96231b3b80d8
2018-07-17 05:48:46 +00:00
Chen Zheng
d13c7c50a3 [testcases] move testcases to right place - NFC
Differential Revision: https://reviews.llvm.org/D49409


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337230 91177308-0d34-0410-b5e6-96231b3b80d8
2018-07-17 01:04:41 +00:00
Matt Davis
40b80a4e12 [llvm-mca][docs] Add notes about cycle and resource callbacks. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337225 91177308-0d34-0410-b5e6-96231b3b80d8
2018-07-16 23:50:53 +00:00
Craig Topper
1fbf51fadc [X86] Add a missing FMA3 scalar intrinsic pattern.
This allows us to use 231 form to fold an insertelement on the add input to the fma. There is technically no software intrinsic that can use this until AVX512F, but it can be manually built up from other intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337223 91177308-0d34-0410-b5e6-96231b3b80d8
2018-07-16 23:10:58 +00:00
Sam Clegg
2a147a1507 [WebAssembly] Remove ELF file support.
This support was partial and temporary.  Now that we have
wasm object file support its no longer needed.

Differential Revision: https://reviews.llvm.org/D48744

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337222 91177308-0d34-0410-b5e6-96231b3b80d8
2018-07-16 23:09:29 +00:00
Sanjay Patel
bb12f48c1c [Intrinsics] define funnel shift IR intrinsics + DAG builder support
As discussed here:
http://lists.llvm.org/pipermail/llvm-dev/2018-May/123292.html
http://lists.llvm.org/pipermail/llvm-dev/2018-July/124400.html

We want to add rotate intrinsics because the IR expansion of that pattern is 4+ instructions, 
and we can lose pieces of the pattern before it gets to the backend. Generalizing the operation 
by allowing 2 different input values (plus the 3rd shift/rotate amount) gives us a "funnel shift" 
operation which may also be a single hardware instruction.

Initially, I thought we needed to define new DAG nodes for these ops, and I spent time working 
on that (much larger patch), but then I concluded that we don't need it. At least as a first 
step, we have all of the backend support necessary to match these ops...because it was required. 
And shepherding these through the IR optimizer is the primary concern, so the IR intrinsics are 
likely all that we'll ever need.

There was also a question about converting the intrinsics to the existing ROTL/ROTR DAG nodes
(along with improving the oversized shift documentation). Again, I don't think that's strictly 
necessary (as the test results here prove). That can be an efficiency improvement as a small 
follow-up patch.

So all we're left with is documentation, definition of the IR intrinsics, and DAG builder support. 

Differential Revision: https://reviews.llvm.org/D49242


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337221 91177308-0d34-0410-b5e6-96231b3b80d8
2018-07-16 22:59:31 +00:00
Puyan Lotfi
41306baa27 [NFC][llvm-objcopy] Make helper functions static
Anywhere in tools/llvm-objcopy where functions or classes are not referenced
outside of a given file, we change things to make the function or class static
or put inside an anonymous namespace.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337220 91177308-0d34-0410-b5e6-96231b3b80d8
2018-07-16 22:17:05 +00:00
Matt Davis
9dce11c0cf [llvm-mca][docs] Initial description of mca internals. NFC
This patch introduces a brief description of the components of MCA.  The main
focus is on Views.   This is a work in progress, and more descriptions will be
introduced later.  I want to flesh-out the Views section more and provide a
detailed description of eventing in MCA.  Eventually a brief code example of a
View should accompany the description.

Also, we should consider moving the MCA internals guide elsewhere at some point.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337219 91177308-0d34-0410-b5e6-96231b3b80d8
2018-07-16 21:42:58 +00:00
Zachary Turner
d554de1ec8 Add missing includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337218 91177308-0d34-0410-b5e6-96231b3b80d8
2018-07-16 21:34:25 +00:00
Zachary Turner
937d2c0dee [LLVMDemangle] Move some utility classes to header files.
In a followup I'm looking to add a Microsoft demangler.  Doing
so needs a lot of the same utility classes and feature test
macros which are already implemented in ItaniumDemangle.cpp.
So move all of these things into header files so that they
can be re-used by a new demangler.

Differential Revision: https://reviews.llvm.org/D49399

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337217 91177308-0d34-0410-b5e6-96231b3b80d8
2018-07-16 21:24:03 +00:00
Roman Lebedev
e5c7b32694 [NFC][InstCombine] Fine-tune 'check for [no] signed truncation' tests
We are using i8 for these tests, and shifting by 4,
which is exactly the half of i8.

But as it is seen from the proofs https://rise4fun.com/Alive/mgu
KeptBits = bitwidth(%x) - MaskedBits,
so with using shifts by 4, we are not really testing that
we actually properly handle the other cases with shifts not by half...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337208 91177308-0d34-0410-b5e6-96231b3b80d8
2018-07-16 20:10:46 +00:00
Jake Ehrlich
51e4fb6e38 [llvm-objcopy] Add support for large indexes
This patch is an update of an older patch that never landed
(see here: https://reviews.llvm.org/D42516)

Recently various users have run into this issue and it just 100%
has to be solved at this point. The main difference in this patch
is that I use gunzip instead of unzip which should hopefully allow
tests to pass. Please review this as if it is a new patch however.
I found some issues along the way and made some minor modifications.

The binary used in this patch for testing (a zip file to make it small)
can be found here:
https://drive.google.com/file/d/1UjsnTO9edLttZibbr-2T1bJl92KEQFAO/view?usp=sharing

Differential Revision: https://reviews.llvm.org/D49206

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337204 91177308-0d34-0410-b5e6-96231b3b80d8
2018-07-16 19:48:52 +00:00
Fangrui Song
7d88286b7c [CodeGen] Fix inconsistent declaration parameter name
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337200 91177308-0d34-0410-b5e6-96231b3b80d8
2018-07-16 18:51:40 +00:00
Farhana Aleen
ac8c393bd5 [AMDGPU] [AMDGPU] Support a fdot2 pattern.
Summary: Optimize fma((float)S0.x, (float)S1.x fma((float)S0.y, (float)S1.y, z))
                   -> fdot2((v2f16)S0, (v2f16)S1, (float)z)

Author: FarhanaAleen

Reviewed By: rampitec, b-sumner

Subscribers: AMDGPU

Differential Revision: https://reviews.llvm.org/D49146

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337198 91177308-0d34-0410-b5e6-96231b3b80d8
2018-07-16 18:19:59 +00:00
Mandeep Singh Grang
bffcc487e3 [llvm] Change 2 instances of std::sort to llvm::sort
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337192 91177308-0d34-0410-b5e6-96231b3b80d8
2018-07-16 17:26:37 +00:00
Roman Lebedev
a5425a350e [InstCombine] Fold 'check for [no] signed truncation' pattern
Summary:
[[ https://bugs.llvm.org/show_bug.cgi?id=38149 | PR38149 ]]

As discussed in https://reviews.llvm.org/D49179#1158957 and later,
the IR for 'check for [no] signed truncation' pattern can be improved:
https://rise4fun.com/Alive/gBf
^ that pattern will be produced by Implicit Integer Truncation sanitizer,
https://reviews.llvm.org/D48958 https://bugs.llvm.org/show_bug.cgi?id=21530
in signed case, therefore it is probably a good idea to improve it.

Proofs for this transform: https://rise4fun.com/Alive/mgu
This transform is surprisingly frustrating.
This does not deal with non-splat shift amounts, or with undef shift amounts.
I've outlined what i think the solution should be:
```
  // Potential handling of non-splats: for each element:
  //  * if both are undef, replace with constant 0.
  //    Because (1<<0) is OK and is 1, and ((1<<0)>>1) is also OK and is 0.
  //  * if both are not undef, and are different, bailout.
  //  * else, only one is undef, then pick the non-undef one.
```

The DAGCombine will reverse this transform, see
https://reviews.llvm.org/D49266

Reviewers: spatel, craig.topper

Reviewed By: spatel

Subscribers: JDevlieghere, rkruppe, llvm-commits

Differential Revision: https://reviews.llvm.org/D49320

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337190 91177308-0d34-0410-b5e6-96231b3b80d8
2018-07-16 16:45:42 +00:00
Wei Mi
735bf22bd7 [RegAlloc] Skip global splitting if the live range is huge and its spill is
trivially rematerializable.

We run into a case where machineLICM hoists a large number of live ranges
outside of a big loop because it thinks those live ranges are trivially
rematerializable. In regalloc, global splitting is tried out first for those
live ranges before they are spilled and rematerialized. Because the global
splitting algorithm is quadratic, increasing a lot of global splitting
candidates causes huge compile time increase (50s to 1400s on my local
machine when compiling a module).

However, we think for live ranges which are very large and are trivially
rematerialiable, it is better to just skip global splitting so as to save
compile time with little chance of sacrificing performance.  We uses the
segment size of live range to indirectly evaluate whether the global
splitting of the live range can introduce high cost, and use an option
as a knob to adjust the size limit threshold.

Differential Revision: https://reviews.llvm.org/D49353



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337186 91177308-0d34-0410-b5e6-96231b3b80d8
2018-07-16 15:42:20 +00:00
Teresa Johnson
92f5878901 Restore "[ThinLTO] Ensure we always select the same function copy to import"
This reverts commit r337081, therefore restoring r337050 (and fix in
r337059), with test fix for bot failure described after the original
description below.

In order to always import the same copy of a linkonce function,
even when encountering it with different thresholds (a higher one then a
lower one), keep track of the summary we decided to import.
This ensures that the backend only gets a single definition to import
for each GUID, so that it doesn't need to choose one.

Move the largest threshold the GUID was considered for import into the
current module out of the ImportMap (which is part of a larger map
maintained across the whole index), and into a new map just maintained
for the current module we are computing imports for. This saves some
memory since we no longer have the thresholds maintained across the
whole index (and throughout the in-process backends when doing a normal
non-distributed ThinLTO build), at the cost of some additional
information being maintained for each invocation of ComputeImportForModule
(the selected summary pointer for each import).

There is an additional map lookup for each callee being considered for
importing, however, this was able to subsume a map lookup in the
Worklist iteration that invokes computeImportForFunction. We also are
able to avoid calling selectCallee if we already failed to import at the
same or higher threshold.

I compared the run time and peak memory for the SPEC2006 471.omnetpp
benchmark (running in-process ThinLTO backends), as well as for a large
internal benchmark with a distributed ThinLTO build (so just looking at
the thin link time/memory). Across a number of runs with and without
this change there was no significant change in the time and memory.

(I tried a few other variations of the change but they also didn't
improve time or peak memory).

The new commit removes a test that no longer makes sense
(Transforms/FunctionImport/hotness_based_import2.ll), as exposed by the
reverse-iteration bot. The test depends on the order of processing the
summary call edges, and actually depended on the old problematic
behavior of selecting more than one summary for a given GUID when
encountered with different thresholds. There was no guarantee even
before that we would eventually pick the linkonce copy with the hottest
call edges, it just happened to work with the test and the old code, and
there was no guarantee that we would end up importing the selected
version of the copy that had the hottest call edges (since the backend
would effectively import only one of the selected copies).

Reviewers: davidxl

Subscribers: mehdi_amini, inglorion, llvm-commits

Differential Revision: https://reviews.llvm.org/D48670

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337184 91177308-0d34-0410-b5e6-96231b3b80d8
2018-07-16 15:30:27 +00:00
Joel Galenson
e27b1d0b0f [cfi-verify] Abort on unsupported targets
As suggested in the review for r337007, this makes cfi-verify abort on unsupported targets instead of producing incorrect results.  It also updates the design document to reflect this.

Differential Revision: https://reviews.llvm.org/D49304

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337181 91177308-0d34-0410-b5e6-96231b3b80d8
2018-07-16 15:26:44 +00:00
Chen Zheng
0a3ff05518 [InstrSimplify] add testcases for fold sdiv if two operands are negatived and non-overflow
Differential Revision: https://reviews.llvm.org/D49365


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337179 91177308-0d34-0410-b5e6-96231b3b80d8
2018-07-16 15:06:42 +00:00
Chandler Carruth
6311079393 [x86/SLH] Completely rework how we sink post-load hardening past data
invariant instructions to be both more correct and much more powerful.

While testing, I continued to find issues with sinking post-load
hardening. Unfortunately, it was amazingly hard to create any useful
tests of this because we were mostly sinking across copies and other
loading instructions. The fact that we couldn't sink past normal
arithmetic was really a big oversight.

So first, I've ported roughly the same set of instructions from the data
invariant loads to also have their non-loading varieties understood to
be data invariant. I've also added a few instructions that came up so
often it again made testing complicated: inc, dec, and lea.

With this, I was able to shake out a few nasty bugs in the validity
checking. We need to restrict to hardening single-def instructions with
defined registers that match a particular form: GPRs that don't have
a NOREX constraint directly attached to their register class.

The (tiny!) test case included catches all of the issues I was seeing
(once we can sink the hardening at all) except for the NOREX issue. The
only test I have there is horrible. It is large, inexplicable, and
doesn't even produce an error unless you try to emit encodings. I can
keep looking for a way to test it, but I'm out of ideas really.

Thanks to Ben for giving me at least a sanity-check review. I'll follow
up with Craig to go over this more thoroughly post-commit, but without
it SLH crashes everywhere so landing it for now.

Differential Revision: https://reviews.llvm.org/D49378

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337177 91177308-0d34-0410-b5e6-96231b3b80d8
2018-07-16 14:58:32 +00:00