Commit Graph

118270 Commits

Author SHA1 Message Date
Sanjay Patel aeeabb506a [VectorUtils] add funnel-shifts to the list of vectorizable intrinsics
This just identifies the intrinsics as candidates for vectorization.
It does not mean we will attempt to vectorize under normal conditions
(the test file is forcing vectorization). 

The cost model must be fixed to show that the transform is profitable 
in general.

Allowing vectorization with these intrinsics is required to avoid
potential regressions from canonicalizing to the intrinsics from
generic IR:
https://bugs.llvm.org/show_bug.cgi?id=37417



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346661 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-12 15:20:14 +00:00
Sanjay Patel 7b8a79a288 [VectorUtils] reorder list of vectorizable intrinsics; NFC
We need to add funnel-shifts to this list, so clean up
the random order before it gets worse.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346660 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-12 15:10:30 +00:00
Simon Pilgrim 789879d5be [CostModel] Add more realistic SK_ExtractSubvector generic costs.
Instead of defaulting to a cost = 1, expand to element extract/insert like we do for other shuffles.

This exposes an issue in LoopVectorize which could call SK_ExtractSubvector with a scalar subvector type.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346656 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-12 14:25:23 +00:00
Alex Bradbury c90bfa8715 [RISCV] Support .option relax and .option norelax
This extends the .option support from D45864 to enable/disable the relax 
feature flag from D44886

During parsing of the relax/norelax directives, the RISCV::FeatureRelax 
feature bits of the SubtargetInfo stored in the AsmParser are updated 
appropriately to reflect whether relaxation is currently enabled in the 
parser. When an instruction is parsed, the parser checks if relaxation is 
currently enabled and if so, gets a handle to the AsmBackend and sets the 
ForceRelocs flag. The AsmBackend uses a combination of the original 
RISCV::FeatureRelax feature bits set by e.g -mattr=+/-relax and the 
ForceRelocs flag to determine whether to emit relocations for symbol and 
branch diffs. Diff relocations should therefore only not be emitted if the 
relax flag was not set on the command line and no instruction was ever parsed 
in a section with relaxation enabled to ensure correct diffs are emitted.

Differential Revision: https://reviews.llvm.org/D46423
Patch by Lewis Revill.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346655 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-12 14:25:07 +00:00
Nirav Dave c5dba22c1d [DAGCombiner] Fix load-store forwarding of indexed loads.
Summary:
Handle extra output from index loads in cases where we wish to
forward a load value directly from a preceeding store.

Fixes PR39571.

Reviewers: peter.smith, rengolin

Subscribers: javed.absar, hiraditya, arphaman, llvm-commits

Differential Revision: https://reviews.llvm.org/D54265

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346654 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-12 14:05:40 +00:00
Philip Pfaffe 0c20a4d744 Add an OptimizerLast EP
Summary:
It turns out that we need an OptimizerLast PassBuilder extension point
after all. I missed the relevance of this EP the first time. By legacy PM magic,
function passes added at this EP get added to the last _Function_ PM, which is a
feature we lost when dropping this EP for the new PM.

A key difference between this and the legacy PassManager's OptimizerLast
callback is that this extension point is not triggered at O0. Extensions
to the O0 pipeline should append their passes to the end of the overall
pipeline.

Differential Revision: https://reviews.llvm.org/D54374

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346645 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-12 11:17:07 +00:00
Max Kazantsev 8e59cd1915 [LICM] Hoist guards from non-header blocks
This patch relaxes overconservative checks on whether or not we could write
memory before we execute an instruction. This allows us to hoist guards out of
loops even if they are not in the header block.

Differential Revision: https://reviews.llvm.org/D50891
Reviewed By: fedor.sergeev



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346643 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-12 09:29:58 +00:00
Calixte Denizet b7ec431ced [GCOV] Add options to filter files which must be instrumented.
Summary:
When making code coverage, a lot of files (like the ones coming from /usr/include) are removed when post-processing gcno/gcda so finally they doen't need to be instrumented nor to appear in gcno/gcda.
The goal of the patch is to be able to filter the files we want to instrument, there are several advantages to do that:
- improve speed (no overhead due to instrumentation on files we don't care)
- reduce gcno/gcda size
- it gives the possibility to easily instrument only few files (e.g. ones modified in a patch) without changing the build system
- need to accept this patch to be enabled in clang: https://reviews.llvm.org/D52034

Reviewers: marco-c, vsk

Reviewed By: marco-c

Subscribers: llvm-commits, sylvestre.ledru

Differential Revision: https://reviews.llvm.org/D52033

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346641 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-12 09:01:43 +00:00
Jonas Paulsson 79d60f6e81 [SystemZ] Replicate the load with most uses in buildVector()
Iterate over all elements and count the number of uses among them for each
used load. Then make sure to REPLICATE the load which has the most uses in
order to minimize the number of needed element insertions.

Review: Ulrich Weigand
https://reviews.llvm.org/D54322

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346637 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-12 08:12:20 +00:00
Philip Reames 0165418d9a [GC] Remove unused configuration variable
The custom root mechanism didn't actually do anything.  ShadowStackGC, the only one which used it, just removed the gcroots before they reached the normal lowering in SelectionDAG.  As a result, the state flag had no value.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346632 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-12 02:34:54 +00:00
Philip Reames 78a558a8b0 [GC] Minor style modernization
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346631 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-12 02:26:26 +00:00
Philip Reames 4708fedcc2 [GCRoot] Remove some unneccessary complexity
The GCStrategy provides three configuration options were are largely redundant.

1) Support for conditionally lowering gcread and gcwrite to loads and stores.  This is redundant since any GC which wished to use these abstractions would lower them out of existance before the built in lowering anyways.  As such, there's no need to have the lowering being conditional.
2) Conditional initialization for allocas marked via gcroot.  Semantically, roots have to be initialized before first potential use.  Arguably, the frontend really should have responsibility for that, but the old API allowed the frontend to ignore this detail.  Only one builtin GC used the non-initializing mode.  Since no one to my knowledge actually uses the ErlangGC strategy, I decide the slight pessimization was worth the simplicity.  If that turns out to be problematic, we can always improve the insertion algorithm to detect more existing initializing stores.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346621 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-11 21:13:09 +00:00
Florian Hahn d3caae0ce2 [IPSCCP,PM] Preserve PDT in the new pass manager.
Reviewers: kuhar, chandlerc, NutshellySima, brzycki

Reviewed By: NutshellySima, brzycki

Differential Revision: https://reviews.llvm.org/D54317



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346618 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-11 20:22:45 +00:00
Fangrui Song b87342a824 [DWARF] Change pubnames to use DWARFSection instead of StringRef
Summary: The debug_info_offset values in .debug_{,gnu_}pub{name,types} may be relocated. Change it to DWARFSection so that we can get relocated values.

Reviewers: ruiu, dblaikie, grimar, JDevlieghere

Reviewed By: JDevlieghere

Subscribers: aprantl, JDevlieghere, llvm-commits

Differential Revision: https://reviews.llvm.org/D54375

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346615 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-11 18:57:28 +00:00
Nico Weber ac4b70f746 Make initializeOutputStream() return false on error and true on success.
As discussed in https://reviews.llvm.org/D52104

Differential Revision: https://reviews.llvm.org/D52143


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346606 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-11 10:04:00 +00:00
Craig Topper abb65ffd37 [X86] Use DAG.getConstant instead of getZeroVector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346605 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-11 07:24:36 +00:00
Jonas Devlieghere 686dfe3676 [Support] Make error banner optional in logAllUnhandledErrors
In a lot of places an empty string was passed as the ErrorBanner to
logAllUnhandledErrors. This patch makes that argument optional to
simplify the call sites.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346604 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-11 01:46:03 +00:00
Craig Topper 3283290275 [X86] Replace calls to getOnesVector/getZeroVector with getConstant.
getConstant will create a BUILD_VECTOR for us and use a legal type if necessary. So just create the simple node and let BUILD_VECTOR legalization do the canonicalization.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346603 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-11 01:40:04 +00:00
Craig Topper d30e1011b8 [DAGCombiner] Make tryToFoldExtendOfConstant return an SDValue instead of an SDNode*. NFC
Removes the need to call getNode internally and to recreate an SDValue after the call.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346600 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-10 23:46:03 +00:00
Sanjay Patel 7c38906dea [InstCombine] simplify code for merging stores; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346596 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-10 20:29:25 +00:00
Sanjay Patel f7b5c13b03 [x86] allow vector load narrowing with multi-use values
This is a long-awaited follow-up suggested in D33578. Since then, we've picked up even more
opportunities for vector narrowing from changes like D53784, so there are a lot of test diffs.
Apart from 2-3 strange cases, these are all wins.

I've structured this to be no-functional-change-intended for any target except for x86
because I couldn't tell if AArch64, ARM, and AMDGPU would improve or not. All of those
targets have existing regression tests (4, 4, 10 files respectively) that would be
affected. Also, Hexagon overrides the shouldReduceLoadWidth() hook, but doesn't show
any regression test diffs. The trade-off is deciding if an extra vector load is better
than a single wide load + extract_subvector.

For x86, this is almost always better (on paper at least) because we often can fold
loads into subsequent ops and not increase the official instruction count. There's also
some unknown -- but potentially large -- benefit from using narrower vector ops if wide
ops are implemented with multiple uops and/or frequency throttling is avoided.

Differential Revision: https://reviews.llvm.org/D54073



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346595 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-10 20:05:31 +00:00
Benjamin Kramer 6f0ce7928e [X86] Remove unused variable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346592 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-10 18:11:11 +00:00
Craig Topper 4ad252ba0c [X86] Remove apparently unneeded code from combineVSZext.
No lit tests fail with this code removed.

This is a pre-commit for D54346.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346590 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-10 17:44:28 +00:00
Simon Pilgrim acd225a655 [CostModel][X86] SK_ExtractSubvector costs must only be tested for vector types (PR39615)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346589 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-10 17:37:52 +00:00
Philip Reames 2f9bd23c20 [GC] Rename a header for consistency
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346588 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-10 16:08:10 +00:00
Roman Lebedev 94d44f1161 [X86][BdVer2] Fix loads/stores throughput for Piledriver (PR39465)
There are two AGU units, and per 1cy, there can be either two loads,
or a load and a store; but not two stores, or two loads and a store.

Additionally, loads shouldn't affect the store scheduler and vice versa.
(but *should* affect the PdEX scheduler.)

Required rL346545.
Fixes https://bugs.llvm.org/show_bug.cgi?id=39465

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346587 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-10 14:31:43 +00:00
Eugene Leviant 10c84a8f35 [ThinLTO] Internalize readonly globals
This patch allows internalising globals if all accesses to them
(from live functions) are from non-volatile load instructions

Differential revision: https://reviews.llvm.org/D49362


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346584 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-10 08:31:21 +00:00
Craig Topper 01568d51f0 [X86] Use a MOVSX instruction instead of a MOVZX instruction in isel for an any_extend of the remainder from an 8-bit sdivrem.
The sdivrem will emit its own MOVSX to move %ah to the low byte of a register. By using a MOVSX for an any_extend this allows a post-isel peephole to merge them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346581 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-10 06:04:33 +00:00
David Carlier 8614602e2f Fix DragonFlyBSD build
Reviewers: rnk, thakis

Reviewed By: krytarowski

Differential Revision: https://reviews.llvm.org/D54363


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346577 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-10 01:01:03 +00:00
Matthias Braun 3816d00971 RegAllocFast: Further cleanups; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346576 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-10 00:36:27 +00:00
Craig Topper bc177f5fc7 [X86] In LowerHorizontalByteSum, emit vector_shuffle nodes instead of directly using X86ISD::UNPCKL/X86ISD::UNPCKH.
This gives shuffle lowering the freedom to use zero_extend_vector_inreg for the unpckl shuffle. Shuffle combining usually makes this swap later, but not when AVX512 is enabled it seems.

While there also use DAG.getConstant to create a 0 vector instead of using the helper the forces a specific BUILD_VECTOR. I don't think that helper is usually needed. We're basically free to create a constant build_vector anytime and it will be legalized on its own.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346574 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-10 00:26:42 +00:00
Thomas Lively e0f010c2e2 [WebAssembly] Update bleeding-edge cpu features
Reviewers: aheejin, dschuff

Subscribers: sbc100, jgravelle-google, sunfish, jfb, llvm-commits

Differential Revision: https://reviews.llvm.org/D54362

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346570 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-10 00:11:14 +00:00
Philip Reames b92d1fef8d [GC] Simplify linking of GC builtin GC strategies
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346569 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-09 23:56:21 +00:00
Eli Friedman 25938772e8 [ARM64] [Windows] Handle funclets
This patch adds support for funclets in frame lowering and ISel
lowering. Together with D50288 and D50166, it enables C++ exception
handling.

Patch by Sanjin Sijaric, with some fixes by me.

Differential Revision: https://reviews.llvm.org/D51524



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346568 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-09 23:33:30 +00:00
Craig Topper a64afff8f4 [SelectionDAG] Fix a -Wparentheses warning from gcc in an assert. NFC
gcc wants parentheses around the logical OR since there is a logical AND for the string.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346564 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-09 23:11:30 +00:00
Eli Friedman 35ef1bd84b [ARM] Add MemOperand to LDRcp to enable DCE.
LDRcp should be deleted when the dest register is dead in register
coalescing. Without MemOp, dead LDRcp will cause dead constant pool
value which references to non-existing label.

Patch by Yin Ma.

Differential Revision: https://reviews.llvm.org/D54173



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346563 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-09 23:09:17 +00:00
Eli Friedman bd0f067b12 [JumpThreading] Fix exponential time algorithm computing known values.
ComputeValueKnownInPredecessors has a "visited" set to prevent infinite
loops, since a value can be visited more than once.  However, the
implementation didn't prevent the algorithm from taking exponential
time. Instead of removing elements from the RecursionSet one at a time,
we should keep around the whole set until
ComputeValueKnownInPredecessors finishes, then discard it.

The testcase is synthetic because I was having trouble effectively
reducing the original.  But it's basically the same idea.

Instead of failing, we could theoretically cache the result instead.
But I don't think it would help substantially in practice.

Differential Revision: https://reviews.llvm.org/D54239



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346562 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-09 22:35:26 +00:00
Craig Topper 52d7ce62d6 [X86] Move the promotion of v16i16->v16i8 for avx512f but not avx512bw from lowering to isel. Change to use vpmovzx instead of vpmovsx.
With avx512f but not avx512bw we need to extend to v16i32 then truncate that to to v16i8. Previously we emitted both nodes during lowering, but I'm trying to switch to using target independent nodes and with that switched the extend+truncate wou

This patch changes the implementation to what will be necessary with that patch which helps minimize test diffs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346552 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-09 20:09:53 +00:00
Bryan Chan 0ea548887e [AArch64] Support HiSilicon's TSV110 processor
Reviewers: t.p.northover, SjoerdMeijer, kristof.beyls

Reviewed By: kristof.beyls

Subscribers: olista01, javed.absar, kristof.beyls, kristina, llvm-commits

Differential Revision: https://reviews.llvm.org/D53908

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346546 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-09 19:32:08 +00:00
Nico Weber 86c04a0332 [MS demangler] Use a slightly shorter unmangling for mangled strings.
Before: const wchar_t * {L"%"}
Now: L"%"

See also PR39593.
Differential Revision: https://reviews.llvm.org/D54294


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346544 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-09 19:28:50 +00:00
Fangrui Song 5ac7dfd5c9 [Hexagon] Fix some -Wunused-function with LLVM_DUMP_METHOD and -Wunused-variable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346543 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-09 19:24:48 +00:00
Paul Robinson 80691e1b43 [DWARFv5] Emit normal type units in .debug_info comdats.
Differential Revision: https://reviews.llvm.org/D54282

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346540 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-09 19:06:09 +00:00
Craig Topper 9ce4cce931 [X86] Turn X86ISD::VSEXT into X86ISD::VZEXT if the upper bits aren't demanded.
This makes X86ISD::VSEXT more similar to ISD::SIGN_EXTEND and ISD::ZERO_EXTEND.

I'm hoping to replace X86ISD::VSEXT/VZEXT with target independent nodes. Making the target specific nodes similar to the target independent nodes helps minimize test diffs in that patch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346539 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-09 19:05:51 +00:00
Simon Pilgrim 5d3d354eee [CostModel][X86] SK_ExtractSubvector is free if the subvector is at the start of the source vector
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346538 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-09 19:04:27 +00:00
Jordan Rupprecht f8c45edd42 [Hexagon] Fix unused variable warning in release builds
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346537 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-09 18:54:27 +00:00
Fangrui Song 33e86fa85e [WebAssembly] Hotfix of WebAssemblyInstructionTableSize after rL346465
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346535 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-09 18:32:20 +00:00
Simon Pilgrim ec09d9119e [TTI] Flip vector types in getShuffleCost SK_ExtractSubvector call
For SK_ExtractSubvector, the default 'Ty' type is the source operand type and 'SubTy' is the destination subvector type

I got this the wrong way around when I added rL346510

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346534 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-09 18:30:59 +00:00
Brendon Cahoon c5c6cf3239 [Hexagon] Implement noreturn optimization
Eliminate the stack frame in functions with the noreturn nounwind
attributes, and when the noreturn-stack-elim target feature is
enabled. This reduces the code and stack space needed for noreturn
functions.

Differential Revision: https://reviews.llvm.org/D54210



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346532 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-09 18:16:24 +00:00
Craig Topper 6b4d662418 [DAGCombiner][X86][Mips] Enable combineShuffleOfScalars to run between vector op legalization and DAG legalization. Fix bad one use check in combineShuffleOfScalars
It's possible for vector op legalization to generate a shuffle. If that happens we should give a chance for DAG combine to combine that with a build_vector input.

I also fixed a bug in combineShuffleOfScalars that was considering the number of uses on a undef input to a shuffle. We don't care how many times undef is used.

Differential Revision: https://reviews.llvm.org/D54283

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346530 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-09 18:04:34 +00:00
Stanislav Mekhanoshin 8153acf695 [AMDGPU] Always pass TRI into findRegister[Use/Def]OperandIdx
This only covers AMDGPU BE, hopefully all occurrences.

Differential Revision: https://reviews.llvm.org/D54235

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346528 91177308-0d34-0410-b5e6-96231b3b80d8
2018-11-09 17:58:59 +00:00