8327 Commits

Author SHA1 Message Date
Nirav Dave
35f98ce715 [ScheduleDAG] Deal with already scheduled loads in ScheduleDAG.
Summary:
If we attempt to unfold an SUnit in ScheduleDAG that results in
finding an already scheduled load, we must should abort the
unfold as it will not improve scheduling.

This fixes PR32610.

Reviewers: jmolloy, sunfish, bogner, spatel

Subscribers: llvm-commits, MatzeB

Differential Revision: https://reviews.llvm.org/D32911

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304321 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-31 18:43:17 +00:00
Nirav Dave
1550dee119 [DAG] Avoid use of stale store.
Correct references to alignment of store which may be deleted in a
previous iteration of merge. Instead use first store that would be
merged.

Corrects pr33172's use-after-poison caught by ASan.

Reviewers: spatel, hfinkel, RKSimon

Reviewed By: RKSimon

Subscribers: thegameg, javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D33686

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304299 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-31 13:36:17 +00:00
Craig Topper
5e57487f27 [SelectionDAG] Remove special case for ISD::FPOWI from the strict FP intrinsic handling.
This code was compensating for FPOWI defaulting to Legal and many targets not changing it to Expand. This was fixed in r304215 to default to Expand so this special handling should no longer be necessary.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304221 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-30 17:12:18 +00:00
Craig Topper
384602a9e4 [SelectionDAG] Set ISD::FPOWI to Expand by default
Summary:
Currently FPOWI defaults to Legal and LegalizeDAG.cpp turns Legal into Expand for this opcode because Legal is a "lie".

This patch changes the default for this opcode to Expand and removes the hack from LegalizeDAG.cpp. It also removes all the code in the targets that set this opcode to Expand themselves since they can just rely on the default.

Reviewers: spatel, RKSimon, efriedma

Reviewed By: RKSimon

Subscribers: jfb, dschuff, sbc100, jgravelle-google, nemanjai, javed.absar, andrew.w.kaylor, llvm-commits

Differential Revision: https://reviews.llvm.org/D33530

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304215 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-30 15:27:55 +00:00
Sanjay Patel
cf2a64aaaf [DAGCombiner] fix load narrowing transform to exclude loads with extension
The extending load possibility was missed in:
https://reviews.llvm.org/rL304072

We might want to handle this cases as a follow-up, but bailing out for now
to avoid miscompiling.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304153 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-29 13:24:58 +00:00
Sanjay Patel
8cbe21fcdd [DAGCombiner] use narrow load to avoid vector extract
If we have (extract_subvector(load wide vector)) with no other users, 
that can just be (load narrow vector). This is intentionally conservative.
Follow-ups may loosen the one-use constraint to account for the extract cost
or just remove the one-use check.

The memop chain updating is based on code that already exists multiple times
in x86 lowering, so that should be pulled into a helper function as a follow-up.

Background: this is a potential improvement noticed via regressions caused by
making x86's peekThroughBitcasts() not loop on consecutive bitcasts (see 
comments in D33137).

Differential Revision: https://reviews.llvm.org/D33578


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304072 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-27 14:07:03 +00:00
Benjamin Kramer
a0f27f968e Make helper functions static. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304029 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-26 20:09:00 +00:00
Sanjay Patel
8f61a6eb1f [DAGCombiner] use narrow vector ops to eliminate concat/extract (PR32790)
In the best case:
extract (binop (concat X1, X2), (concat Y1, Y2)), N --> binop XN, YN
...we kill all of the extract/concat and just have narrow binops remaining.

If only one of the binop operands is amenable, this transform is still
worthwhile because we kill some of the extract/concat.

Optional bitcasting makes the code more complicated, but there doesn't
seem to be a way to avoid that.

The TODO about extending to more than bitwise logic is there because we really
will regress several x86 tests including madd, psad, and even a plain
integer-multiply-by-2 or shift-left-by-1. I don't think there's anything
fundamentally wrong with this patch that would cause those regressions; those
folds are just missing or brittle.

If we extend to more binops, I found that this patch will fire on at least one
non-x86 regression test. There's an ARM NEON test in
test/CodeGen/ARM/coalesce-subregs.ll with a pattern like:

            t5: v2f32 = vector_shuffle<0,3> t2, t4
          t6: v1i64 = bitcast t5
          t8: v1i64 = BUILD_VECTOR Constant:i64<0>
        t9: v2i64 = concat_vectors t6, t8
      t10: v4f32 = bitcast t9
    t12: v4f32 = fmul t11, t10
  t13: v2i64 = bitcast t12
t16: v1i64 = extract_subvector t13, Constant:i32<0>

There was no functional change in the codegen from this transform from what I
could see though.

For the x86 test changes:

1. PR32790() is the closest call. We don't reduce the AVX1 instruction count in that case,
   but we improve throughput. Also, on a core like Jaguar that double-pumps 256-bit ops,
   there's an unseen win because two 128-bit ops have the same cost as the wider 256-bit op.
   SSE/AVX2/AXV512 are not affected which is expected because only AVX1 has the extract/concat
   ops to match the pattern.
2. do_not_use_256bit_op() is the best case. Everyone wins by avoiding the concat/extract.
   Related bug for IR filed as: https://bugs.llvm.org/show_bug.cgi?id=33026
3. The SSE diffs in vector-trunc-math.ll are just scheduling/RA, so nothing real AFAICT.
4. The AVX1 diffs in vector-tzcnt-256.ll are all the same pattern: we reduced the instruction
   count by one in each case by eliminating two insert/extract while adding one narrower logic op.

https://bugs.llvm.org/show_bug.cgi?id=32790

Differential Revision: https://reviews.llvm.org/D33137



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303997 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-26 15:33:18 +00:00
Nirav Dave
f6ed90efa1 [DAG] Move legal type checks in store merge to be checked only
on non-legal cases. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303994 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-26 14:37:27 +00:00
John Brawn
bafb2e66d8 [ARM] Fix lowering of misaligned memcpy/memset
Currently getOptimalMemOpType returns i32 for large enough sizes without
checking for alignment, leading to poor code generation when misaligned accesses
aren't permitted as we generate a word store then later split it up into byte
stores. This means we inadvertantly go over the MaxStoresPerMemcpy limit and for
memset we splat the memset value into a word then immediately split it up
again.

Fix this by leaving it up to FindOptimalMemOpLowering to figure out which type
to use, but also fix a bug there where it wasn't correctly checking if
misaligned memory accesses are allowed.

Differential Revision: https://reviews.llvm.org/D33442


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303990 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-26 13:59:12 +00:00
Andrew Kaylor
325c68628e Add constrained intrinsics for some libm-equivalent operations
Differential revision: https://reviews.llvm.org/D32319



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303922 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-25 21:31:00 +00:00
Adrian Prantl
674c13e409 Fix SelectionDAGBuilder::getDbgValue to not expect DW_OP_deref on FI vars
This fixes an oversight in r300522, which changed alloca
dbg.values to no longer emit a DW_OP_deref.

The array.ll testcase was regenerated from source.

Fixes PR33166:
https://bugs.llvm.org/show_bug.cgi?id=33166

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303897 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-25 18:54:10 +00:00
Nirav Dave
3e49889dd5 [DAG] Prevent crashes when merging constant stores with high-bit set. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303802 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-24 19:56:39 +00:00
Tim Northover
f226a627f9 Revert LLVM changes for "Sema: allow imaginary constants via GNU extension if UDL overloads not present."
The changes accidentally crept into a Clang commit I was making.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303697 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-23 21:53:11 +00:00
Tim Northover
5be8b939f0 Sema: allow imaginary constants via GNU extension if UDL overloads not present.
C++14 added user-defined literal support for complex numbers so that you can
write something like "complex<double> val = 2i". However, there is an existing
GNU extension supporting this syntax and interpreting the result as a _Complex
type.

This changes parsing so that such literals are interpreted in terms of C++14's
operators if an overload is present but otherwise falls back to the original
GNU extension.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303694 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-23 21:41:49 +00:00
Nirav Dave
666fbb4259 [DAG] Add AddressSpace parameter to canMergeStoresTo. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303673 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-23 18:53:02 +00:00
Nirav Dave
91b8ce247b [DAG] Add canMergeStoresTo predicate checks. NFCI.
Propagate canMergeStoresTo checks to missing cases in StoreMerge.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303668 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-23 18:33:09 +00:00
Craig Topper
5e9f2d0f5d [KnownBits] Use !hasConflict() in asserts in place of Zero & One == 0 or similar. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303614 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-23 07:18:37 +00:00
Nirav Dave
40b1e969f9 [DAG] Rework store merge to loop on load candidates. NFCI.
Continue to consider remaining candidate merges until all possible
merges have been considered.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303560 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-22 15:33:47 +00:00
Matthias Braun
708626d601 SimplifyLibCalls: Optimize wcslen
Refactor the strlen optimization code to work for both strlen and wcslen.

This especially helps with programs in the wild where people pass
L"string"s to const std::wstring& function parameters and the wstring
constructor gets inlined.

This also fixes a lingerind API problem/bug in getConstantStringInfo()
where zeroinitializers would always give you an empty string (without a
length) back regardless of the actual length of the initializer which
did not work well in the TrimAtNul==false causing the PR mentioned
below.

Note that the fixed getConstantStringInfo() needed fixes to SelectionDAG
memcpy lowering and may lead to some cases for out-of-bounds
zeroinitializer accesses not getting optimized anymore. So some code
with UB may produce out of bound memory reads now instead of just
producing zeros.

The refactoring "accidentally" fixes http://llvm.org/PR32124

Differential Revision: https://reviews.llvm.org/D32839

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303461 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-19 22:37:09 +00:00
Amaury Sechet
04150ba0ac [DAGCombine] (addcarry 0, 0, X) -> (ext/trunc X)
Summary:
While this makes some case better and some case worse - so it's unclear if it is a worthy combine just by itself - this is a useful canonicalisation.

As per discussion in D32756 .

Reviewers: jyknight, nemanjai, mkuper, spatel, RKSimon, zvi, bkramer

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D32916

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303441 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-19 18:20:44 +00:00
Craig Topper
ad0e6668a7 [Statistics] Add a method to atomically update a statistic that contains a maximum
Summary:
There are several places in the codebase that try to calculate a maximum value in a Statistic object. We currently do this in one of two ways:

  MaxNumFoo = std::max(MaxNumFoo, NumFoo);

or

  MaxNumFoo = (MaxNumFoo > NumFoo) ? MaxNumFoo : NumFoo;

The first version reads from MaxNumFoo one time and uncontionally rwrites to it. The second version possibly reads it twice depending on the result of the first compare.  But we have no way of knowing if the value was changed by another thread between the reads and the writes.

This patch adds a method to the Statistic object that can ensure that we only store if our value is the max and the previous max didn't change after we read it. If it changed we'll recheck if our value should still be the max or not and try again.

This spawned from an audit I'm trying to do of all places we uses the implicit conversion to unsigned on the Statistics objects. See my previous thread on llvm-dev https://groups.google.com/forum/#!topic/llvm-dev/yfvxiorKrDQ

Reviewers: dberlin, chandlerc, hfinkel, dblaikie

Reviewed By: chandlerc

Subscribers: llvm-commits, sanjoy

Differential Revision: https://reviews.llvm.org/D33301

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303318 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-18 00:51:39 +00:00
Nirav Dave
acc2c1d71d Elide stores which are overwritten without being observed.
Summary:
In SelectionDAG, when a store is immediately chained to another store
to the same address, elide the first store as it has no observable
effects. This is causes small improvements dealing with intrinsics
lowered to stores.

Test notes:

* Many testcases overwrite store addresses multiple times and needed
  minor changes, mainly making stores volatile to prevent the
  optimization from optimizing the test away.

* Many X86 test cases optimized out instructions associated with
  associated with va_start.

* Note that test_splat in CodeGen/AArch64/misched-stp.ll no longer has
  dependencies to check and can probably be removed and potentially
  replaced with another test.

Reviewers: rnk, john.brawn

Subscribers: aemerson, rengolin, qcolombet, jyknight, nemanjai, nhaehnle, javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D33206

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303198 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-16 19:43:56 +00:00
Nirav Dave
d4f4d5c5f3 [DAG] Prune deleted nodes in TokenFactor
Fix visitTokenFactor to correctly remove deleted nodes. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303181 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-16 15:49:02 +00:00
Peter Collingbourne
6ba81f2c10 IR: Give function GlobalValue::getRealLinkageName() a less misleading name: dropLLVMManglingEscape().
This function gives the wrong answer on some non-ELF platforms in some
cases. The function that does the right thing lives in Mangler.h. To try to
discourage people from using this function, give it a different name.

Differential Revision: https://reviews.llvm.org/D33162

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303134 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-16 00:39:01 +00:00
Simon Pilgrim
72a3a14d8b [SelectionDAG] Added support for EXTRACT_SUBVECTOR/CONCAT_VECTORS demandedelts in ComputeNumSignBits
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302997 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-13 22:10:58 +00:00
Simon Pilgrim
bacfc66c2e [SelectionDAG] Add VECTOR_SHUFFLE support to ComputeNumSignBits
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302993 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-13 19:57:10 +00:00
Craig Topper
a7f9de4432 [ValueTracking] Remove const_casts on several calls to computeKnownBits and ComputeSignBit. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302991 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-13 17:22:16 +00:00
Tim Shen
ac2d13ffb3 [PPC] Move the combine "a << (b % (sizeof(a) * 8)) -> (PPCshl a, b)" to the backend. NFC.
Summary:
Eli pointed out that it's unsafe to combine the shifts to ISD::SHL etc.,
because those are not defined for b > sizeof(a) * 8, even after some of
the combiners run.

However, PPCISD::SHL defines that behavior (as the instructions themselves).
Move the combination to the backend.

The tests in shift_mask.ll still pass.

Reviewers: echristo, hfinkel, efriedma, iteratee

Subscribers: nemanjai, llvm-commits

Differential Revision: https://reviews.llvm.org/D33076

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302937 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-12 19:25:37 +00:00
Craig Topper
d49344495d [KnownBits] Add bit counting methods to KnownBits struct and use them where possible
This patch adds min/max population count, leading/trailing zero/one bit counting methods.

The min methods return answers based on bits that are known without considering unknown bits. The max methods give answers taking into account the largest count that unknown bits could give.

Differential Revision: https://reviews.llvm.org/D32931

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302925 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-12 17:20:30 +00:00
Simon Pilgrim
f50e2288e0 [DAGCombine] Use SelectionDAG::getAnyExtOrTrunc helper. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302907 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-12 15:26:50 +00:00
Simon Pilgrim
36dcf131ef [DAGCombine] Use SelectionDAG::getZExtOrTrunc helper. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302897 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-12 13:22:12 +00:00
Simon Pilgrim
43d171f539 Use SDValue::getOperand() helper. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302896 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-12 13:20:24 +00:00
Vadzim Dambrouski
29165da1cd [MSP430] Generate EABI-compliant libcalls
Updates the MSP430 target to generate EABI-compatible libcall names.
As a byproduct, adjusts the hardware multiplier options available in
the MSP430 target, adds support for promotion of the ISD::MUL operation
for 8-bit integers, and correctly marks R11 as used by call instructions.

Patch by Andrew Wygle.

Differential Revision: https://reviews.llvm.org/D32676

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302820 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-11 19:56:14 +00:00
Simon Pilgrim
44303fa5c8 [DAGCombine] Use SelectionDAG::getAnyExtOrTrunc helper. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302808 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-11 16:40:44 +00:00
Simon Pilgrim
7d572e564a Strip trailing whitespace. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302784 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-11 10:03:05 +00:00
David L. Jones
538282cc5e Revert "[SDAG] Relax conditions under stores of loaded values can be merged"
This reverts r302712.

The change fails with ASAN enabled:

ERROR: AddressSanitizer: use-after-poison on address ... at ...
READ of size 2 at ... thread T0
  #0 ... in llvm::SDNode::getNumValues() const <snip>/include/llvm/CodeGen/SelectionDAGNodes.h:855:42
  #1 ... in llvm::SDNode::hasAnyUseOfValue(unsigned int) const <snip>/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:7270:3
  #2 ... in llvm::SDValue::use_empty() const <snip> include/llvm/CodeGen/SelectionDAGNodes.h:1042:17
  #3 ... in (anonymous namespace)::DAGCombiner::MergeConsecutiveStores(llvm::StoreSDNode*) <snip>/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:12944:7

Reviewers: niravd

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D33081

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302746 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-10 23:56:21 +00:00
Nirav Dave
a7aa63a594 [SDAG] Relax conditions under stores of loaded values can be merged
Summary:

Allow consecutive stores whose values come from consecutive loads to
merged in the presense of other uses of the loads. Previously this was
disallowed as in general the merged load cannot be shared with the
other uses. Merging N stores into 1 may cause as many as N redundant
loads. However in the context of caching this should have neglible
affect on memory pressure and reduce instruction count making it
almost always a win.

Fixes PR32086.

Reviewers: spatel, jyknight, andreadb, hfinkel, efriedma

Reviewed By: efriedma

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D30471

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302712 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-10 19:53:41 +00:00
Amaury Sechet
8648143a02 Small refactoring in DAGCombine. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302699 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-10 17:58:28 +00:00
Simon Pilgrim
80d9dea549 [DAGCombiner] Dropped explicit (sra 0, x) -> 0 and (sra -1, x) -> 0 folds.
These are both handled (and tested) by the earlier ComputeNumSignBits == EltSizeInBits fold.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302651 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-10 13:06:26 +00:00
Simon Pilgrim
ceb82aef81 [DAGCombiner] Add vector support to fold (shl/srl 0, x) -> 0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302641 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-10 12:34:27 +00:00
Ahmed Bougacha
d5c43cc5c9 [CodeGen] Don't require AA in SDAGISel at -O0.
Before r247167, the pass manager builder controlled which AA
implementations were used, exporting them all in the AliasAnalysis
analysis group.

Now, AAResultsWrapperPass always uses BasicAA, but still uses other AA
implementations if made available in the pass pipeline.

But regardless, SDAGISel is required at O0, and really doesn't need to
be doing fancy optimizations based on useful AA results.

Don't require AA at CodeGenOpt::None, and only use it otherwise.

This does have a functional impact (and one testcase is pessimized
because we can't reuse a load).  But I think that's desirable no matter
what.

Note that this alone doesn't result in less DT computations: TwoAddress
was previously able to reuse the DT we computed for SDAG.  That will be
fixed separately.

Differential Revision: https://reviews.llvm.org/D32766

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302611 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-10 00:39:30 +00:00
Zvi Rackover
14cb3039db DAGCombine: Combine shuffles of splat-shuffles
Summary: Reapply r299047, but this time handle correctly splat-masks with undef elements.

Reviewers: spatel, RKSimon, eli.friedman, andreadb

Reviewed By: spatel

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D31961

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302583 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 20:25:38 +00:00
Reid Kleckner
7dfa173654 Re-land "Use the frame index side table for byval and inalloca arguments"
This re-lands r302483. It was not the cause of PR32977.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302544 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 16:02:20 +00:00
Reid Kleckner
d3285d0ce4 Re-land "Don't add DBG_VALUE instructions for static allocas in dbg.declare"
This re-lands commit r302461. It was not the cause of PR32977.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302543 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 16:01:47 +00:00
Serge Pavlov
1f4a80fdc1 Add extra operand to CALLSEQ_START to keep frame part set up previously
Using arguments with attribute inalloca creates problems for verification
of machine representation. This attribute instructs the backend that the
argument is prepared in stack prior to  CALLSEQ_START..CALLSEQ_END
sequence (see http://llvm.org/docs/InAlloca.htm for details). Frame size
stored in CALLSEQ_START in this case does not count the size of this
argument. However CALLSEQ_END still keeps total frame size, as caller can
be responsible for cleanup of entire frame. So CALLSEQ_START and
CALLSEQ_END keep different frame size and the difference is treated by
MachineVerifier as stack error. Currently there is no way to distinguish
this case from actual errors.

This patch adds additional argument to CALLSEQ_START and its
target-specific counterparts to keep size of stack that is set up prior to
the call frame sequence. This argument allows MachineVerifier to calculate
actual frame size associated with frame setup instruction and correctly
process the case of inalloca arguments.

The changes made by the patch are:
- Frame setup instructions get the second mandatory argument. It
  affects all targets that use frame pseudo instructions and touched many
  files although the changes are uniform.
- Access to frame properties are implemented using special instructions
  rather than calls getOperand(N).getImm(). For X86 and ARM such
  replacement was made previously.
- Changes that reflect appearance of additional argument of frame setup
  instruction. These involve proper instruction initialization and
  methods that access instruction arguments.
- MachineVerifier retrieves frame size using method, which reports sum of
  frame parts initialized inside frame instruction pair and outside it.

The patch implements approach proposed by Quentin Colombet in
https://bugs.llvm.org/show_bug.cgi?id=27481#c1.
It fixes 9 tests failed with machine verifier enabled and listed
in PR27481.

Differential Revision: https://reviews.llvm.org/D32394


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302527 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 13:35:13 +00:00
Amara Emerson
8f1f7ce9d1 Introduce experimental generic intrinsics for horizontal vector reductions.
- This change allows targets to opt-in to using them instead of the log2
  shufflevector algorithm.
- The SLP and Loop vectorizers have the common code to do shuffle reductions
  factored out into LoopUtils, and now have a unified interface for generating
  reductions regardless of the preference of the target. LoopUtils now uses TTI
  to determine what kind of reductions the target wants to handle.
- For CodeGen, basic legalization support is added.

Differential Revision: https://reviews.llvm.org/D30086



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302514 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 10:43:25 +00:00
Reid Kleckner
5c900216f1 Revert "Don't add DBG_VALUE instructions for static allocas in dbg.declare"
This reverts commit r302461.

It appears to be causing failures compiling gtest with debug info on the
Linux sanitizer bot. I was unable to reproduce the failure locally,
however.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302504 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 01:57:44 +00:00
Reid Kleckner
3d5255af74 Revert "Use the frame index side table for byval and inalloca arguments"
This reverts r302483 and it's follow up fix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302493 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-09 01:14:39 +00:00
Reid Kleckner
8c3a49c4c1 Use the frame index side table for byval and inalloca arguments
Summary:
For inalloca functions, this is a very common code pattern:

  %argpack = type <{ i32, i32, i32 }>
  define void @f(%argpack* inalloca %args) {
  entry:
    %a = getelementptr inbounds %argpack, %argpack* %args, i32 0, i32 0
    %b = getelementptr inbounds %argpack, %argpack* %args, i32 0, i32 1
    %c = getelementptr inbounds %argpack, %argpack* %args, i32 0, i32 2
    tail call void @llvm.dbg.declare(metadata i32* %a, ... "a")
    tail call void @llvm.dbg.declare(metadata i32* %c, ... "b")
    tail call void @llvm.dbg.declare(metadata i32* %b, ... "c")

Even though these GEPs can be simplified to a constant offset from EBP
or RSP, we don't do that at -O0, and each GEP is computed into a
register. Registers used to compute argument addresses are typically
spilled and clobbered very quickly after the initial computation, so
live debug variable tracking loses information very quickly if we use
DBG_VALUE instructions.

This change moves processing of dbg.declare between argument lowering
and basic block isel, so that we can ask if an argument has a frame
index or not. If the argument lives in a register as is the case for
byval arguments on some targets, then we don't put it in the side table
and during ISel we emit DBG_VALUE instructions.

Reviewers: aprantl

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D32980

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302483 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-08 23:20:27 +00:00