30 Commits

Author SHA1 Message Date
Aakanksha Patil
67bb6a3b71 AMDGPU: Handle "uniform-work-group-size" attribute (fix for RADV)
A previous patch for "uniform-work-group-size" attribute was found to break
some RADV and possibly radeon SI tests and had to be retracted.
This patch fixes that.

Differential Revision: http://reviews.llvm.org/D58993



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355574 91177308-0d34-0410-b5e6-96231b3b80d8
2019-03-07 00:54:04 +00:00
Chandler Carruth
6b547686c5 Update the file headers across all of the LLVM projects in the monorepo
to reflect the new license.

We understand that people may be surprised that we're moving the header
entirely to discuss the new license. We checked this carefully with the
Foundation's lawyer and we believe this is the correct approach.

Essentially, all code in the project is now made available by the LLVM
project under our new license, so you will see that the license headers
include that license only. Some of our contributors have contributed
code under our old license, and accordingly, we have retained a copy of
our old license notice in the top-level files in each project and
repository.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351636 91177308-0d34-0410-b5e6-96231b3b80d8
2019-01-19 08:50:56 +00:00
Aakanksha Patil
cc31a27f1e Revert r348971: [AMDGPU] Support for "uniform-work-group-size" attribute
This patch breaks RADV (and probably RadeonSI as well)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349084 91177308-0d34-0410-b5e6-96231b3b80d8
2018-12-13 21:23:12 +00:00
Aakanksha Patil
b20ee3547f [AMDGPU] Support for "uniform-work-group-size" attribute
Updated the annotate-kernel-features pass to support the propagation of uniform-work-group attribute from the kernel to the called functions. Once this pass is run, all kernels, even the ones which initially did not have the attribute, will be able to indicate weather or not they have uniform work group size depending on the value of the attribute. 

Differential Revision: https://reviews.llvm.org/D50200



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@348971 91177308-0d34-0410-b5e6-96231b3b80d8
2018-12-12 20:49:17 +00:00
Matt Arsenault
7e212e4168 AMDGPU: Remove remnants of old address space mapping
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341165 91177308-0d34-0410-b5e6-96231b3b80d8
2018-08-31 05:49:54 +00:00
Tom Stellard
1d6fd076a3 AMDGPU: Refactor Subtarget classes
Summary:
This is a follow-up to r335942.
- Merge SISubtarget into AMDGPUSubtarget and rename to GCNSubtarget
- Rename AMDGPUCommonSubtarget to AMDGPUSubtarget
- Merge R600Subtarget::Generation and GCNSubtarget::Generation into
  AMDGPUSubtarget::Generation.

Reviewers: arsenm, jvesely

Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D49037

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336851 91177308-0d34-0410-b5e6-96231b3b80d8
2018-07-11 20:59:01 +00:00
Eugene Zelenko
046ca04445 [Analysis] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes. Also affected in files (NFC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312289 91177308-0d34-0410-b5e6-96231b3b80d8
2017-08-31 21:56:16 +00:00
Matt Arsenault
dbe42be969 AMDGPU: Annotate implicitarg.ptr usage
We need to pass something to functions for this to work.
It isn't derivable just from the kernarg segment pointer
because the implicit arguments are placed after the
kernel arguments.

Also fixes missing test for the intrinsic.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@309398 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-28 15:52:08 +00:00
Matt Arsenault
5472b31175 AMDGPU: Annotate necessity of flat-scratch-init
As an approximation of the existing handling to avoid
regressions. Fixes using too many registers with calls
on subtargets with the SGPR allocation bug.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308326 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-18 16:44:58 +00:00
Matt Arsenault
bcb8abee35 AMDGPU: Annotate features from x work item/group IDs.
This wasn't necessary before since they are always enabled
for kernels, but this is necessary if they need to be
forwarded to a callable function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308226 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-17 22:35:50 +00:00
Davide Italiano
33778b7f13 [AMDGPU] Throw away more dead code. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308055 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-14 21:20:29 +00:00
Davide Italiano
9994117767 [AMDGPU] Garbage collect dead code. NFCI.
Unbreaks the build with GCC7.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308047 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-14 18:47:29 +00:00
Matt Arsenault
f9915c27c2 AMDGPU: Detect kernarg segment pointer
This is necessary to pass the kernarg segment pointer
to callee functions. Also don't unconditionally enable
for kernels.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307978 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-14 00:11:13 +00:00
Matt Arsenault
a20c1d0cec AMDGPU: Annotate call graph with used features
Previously this wouldn't detect used features indirectly
used in callee functions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307967 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-13 21:43:42 +00:00
Francis Visoiu Mistrih
ae1c853358 [LegacyPassManager] Remove TargetMachine constructors
This provides a new way to access the TargetMachine through
TargetPassConfig, as a dependency.

The patterns replaced here are:

* Passes handling a null TargetMachine call
  `getAnalysisIfAvailable<TargetPassConfig>`.

* Passes not handling a null TargetMachine
  `addRequired<TargetPassConfig>` and call
  `getAnalysis<TargetPassConfig>`.

* MachineFunctionPasses now use MF.getTarget().

* Remove all the TargetMachine constructors.
* Remove INITIALIZE_TM_PASS.

This fixes a crash when running `llc -start-before prologepilog`.

PEI needs StackProtector, which gets constructed without a TargetMachine
by the pass manager. The StackProtector pass doesn't handle the case
where there is no TargetMachine, so it segfaults.

Related to PR30324.

Differential Revision: https://reviews.llvm.org/D33222

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303360 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-18 17:21:13 +00:00
Yaxun Liu
ab3be33d40 [AMDGPU] Get address space mapping by target triple environment
As we introduced target triple environment amdgiz and amdgizcl, the address
space values are no longer enums. We have to decide the value by target triple.

The basic idea is to use struct AMDGPUAS to represent address space values.
For address space values which are not depend on target triple, use static
const members, so that they don't occupy extra memory space and is equivalent
to a compile time constant.

Since the struct is lightweight and cheap, it can be created on the fly at
the point of usage. Or it can be added as member to a pass and created at
the beginning of the run* function.

Differential Revision: https://reviews.llvm.org/D31284


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298846 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-27 14:04:01 +00:00
Matt Arsenault
83c857cd3a AMDGPU: Merge initial gfx9 support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295554 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-18 18:29:53 +00:00
Wei Ding
c75c94d0eb AMDGPU : Add trap handler support.
Differential Revision: http://reviews.llvm.org/D26010

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294692 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-10 02:15:29 +00:00
Wei Ding
2e3d9f4dbc AMDGPU : Add trap handler support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292893 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-24 06:41:21 +00:00
Mehdi Amini
67f335d992 Use StringRef in Pass/PassManager APIs (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283004 91177308-0d34-0410-b5e6-96231b3b80d8
2016-10-01 02:56:57 +00:00
Tom Stellard
1961591989 AMDGPU/SI: Add support for triples with the mesa3d operating system
Summary:
mesa3d will use the same kernel calling convention as amdhsa, but it will
handle everything else like the default 'unknown' OS type.

Reviewers: arsenm

Subscribers: arsenm, llvm-commits, kzhuravl

Differential Revision: https://reviews.llvm.org/D22783

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281779 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 21:34:26 +00:00
Matt Arsenault
44cd439f9a AMDGPU: Prune includes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278391 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-11 19:18:50 +00:00
Matt Arsenault
30f0e3e4be AMDGPU: Add HSA dispatch id intrinsic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276437 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-22 17:01:30 +00:00
Matt Arsenault
bc1b8d5b49 AMDGPU: Fix constantexpr addrspacecasts
If we had a constant group address space cast the queue pointer
wasn't enabled for the function, resulting in a crash on noreg
later.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271935 91177308-0d34-0410-b5e6-96231b3b80d8
2016-06-06 20:03:31 +00:00
Matt Arsenault
f9fe659922 AMDGPU: Implement addrspacecast
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267452 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-25 19:27:24 +00:00
Matt Arsenault
51b6e0bf3a AMDGPU: Add queue ptr intrinsic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267451 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-25 19:27:18 +00:00
Matt Arsenault
9a30bf46a7 AMDGPU: Stop checking intrinsics not used by HSA for dispatch-ptr
Only the dispatch.ptr intrinsic is supposed to be used now to get
the workgroup size, and the read.local.size intrinsics do not
work correctly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@259296 91177308-0d34-0410-b5e6-96231b3b80d8
2016-01-30 05:10:59 +00:00
Matt Arsenault
27e98d1c21 AMDGPU: Add new amdgcn workitem intrinsics
These use the correct prefix and follow the HSA naming convention
rather than the config register option names.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@259293 91177308-0d34-0410-b5e6-96231b3b80d8
2016-01-30 04:25:19 +00:00
Tom Stellard
aa23e0330d AMDGPU: Add llvm.amdgcn.dispatch.ptr intrinsic
Summary:
This returns a pointer to the dispatch packet, which can be used to load
information about the kernel dispach.

Reviewers: arsenm

Subscribers: arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D14898

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254116 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-26 00:43:29 +00:00
Matt Arsenault
454a57ccb6 AMDGPU: Add pass to detect used kernel features
Mark kernels that use certain features that require user
SGPRs to support with kernel attributes. We need to know
before instruction selection begins because it impacts
the kernel calling convention lowering.

For now this only detects the workitem intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252323 91177308-0d34-0410-b5e6-96231b3b80d8
2015-11-06 18:01:57 +00:00