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cbb9812d0d
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317 Commits

Author SHA1 Message Date
Chris Lattner
cbb9812d0d bling bling! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16873 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-10-10 16:26:13 +00:00
Nate Begeman
bdf69847a9 Implement logical and with an immediate that consists of a contiguous block 
of one or more 1 bits (may wrap from least significant bit to most
significant bit) as the rlwinm rather than andi., andis., or some longer
instructons sequence.

int andn4(int z) { return z & -4; }
int clearhi(int z) { return z & 0x0000FFFF; }
int clearlo(int z) { return z & 0xFFFF0000; }
int clearmid(int z) { return z & 0x00FFFF00; }
int clearwrap(int z) { return z & 0xFF0000FF; }

_andn4:
        rlwinm r3, r3, 0, 0, 29
        blr

_clearhi:
        rlwinm r3, r3, 0, 16, 31
        blr

_clearlo:
        rlwinm r3, r3, 0, 0, 15
        blr

_clearmid:
        rlwinm r3, r3, 0, 8, 23
        blr

_clearwrap:
        rlwinm r3, r3, 0, 24, 7
        blr


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16832 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-10-08 02:49:24 +00:00
Nate Begeman
b816f0298d Several fixes and enhancements to the PPC32 backend. 
1. Fix an illegal argument to getClassB when deciding whether or not to
   sign extend a byte load.

2. Initial addition of isLoad and isStore flags to the instruction .td file
   for eventual use in a scheduler.

3. Rewrite of how constants are handled in emitSimpleBinaryOperation so
   that we can emit the PowerPC shifted immediate instructions far more
   often.  This allows us to emit the following code:

int foo(int x) { return x | 0x00F0000; }

_foo:
.LBB_foo_0:     ; entry
        ; IMPLICIT_DEF
        oris r3, r3, 15
        blr


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16826 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-10-07 22:30:03 +00:00
Nate Begeman
cb90de37a7 Add ori reg, reg, 0 as a move instruction. This can be generated from 
loading a 32bit constant into a register whose low halfword is all zeroes.

We now omit the ori after the lis for the following C code:

int bar(int y) { return y * 0x00F0000; }

_bar:
.LBB_bar_0:     ; entry
        ; IMPLICIT_DEF
        lis r2, 15
        mullw r3, r3, r2
        blr


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16825 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-10-07 22:26:12 +00:00
Nate Begeman
5a181c848b Remove unnecessary header include 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16824 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-10-07 22:24:32 +00:00
Chris Lattner
7c348e1c9f Correct some typeos 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16770 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-10-06 16:28:24 +00:00
Nate Begeman
35b020df39 Turning on fsel code gen now that we can do so would be good. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16765 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-10-06 11:03:30 +00:00
Nate Begeman
087d5d92f1 Implement floating point select for lt, gt, le, ge using the powerpc fsel 
instruction.

Now, rather than emitting the following loop out of bisect:
.LBB_main_19:	; no_exit.0.i
	rlwinm r3, r2, 3, 0, 28
	lfdx f1, r3, r27
	addis r3, r30, ha16(.CPI_main_1-"L00000$pb")
	lfd f2, lo16(.CPI_main_1-"L00000$pb")(r3)
	fsub f2, f2, f1
	addis r3, r30, ha16(.CPI_main_1-"L00000$pb")
	lfd f4, lo16(.CPI_main_1-"L00000$pb")(r3)
	fcmpu cr0, f1, f4
	bge .LBB_main_64	; no_exit.0.i
.LBB_main_63:	; no_exit.0.i
	b .LBB_main_65	; no_exit.0.i
.LBB_main_64:	; no_exit.0.i
	fmr f2, f1
.LBB_main_65:	; no_exit.0.i
	addi r3, r2, 1
	rlwinm r3, r3, 3, 0, 28
	lfdx f1, r3, r27
	addis r3, r30, ha16(.CPI_main_1-"L00000$pb")
	lfd f4, lo16(.CPI_main_1-"L00000$pb")(r3)
	fsub f4, f4, f1
	addis r3, r30, ha16(.CPI_main_1-"L00000$pb")
	lfd f5, lo16(.CPI_main_1-"L00000$pb")(r3)
	fcmpu cr0, f1, f5
	bge .LBB_main_67	; no_exit.0.i
.LBB_main_66:	; no_exit.0.i
	b .LBB_main_68	; no_exit.0.i
.LBB_main_67:	; no_exit.0.i
	fmr f4, f1
.LBB_main_68:	; no_exit.0.i
	fadd f1, f2, f4
	addis r3, r30, ha16(.CPI_main_2-"L00000$pb")
	lfd f2, lo16(.CPI_main_2-"L00000$pb")(r3)
	fmul f1, f1, f2
	rlwinm r3, r2, 3, 0, 28
	lfdx f2, r3, r28
	fadd f4, f2, f1
	fcmpu cr0, f4, f0
	bgt .LBB_main_70	; no_exit.0.i
.LBB_main_69:	; no_exit.0.i
	b .LBB_main_71	; no_exit.0.i
.LBB_main_70:	; no_exit.0.i
	fmr f0, f4
.LBB_main_71:	; no_exit.0.i
	fsub f1, f2, f1
	addi r2, r2, -1
	fcmpu cr0, f1, f3
	blt .LBB_main_73	; no_exit.0.i
.LBB_main_72:	; no_exit.0.i
	b .LBB_main_74	; no_exit.0.i
.LBB_main_73:	; no_exit.0.i
	fmr f3, f1
.LBB_main_74:	; no_exit.0.i
	cmpwi cr0, r2, -1
	fmr f16, f0
	fmr f17, f3
	bgt .LBB_main_19	; no_exit.0.i

We emit this instead:
.LBB_main_19:	; no_exit.0.i
	rlwinm r3, r2, 3, 0, 28
	lfdx f1, r3, r27
	addis r3, r30, ha16(.CPI_main_1-"L00000$pb")
	lfd f2, lo16(.CPI_main_1-"L00000$pb")(r3)
	fsub f2, f2, f1
	fsel f1, f1, f1, f2
	addi r3, r2, 1
	rlwinm r3, r3, 3, 0, 28
	lfdx f2, r3, r27
	addis r3, r30, ha16(.CPI_main_1-"L00000$pb")
	lfd f4, lo16(.CPI_main_1-"L00000$pb")(r3)
	fsub f4, f4, f2
	fsel f2, f2, f2, f4
	fadd f1, f1, f2
	addis r3, r30, ha16(.CPI_main_2-"L00000$pb")
	lfd f2, lo16(.CPI_main_2-"L00000$pb")(r3)
	fmul f1, f1, f2
	rlwinm r3, r2, 3, 0, 28
	lfdx f2, r3, r28
	fadd f4, f2, f1
	fsub f5, f0, f4
	fsel f0, f5, f0, f4
	fsub f1, f2, f1
	addi r2, r2, -1
	fsub f2, f1, f3
	fsel f3, f2, f3, f1
	cmpwi cr0, r2, -1
	fmr f16, f0
	fmr f17, f3
	bgt .LBB_main_19	; no_exit.0.i


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16764 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-10-06 09:53:04 +00:00
Nate Begeman
1f49e868aa Generate better code by being far less clever when it comes to the select instruction. Don't create overlapping register lifetimes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16580 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-09-29 05:00:31 +00:00
Nate Begeman
1b99fd3e8a improve Type::BoolTy codegen by eliminating unnecessary clears and sign extends 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16578 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-09-29 03:45:33 +00:00
Nate Begeman
a41fc77ae4 To go along with sabre's improved InstCombining, improve recognition of 
integers that we can use as immediate values in instructions.

Example from yacr2:
-       lis r10, -1
-       ori r10, r10, 65535
-       add r28, r28, r10
+       addi r28, r28, -1
        addi r7, r7, 1
        addi r9, r9, 1
        b .LBB_main_9   ; loopentry.1.i214


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16566 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-09-29 02:35:05 +00:00
Nate Begeman
da721e74f8 Correct some BuildMI arguments for the upcoming simple scheduler 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16519 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-09-27 05:08:17 +00:00
Nate Begeman
645495d2e6 Fix the last of the major PPC GEP folding deficiencies. This will allow 
the ISel to use indexed and non-zero immediate offsets for GEPs that have
more than one use.  This is common for instruction sequences such as a load
followed by a modify and store to the same address.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16493 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-09-23 05:31:33 +00:00
Nate Begeman
a2de102a5b add optimized code sequences for setcc x, 0 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16478 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-09-22 04:40:25 +00:00
Misha Brukman
540c82a700 s/ISel/PPC64ISel/ to have unique class names for debugging via gdb because the 
C++ front-end in gcc does not mangle classes in anonymous namespaces correctly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16471 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-09-21 18:22:33 +00:00
Misha Brukman
a1dca55a3a s/ISel/PPC32ISel/ to have unique class names for debugging via gdb because the 
C++ front-end in gcc does not mangle classes in anonymous namespaces correctly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16470 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-09-21 18:22:19 +00:00
Chris Lattner
b228657acc Revamp the Register class, and allow the use of the RegisterGroup class to 
specify aliases directly in register definitions.

Patch contributed by Jason Eckhardt!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16330 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-09-14 04:17:02 +00:00
Nate Begeman
20136a21ba Add 64 bit divide instructions, and use them 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16198 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-09-06 18:46:59 +00:00
Misha Brukman
3e0b51ab3b * Change PPC32AsmPrinter => PowerPCAsmPrinter since it is now shared between 
Darwin and AIX and is not 32- or 64-bit specific
* Bring back PowerPC.td as a result, to make it use the `PowerPC' class name
* Adjust Makefile accordingly


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16174 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-09-05 02:42:44 +00:00
Misha Brukman
b986b7de50 Renamed PPC32AsmPrinter.cpp => PowerPCAsmPrinter.cpp as the Darwin and AIX asm 
printers are now unified into one file.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16173 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-09-05 02:27:37 +00:00
Nate Begeman
a11c2e8fb9 Include MathExtras.h to fix build breakage, thanks to Vladimir 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16164 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-09-04 14:51:26 +00:00
Nate Begeman
ed42853be1 All PPC instructions are now auto-printed 
32 and 64 bit AsmWriters unified
Darwin and AIX specific features of AsmWriter split out


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16163 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-09-04 05:00:00 +00:00
Nate Begeman
b7a8f2cdaa Convert remaining X-Form and Pseudo instructions over to asm writer 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16142 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-09-02 08:13:00 +00:00
Reid Spencer
551ccae044 Changes For Bug 352 
Move include/Config and include/Support into include/llvm/Config,
include/llvm/ADT and include/llvm/Support. From here on out, all LLVM
public header files must be under include/llvm/.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16137 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-09-01 22:55:40 +00:00
Nate Begeman
cc8bd9ca7c convert M and MD form instructions to generated asm writer 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16121 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-31 02:28:08 +00:00
Nate Begeman
07aada8b0f Move yet more instructions over to being printed by the generated asm writer 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16112 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-30 02:28:06 +00:00
Nate Begeman
6b3dc55ef8 Convert A-Form instructions to auto-generated asm writer 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16107 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-29 22:45:13 +00:00
Nate Begeman
d332fd54f5 Improvements to int->float cast code for PPC-64 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16105 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-29 22:02:43 +00:00
Nate Begeman
f2f0781a10 Implement the following missing functionality in the PPC backend: 
cast fp->bool
cast ulong->fp
algebraic right shift long by non-constant value
These changes tested across most of the test suite.  Fixes Regression/casts


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16081 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-29 08:19:32 +00:00
Nate Begeman
5709998993 Register sizes are in bits, not bytes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16070 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-27 04:28:10 +00:00
Nate Begeman
0e5e5f56bd Kill a majority of unnecessary sign extensions for byte loads 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15991 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-22 08:10:15 +00:00
Nate Begeman
1f4a132599 Don't hard code the offset of the saved R31 in functions with frame pointers 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15990 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-22 08:09:17 +00:00
Nate Begeman
a96c4af7f1 Back out branchless SetCC code. While it helped a lot in some cases, it 
hurt a lot in others.  Instead, improve branching version of SetCC and
Select instructions.  The old code will be in CVS should we ever need to
dig it up again.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15979 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-21 20:42:14 +00:00
Chris Lattner
608034ec1a Switch from bytes to bits for alignment. 
Also, change GPRC for PPC32 to align on 32-bit boundary instead of 64-bit


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15975 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-21 20:14:40 +00:00
Chris Lattner
8edcd84653 Reduce uses of getRegClass 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15968 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-21 19:51:17 +00:00
Chris Lattner
12585baf1a Fix warning 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15964 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-21 19:11:03 +00:00
Nate Begeman
c3306120cc Move XForm instructions over to the auto-generated asm writer 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15962 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-21 05:56:39 +00:00
Nate Begeman
b65eadb7f5 remove some things from the todo list. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15956 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-20 18:46:54 +00:00
Chris Lattner
f908888553 Do not register ppc64 yet, as it breaks the SparcV9 backend 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15955 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-20 18:09:18 +00:00
Nate Begeman
b47321ba2b Implement code to convert SetCC into straight line code where appropriate. Add necessary instructions for this transformation to the .td file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15952 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-20 09:56:22 +00:00
Misha Brukman
43f20a56b2 Fix opcodes being printed in caps (the more general fix may be `AsmWriter') 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15932 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-19 21:56:12 +00:00
Misha Brukman
1601d9c1f0 Stack space for argument passing is 32 regardless of 32- vs. 64-bit arch. 
Thanks to Nate Begeman for pointing this out.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15930 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-19 21:51:19 +00:00
Misha Brukman
983e92dc0d LR needs to be saved at 16-byte offset on a 64-bit arch 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15929 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-19 21:36:14 +00:00
Misha Brukman
4debafbea4 On 64-bit PowerPC, pointers are 8 bytes, so parameter area offset is 48, not 24 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15928 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-19 21:34:05 +00:00
Misha Brukman
d2cbb871d0 This PHI has 4 additional operands, not 2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15926 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-19 21:00:12 +00:00
Misha Brukman
95ab78af3c Use the appropriate 64-bit register description file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15922 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-19 19:36:57 +00:00
Misha Brukman
5e9867e71c Fix more remaining 32-bit vestiges of PowerPC 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15919 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-19 18:49:58 +00:00
Misha Brukman
cc55ad5fe9 Fix another vestige of the 32-bit PowerPC backend. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15918 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-19 16:50:30 +00:00
Misha Brukman
ab566eaa68 Correct character prepended to global symbols ('.'), use Mangler consistently 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15917 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-19 16:33:56 +00:00
Misha Brukman
1c514ec89d * Eliminate global base register, r2 is used for that on AIX/PowerPC 
* Fix bug from 32-bit PowerPC days of 2-register long split


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15916 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-19 16:29:25 +00:00