Commit Graph

45004 Commits

Author SHA1 Message Date
Wei Mi
d6cdc20e21 Revert rL303923 since it broke the sanitizer bootstrap build bot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303969 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-26 05:42:50 +00:00
Matthias Braun
55d0a522c4 Revert "LivePhysRegs: Fix addLiveOutsNoPristines() for return blocks past PEI"
Tentatively revert this to see if it fixes the buildbot stage2
breakages.

This reverts commit r303938.
This reverts commit r303954.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303960 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-26 02:25:20 +00:00
Matthias Braun
e4bd195e02 Test for r303938
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303954 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-26 01:29:25 +00:00
Chandler Carruth
88001205b7 [PM] Enable the new simple loop unswitch pass in the new pass manager
(where it is the only realistic option).

This passes the LLVM test suite for me, but I'm clearly still hammering
on this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303952 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-26 01:24:11 +00:00
Peter Collingbourne
c58f672ed1 LTO: Do summary-based prevailing symbol resolution at --lto-O0.
Prevailing symbol resolution is necessary for correctness. Without
this we can end up dropping a referenced linkonce symbol from the link.

Differential Revision: https://reviews.llvm.org/D33570

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303939 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-25 23:40:11 +00:00
Tim Shen
7a45750233 [PPC] Fix atomics lowering in DAG lowering.
I forgot to forward the chain, causing some missing instruction
dependencies. The test crashes the compiler without this patch.

Inspired by the test case, D33519 also tries to remove the extra sync.

Differential Revision: https://reviews.llvm.org/D33573

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303931 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-25 22:58:35 +00:00
David Blaikie
e55679d86d Fix test to handle running on platforms which don't enable pubnames at all
Check that there are no entries in the pub sections, but that they may
either be not present or present-but-empty.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303927 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-25 22:10:51 +00:00
Wei Mi
d163591138 [GVN] Add phi-translate support in scalarpre.
Right now scalarpre doesn't have phi-translate support, so it will miss some
simple pre opportunities. Like the following testcase, current scalarpre cannot
recognize the last "a * b" is fully redundent because a and b used by the last
"a * b" expr are both defined by phis.

  long a[100], b[100], g1, g2, g3;
  __attribute__((pure)) long goo();

  void foo(long a, long b, long c, long d) {
    g1 = a * b;
    if (__builtin_expect(g2 > 3, 0)) {
      a = c;
      b = d;
      g2 = a * b;
    }
    g3 = a * b;      // fully redundant.
  }

The patch adds phi-translate support in scalarpre. This is only a temporary
solution before the newpre based on newgvn is available.

Differential Revision: https://reviews.llvm.org/D32252


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303923 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-25 21:49:02 +00:00
Andrew Kaylor
325c68628e Add constrained intrinsics for some libm-equivalent operations
Differential revision: https://reviews.llvm.org/D32319



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303922 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-25 21:31:00 +00:00
Matthias Braun
94c4904dc5 CodeGen: Rename DEBUG_TYPE to match passnames
Rename the DEBUG_TYPE to match the names of corresponding passes where
it makes sense. Also establish the pattern of simply referencing
DEBUG_TYPE instead of repeating the passname where possible.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303921 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-25 21:26:32 +00:00
Bob Haarman
ae12b7b360 [pdb] pad source file name buffer at the end instead of the beginning
Summary:
DbiStreamBuilder calculated the offset of the source file names inside
the file info substream as the size of the file info substream minus
the size of the file names. Since the file info substream is padded to
a multiple of 4 bytes, this caused the first file name to be aligned
on a 4-byte boundary. By contrast, DbiModuleList would read the file
names immediately after the file name offset table, without skipping
to the next 4-byte boundary. This change makes it so that the file
names are written to the location where DbiModuleList expects them,
and puts any necessary padding for the file info substream after the
file names instead of before it.

Reviewers: amccarth, rnk, zturner

Reviewed By: amccarth, zturner

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D33475


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303917 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-25 21:12:15 +00:00
Sam Clegg
d4b1dbe69d [WebAssembly] MC: Include unnamed data when writing wasm files
Also, include global entries for all data symbols, not
just external ones, since these are referenced by the
relocation records.

Add a test case that includes unnamed data.

Differential Revision: https://reviews.llvm.org/D33079

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303915 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-25 21:08:07 +00:00
Nico Weber
b6e91f4292 Revert r303859, CodeGen/AMDGPU/llvm.amdgcn.s.getpc.ll fails on bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303902 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-25 19:19:29 +00:00
Manoj Gupta
abf5868389 [AArch64]: add 'a' inline asm operand modifier.
Summary:
This is used in the Linux kernel, and effectively just means "print an
address". This brings back r193593.

Reviewed by: Renato Golin

Reviewers: t.p.northover, rengolin, richard.barton.arm, kristof.beyls

Subscribers: aemerson, javed.absar, llvm-commits, eraman

Differential Revision: https://reviews.llvm.org/D33558



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303901 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-25 19:07:57 +00:00
Adrian Prantl
674c13e409 Fix SelectionDAGBuilder::getDbgValue to not expect DW_OP_deref on FI vars
This fixes an oversight in r300522, which changed alloca
dbg.values to no longer emit a DW_OP_deref.

The array.ll testcase was regenerated from source.

Fixes PR33166:
https://bugs.llvm.org/show_bug.cgi?id=33166

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303897 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-25 18:54:10 +00:00
David Blaikie
03e10d9460 DebugInfo: Produce debug_{gnu_}pub{names,types} entries when explicitly requested, even in -gmlt or when empty
Turns out gold doesn't use the DW_AT_GNU_pubnames to decide whether to
parse the rest of the DIEs when building gdb-index. This causes gold to
trip over LLVM's output when there are DW_FORM_ref_addr present.

Gold does use the presence of a debug_gnu_pub{names,types} entry for the
CU to skip parsing the debug_info portion, so make sure that's included
even when empty (technically, when empty there couldn't be any ref_addr
anyway - it only came up when gmlt didn't produce any (even non-empty)
pubnames - but given what that reveals about gold's implementation, this
seems like a good thing to do for consistency).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303894 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-25 18:50:28 +00:00
Bob Haarman
ecda7b1922 [llvm-pdbdump] [yaml2pdb] always include object file name in module info
Summary:
Previously, the yaml2pdb subcommand of llvm-pdbdump only
included object file names in module info if a module info stream was
present. This change makes it so that we include the object file name
even if there is no module info stream for the module. As a result,
running
llvm-pdbdump pdb2yaml -dbi-module-info original.pdb > original.yaml &&
llvm-pdbdump yaml2pdb -pdb=new.pdb original.yaml && llvm-pdbdump
pdb2yaml -dbi-module-info new.pdb > new.yaml now produces identical
original.yaml and new.yaml files.

Reviewers: amccarth, zturner

Reviewed By: zturner

Subscribers: fhahn, llvm-commits

Differential Revision: https://reviews.llvm.org/D33463


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303891 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-25 18:04:17 +00:00
Daniel Berlin
4133415c70 NewGVN: Fix PR 33119, PR 33129, due to regressed undef handling
Fix PR33120 and others by eliminating self-cycles a different way.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303875 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-25 15:44:20 +00:00
Artur Pilipenko
81a4c4fa69 [InstCombine] Teach isAllocSiteRemovable to look through addrspacecasts
Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D28565

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303870 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-25 15:14:48 +00:00
Sanjay Patel
6680feb0be [InstCombine] make icmp-mul fold more efficient
There's probably a lot more like this (see also comments in D33338 about responsibility), 
but I suspect we don't usually get a visible manifestation.

Given the recent interest in improving InstCombine efficiency, another potential micro-opt
that could be repeated several times in this function: morph the existing icmp pred/operands
instead of creating a new instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303860 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-25 14:13:57 +00:00
Tim Corringham
b88c01b1f7 [AMDGPU] add intrinsic for s_getpc
Summary: The s_getpc instruction is exposed as intrinsic llvm.amdgcn.s.getpc.

Reviewers: arsenm

Reviewed By: arsenm

Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye

Differential Revision: https://reviews.llvm.org/D32862

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303859 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-25 14:04:14 +00:00
Oren Ben Simhon
f3cb5d6f7f [X86] Adding vpopcntd and vpopcntq instructions
AVX512_VPOPCNTDQ is a new feature set that was published by Intel.
The patch represents the LLVM side of the addition of two new intrinsic based instructions (vpopcntd and vpopcntq).

Differential Revision: https://reviews.llvm.org/D33169



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303858 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-25 13:45:23 +00:00
James Molloy
9693a6db68 [GVNSink] GVNSink pass
This patch provides an initial prototype for a pass that sinks instructions based on GVN information, similar to GVNHoist. It is not yet ready for commiting but I've uploaded it to gather some initial thoughts.

This pass attempts to sink instructions into successors, reducing static
instruction count and enabling if-conversion.
We use a variant of global value numbering to decide what can be sunk.
Consider:

[ %a1 = add i32 %b, 1  ]   [ %c1 = add i32 %d, 1  ]
[ %a2 = xor i32 %a1, 1 ]   [ %c2 = xor i32 %c1, 1 ]
                 \           /
           [ %e = phi i32 %a2, %c2 ]
           [ add i32 %e, 4         ]

GVN would number %a1 and %c1 differently because they compute different
results - the VN of an instruction is a function of its opcode and the
transitive closure of its operands. This is the key property for hoisting
and CSE.

What we want when sinking however is for a numbering that is a function of
the *uses* of an instruction, which allows us to answer the question "if I
replace %a1 with %c1, will it contribute in an equivalent way to all
successive instructions?". The (new) PostValueTable class in GVN provides this
mapping.

This pass has some shown really impressive improvements especially for codesize already on internal benchmarks, so I have high hopes it can replace all the sinking logic in SimplifyCFG.

Differential revision: https://reviews.llvm.org/D24805

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303850 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-25 12:51:11 +00:00
Chandler Carruth
4fde77f8f1 [PM] Teach the PGO instrumentation pasess to run GlobalDCE before
instrumenting code.

This is important in the new pass manager. The old pass manager's
inliner has a small DCE routine embedded within it. The new pass manager
relies on the actual GlobalDCE pass for this.

Without this patch, instrumentation profiling with the new PM results in
massive code bloat in the object files because the instrumentation
itself ends up preventing DCE from working to remove the code.

We should probably change the instrumentation (and/or DCE) so that we
can eliminate dead code even if instrumented, but we shouldn't even
spend the time generating instrumentation for that code so this still
seems like a good patch.

Differential Revision: https://reviews.llvm.org/D33535

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303845 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-25 07:15:09 +00:00
Chandler Carruth
2dcd120478 [PM/Unswitch] Fix a bug in the domtree update logic for the new unswitch
pass.

The original logic only considered direct successors of the hoisted
domtree nodes, but that isn't really enough. If there are other basic
blocks that are completely within the subtree, their successors could
just as easily be impacted by the hoisting.

The more I think about it, the more I think the correct update here is
to hoist every block on the dominance frontier which has an idom in the
chain we hoist across. However, this is subtle enough that I'd
definitely appreciate some more eyes on it.

Sadly, if this is the correct algorithm, it requires computing a (highly
localized) dominance frontier. I've done this in the simplest (IE, least
code) way I could come up with, but that may be too naive. Suggestions
welcome here, dominance update algorithms are not an area I've studied
much, so I don't have strong opinions.

In good news, with this patch, turning on simple unswitch passes the
LLVM test suite for me with asserts enabled.

Differential Revision: https://reviews.llvm.org/D32740

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303843 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-25 06:33:36 +00:00
George Karpenkov
f6cb509385 Fix coverage check for full post-dominator basic blocks.
Coverage instrumentation which does not instrument full post-dominators
and full-dominators may skip valid paths, as the reasoning for skipping
blocks may become circular.
This patch fixes that, by only skipping
full post-dominators with multiple predecessors, as such predecessors by
definition can not be full-dominators.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303827 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-25 01:41:46 +00:00
Gor Nishanov
5d2828c385 [coroutines] Relocate instructions that maybe spilled after coro.begin
Summary:
Frontend generates store instructions after allocas, for example:

```
define i8* @f(i64 %this) "coroutine.presplit"="1" personality i32 0 {
entry:
  %this.addr = alloca i64
  store i64 %this, i64* %this.addr
  ..
  %hdl = call i8* @llvm.coro.begin(token %id, i8* %alloc)

```
Such instructions may require spilling into coro.frame, but, coro-frame address is only available after coro.begin and thus needs to be moved after coro.begin.
The only instructions that should not be moved are the arguments of coro.begin and all of their operands.

Reviewers: GorNishanov, majnemer

Reviewed By: GorNishanov

Subscribers: llvm-commits, EricWF

Differential Revision: https://reviews.llvm.org/D33527

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303825 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-25 00:46:20 +00:00
Tony Jiang
133fa95ca7 [PowerPC] Fix a performance bug for PPC::XXSLDWI.
There are some VectorShuffle Nodes in SDAG which can be selected to XXSLDWI
instruction, this patch recognizes them and does the selection to improve the
PPC performance.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303822 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-24 23:48:29 +00:00
Rafael Espindola
89995adbed Print symbols from COFF import libraries.
This change allows llvm-nm to print symbols found in import libraries,
in part by allowing COFFImportFiles to be casted to SymbolicFiles.

Patch by Dave Lee!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303821 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-24 23:40:36 +00:00
Gor Nishanov
1c3064b7b3 [coroutines] Allow rematerialization upto 4 times. Remove incorrect assert
Reviewers: majnemer

Subscribers: EricWF, llvm-commits

Differential Revision: https://reviews.llvm.org/D33524

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303819 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-24 23:01:02 +00:00
Sanjay Patel
d47a423c5e [InstCombine] use m_APInt to allow icmp-mul-mul vector fold
The swapped operands in the first test is a manifestation of an 
inefficiency for vectors that doesn't exist for scalars because 
the IRBuilder checks for an all-ones mask for scalars, but not 
vectors.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303818 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-24 22:58:17 +00:00
Sanjay Patel
7941a52006 [InstCombine] add tests for icmp eq (mul X, C), (mul Y, C); NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303816 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-24 22:36:14 +00:00
Sanjay Patel
f717c76e13 [InstCombine] move tests and use FileCheck; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303808 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-24 21:48:25 +00:00
Teresa Johnson
4c833e2dc2 Fix a couple of typos in memory intrinsic optimization output (NFC)
s/instrinsic/intrinsic

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303782 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-24 17:55:25 +00:00
Zaara Syeda
8abe596788 P9: D-form vector load/store. Differential Revision: https://reviews.llvm.org/D33248
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303780 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-24 17:50:37 +00:00
Krzysztof Parzyszek
a1adbd39e9 Move machine-cse-physreg.mir to test/CodeGen/Thumb
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303778 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-24 17:20:47 +00:00
Craig Topper
f9152c247d [InstSimplify] Simplify uadd/sadd/umul/smul with overflow intrinsics when the Zero or Undef is on the LHS.
Summary: This code was migrated from InstCombine a few years ago. InstCombine had nearby code that would move Constants to the RHS for these, but InstSimplify doesn't have such code on this path.

Reviewers: spatel, majnemer, davide

Reviewed By: spatel

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D33473

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303774 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-24 17:05:28 +00:00
Matthew Simpson
59a0e24a58 Revert r291254: [AArch64] Reduce vector insert/extract cost for Falkor
The default vector insert/extract cost is more profitable on Falkor than the
reduced cost.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303771 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-24 16:48:39 +00:00
Matthew Simpson
9e8c6339d7 [LV] Update type in cost model for scalarization
For non-uniform instructions marked for scalarization, we should update
`VectorTy` when computing instruction costs to reflect the scalar type. In
addition to determining instruction costs, this type is also used to signal
that all instructions in the loop will be scalarized. This currently affects
memory instructions and non-pointer induction variables and their updates. (We
also mark GEPs scalar after vectorization, but their cost is computed together
with memory instructions.) For scalarized induction updates, this patch also
scales the scalar cost by the vectorization factor, corresponding to each
induction step.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303763 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-24 15:26:15 +00:00
Vadzim Dambrouski
6f94f45297 [MSP430] Fix PR33050: Don't use ADD16ri to lower FrameIndex.
Use ADDframe pseudo instruction instead.
This will fix machine verifier error, and will help to fix PR32146.

Differential Revision: https://reviews.llvm.org/D33452

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303758 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-24 15:08:30 +00:00
Sanjay Patel
577a993423 [InstCombine] add tests to show potential missing folds; NFC
As noted in https://bugs.llvm.org/show_bug.cgi?id=33138 and
the comments, there are multiple ways to view this. If we
choose not to solve this in InstCombine, these tests will
serve as documentation of that choice.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303755 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-24 14:56:51 +00:00
Sanjay Patel
852ab094ff [InstCombine] add tests to document bitcast + bitwise-logic behavior; NFC
The solution for PR26702 ( https://bugs.llvm.org/show_bug.cgi?id=26702 )
added a canonicalization rule, but the minimal regression tests don't 
demonstrate how that rule interacts with other folds.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303750 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-24 14:21:31 +00:00
Diana Picus
70301d661a Revert "[SCEV] Do not fold dominated SCEVUnknown into AddRecExpr start"
This reverts commit r303730 because it broke all the buildbots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303747 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-24 14:16:04 +00:00
Jonas Paulsson
a551a28baa [LoopVectorizer] Let target prefer scalar addressing computations.
The loop vectorizer usually vectorizes any instruction it can and then
extracts the elements for a scalarized use. On SystemZ, all elements
containing addresses must be extracted into address registers (GRs). Since
this extraction is not free, it is better to have the address in a suitable
register to begin with. By forcing address arithmetic instructions and loads
of addresses to be scalar after vectorization, two benefits result:

* No need to extract the register
* LSR optimizations trigger (LSR isn't handling vector addresses currently)

Benchmarking show improvements on SystemZ with this new behaviour.

Any other target could try this by returning false in the new hook
prefersVectorizedAddressing().

Review: Renato Golin, Elena Demikhovsky, Ulrich Weigand
https://reviews.llvm.org/D32422

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303744 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-24 13:42:56 +00:00
Mikael Holmen
3bfeab444d MachineCSE: Respect interblock physreg liveness
Summary:
This is a fix for PR32538. MachineCSE first looks at MO.isDead(), but
if it is not marked dead, MachineCSE still wants to do its own check
to see if it is trivially dead. This check for the trivial case
assumed that physical registers cannot be live out of a block.

Patch by Mattias Eriksson.

Reviewers: qcolombet, jbhateja

Reviewed By: qcolombet, jbhateja

Subscribers: jbhateja, llvm-commits

Differential Revision: https://reviews.llvm.org/D33408

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303731 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-24 09:35:23 +00:00
Max Kazantsev
c7e5bebc4a [SCEV] Do not fold dominated SCEVUnknown into AddRecExpr start
When folding arguments of AddExpr or MulExpr with recurrences, we rely on the fact that
the loop of our base recurrency is the bottom-lost in terms of domination. This assumption
may be broken by an expression which is treated as invariant, and which depends on a complex
Phi for which SCEVUnknown was created. If such Phi is a loop Phi, and this loop is lower than
the chosen AddRecExpr's loop, it is invalid to fold our expression with the recurrence.

Another reason why it might be invalid to fold SCEVUnknown into Phi start value is that unlike
other SCEVs, SCEVUnknown are sometimes position-bound. For example, here:

for (...) { // loop
  phi = {A,+,B}
}
X = load ...
Folding phi + X into {A+X,+,B}<loop> actually makes no sense, because X does not exist and cannot
exist while we are iterating in loop (this memory can be even not allocated and not filled by this moment).
It is only valid to make such folding if X is defined before the loop. In this case the recurrence {A+X,+,B}<loop>
may be existant.

This patch prohibits folding of SCEVUnknown (and those who use them) into the start value of an AddRecExpr,
if this instruction is dominated by the loop. Merging the dominating unknown values is still valid. Some tests that
relied on the fact that some SCEVUnknown should be folded into AddRec's are changed so that they no longer
expect such behavior.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303730 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-24 08:52:18 +00:00
Daniel Sanders
6f7f2057b7 Explicitly set CPU and -slow-incdec to try to fix r303678's test on llvm-clang-x86_64-expensive-checks-win.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303727 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-24 07:02:37 +00:00
Daniel Sanders
3db1f7b146 Revert r303720: Tweak r303678's test to try to fix llvm-clang-x86_64-expensive-checks-win.
It doesn't fix that builder.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303721 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-24 06:44:55 +00:00
Daniel Sanders
69f6762057 Tweak r303678's test to try to fix llvm-clang-x86_64-expensive-checks-win.
I suspect this buildbot has slow-incdec set by default, most likely due to
the default CPU having this set. This feature bit can prevent optsize from
having an effect on this IR.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303720 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-24 06:05:14 +00:00
Davide Italiano
6ff9a78ce5 [NewGVN] Update additionalUsers when we simplify to a value.
Otherwise we don't revisit an instruction that could be simplified,
and when we verify, we discover there's something that changed, i.e.
what we had wasn't a maximal fixpoint.

Fixes PR32836.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303715 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-24 02:30:24 +00:00