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11188 Commits

Author SHA1 Message Date
Chris Lattner
dcd5abc70c silence a bogus warning 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23595 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-02 16:30:51 +00:00
Chris Lattner
3cf8760dc5 silence some warnings 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23594 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-02 16:29:36 +00:00
Chris Lattner
123557fcf0 silence a warning 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23593 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-02 16:27:59 +00:00
Chris Lattner
dff06f4348 add patterns for float binops and fma ops 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23592 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-02 07:46:28 +00:00
Chris Lattner
080a4b1637 Sort the cpu and features table, so that the alpha backend doesn't fail EVERY 
compile with an assertion that the tables are not sorted!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23591 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-02 07:13:52 +00:00
Chris Lattner
a3638c0f1f Add assertions to the trivial scheduler to check that the value types match 
up between defs and uses.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23590 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-02 07:10:55 +00:00
Chris Lattner
43f07a4bbc another solution to the fsel issue. Instead of having 4 variants, just force 
the comparison to be 64-bits.  This is fine because extensions from float
to double are free.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23589 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-02 07:07:49 +00:00
Chris Lattner
867940d1b7 fsel can take a different FP type for the comparison and for the result. As such 
split the FSEL family into 4 things instead of just two.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23588 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-02 06:58:23 +00:00
Chris Lattner
7c0d664c21 fix an f32/f64 type mismatch 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23587 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-02 06:37:13 +00:00
Chris Lattner
14765be0bc Codegen CopyFromReg using the regclass that matches the valuetype of the 
destination vreg.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23586 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-02 06:34:16 +00:00
Chris Lattner
a916dd8888 Adjust to change in ctor 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23585 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-02 06:23:51 +00:00
Chris Lattner
ca0a4778a8 Minor tweak to the branch selector. When emitting a two-way branch, and if 
we're in a single-mbb loop, make sure to emit the backwards branch as the
conditional branch instead of the uncond branch.  For example, emit this:

LBBl29_z__44:
        stw r9, 0(r15)
        stw r9, 4(r15)
        stw r9, 8(r15)
        stw r9, 12(r15)
        addi r15, r15, 16
        addi r8, r8, 1
        cmpw cr0, r8, r28
        ble cr0, LBBl29_z__44
        b LBBl29_z__48                   *** NOT PART OF LOOP

Instead of:

LBBl29_z__44:
        stw r9, 0(r15)
        stw r9, 4(r15)
        stw r9, 8(r15)
        stw r9, 12(r15)
        addi r15, r15, 16
        addi r8, r8, 1
        cmpw cr0, r8, r28
        bgt cr0, LBBl29_z__48            *** PART OF LOOP!
        b LBBl29_z__44

The former sequence has one fewer dispatch group for the loop body.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23582 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-01 23:06:26 +00:00
Chris Lattner
b91956e7f8 like the comment says, enable this 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23581 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-01 23:02:40 +00:00
Chris Lattner
505277a7f5 Add some very paranoid checking for operand/result reg class matchup 
For instructions that define multiple results, use the right regclass
to define the result, not always the rc of result #0


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23580 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-01 07:45:09 +00:00
Jeff Cohen
2aeaf4e839 Fix VC++ warnings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23579 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-01 03:57:14 +00:00
Chris Lattner
2c1760f636 fix typo 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23578 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-01 02:51:36 +00:00
Chris Lattner
919c032fa4 Modify the ppc backend to use two register classes for FP: F8RC and F4RC. 
These are used to represent float and double values, and the two regclasses
contain the same physical registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23577 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-01 01:35:02 +00:00
Chris Lattner
37345fe3cd add a method 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23575 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-01 00:17:07 +00:00
Jim Laskey
22f6212e9f typo 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23574 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-01 00:08:23 +00:00
Jim Laskey
41755e2c7e 1. Simplify the gathering of node groups. 
2. Printing node groups when displaying nodes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23573 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-01 00:03:07 +00:00
Jim Laskey
242f2557cc Should be using flag and not chain. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23572 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-30 23:43:37 +00:00
Nate Begeman
2b5e66fc6e Remove some now-dead code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23571 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-30 21:28:27 +00:00
Andrew Lenharth
ac35cd207f subtarget support for CIX and FIX extentions (the only 2 I care about right now) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23569 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-30 20:24:38 +00:00
Jim Laskey
b6d4c2cf2d 1. Made things node-centric (from operand). 
2. Added node groups to handle flagged nodes.

3. Started weaning simple scheduling off existing emitter.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23566 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-30 19:15:27 +00:00
Chris Lattner
0f21fd5204 Rename MRegisterDesc -> TargetRegisterDesc for consistency 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23564 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-30 17:49:27 +00:00
Chris Lattner
863914feb5 trim down the target info structs now that we have a preferred spill register class for each callee save register 
Why is V9 maintaining these tables manually? ugh!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23561 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-30 17:38:36 +00:00
Chris Lattner
8fb040e584 now that we have a reg class to spill with, get this info from the regclass 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23559 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-30 17:19:22 +00:00
Chris Lattner
5802be13e0 constant fold these calls 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23558 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-30 17:16:59 +00:00
Chris Lattner
56bcae0de9 simplify this code using the new regclass info passed in 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23557 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-30 17:12:38 +00:00
Chris Lattner
80a4f169b4 Now that we have getCalleeSaveRegClasses() info, use it to pass the register 
class into the spill/reload methods.  Targets can now rely on that argument.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23556 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-30 16:59:07 +00:00
Chris Lattner
e4047188e7 stub out a virtual method 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23554 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-30 06:55:18 +00:00
Chris Lattner
d174fe0ec3 CR registers are not used by this "target" 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23552 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-30 06:43:58 +00:00
Chris Lattner
0a37960d32 these registers don't belong to any register classes, so don't mark them 
as callee save.  They can never be generated by the compiler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23551 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-30 06:42:24 +00:00
Chris Lattner
ef242b1ccc Now that self referential classes are supported, get rid of a work-around. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23544 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-30 04:13:23 +00:00
Chris Lattner
b48d2cf5eb pass extra args 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23539 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-30 01:31:52 +00:00
Chris Lattner
0ffb1a56ff these methods get extra args 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23538 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-30 01:30:55 +00:00
Chris Lattner
97d5e6461a Pass extra regclasses into spilling code 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23537 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-30 01:29:42 +00:00
Chris Lattner
bf9716b9c4 Change this code ot pass register classes into the stack slot spiller/reloader 
code.  PrologEpilogInserter hasn't been updated yet though, so targets cannot
use this info.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23536 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-30 01:29:00 +00:00
Chris Lattner
ff201eebea Use the 32-bit version for now 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23534 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-30 00:05:05 +00:00
Chris Lattner
67ab118a6d Add a bunch of patterns for F64 FP ops, add some more integer ops 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23533 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-29 23:34:24 +00:00
Chris Lattner
237733e933 Remove code for patterns that are autogenerated 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23532 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-29 23:33:31 +00:00
Andrew Lenharth
120ab480ab begining alpha subtarget support 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23531 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-29 22:54:56 +00:00
Chris Lattner
c7a37a52cd tblgen autogens this pattern now 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23530 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-29 22:37:24 +00:00
Andrew Lenharth
68fd4866de copy and paste error 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23528 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-29 21:11:57 +00:00
Chris Lattner
221e53caea now that tblgen is smarter, this pattern is not needed. Also, tblgen 
now inverts commuted versions of ANDC/ORC with the current .td file.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23527 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-29 19:29:15 +00:00
Chris Lattner
93e50ce04c Insert stores after phi nodes in the normal dest. This fixes 
LowerInvoke/2005-08-03-InvokeWithPHI.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23525 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-29 17:44:20 +00:00
Chris Lattner
52897f827e consistency with other cases, no functionality change 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23524 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-29 17:38:52 +00:00
Chris Lattner
f13befb456 Make the JIT default to the DAG isel instead of the pattern isel, like LLC. 
The Pattern isel has some strange memory corruption issues going on. :(

This should have been converted over anyway, but it got forgotten somehow
when switching to the dag isel.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23523 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-29 17:31:03 +00:00
Chris Lattner
473a99073c Fix two bugs in my patch earlier today that broke int->fp conversion on X86. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23522 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-29 06:44:39 +00:00
Chris Lattner
a48bc53cad Fold isascii into a simple comparison. This speeds up 197.parser by 7.4%, 
bringing the LLC time down to the CBE time.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23521 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-29 06:17:27 +00:00