r315275 set the IsLittleEndian parameter incorrectly. This patch corrects
this, and adds a test to ensure such mistakes will be caught in the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316091 91177308-0d34-0410-b5e6-96231b3b80d8
%lo(), %hi(), and %pcrel_hi() are supported and test cases have been added to
ensure the appropriate fixups and relocations are generated. I've added an
instruction format field which is used in RISCVMCCodeEmitter to, for
instance, tell whether it should emit a lo12_i fixup or a lo12_s fixup
(RISC-V has two 12-bit immediate encodings depending on the instruction
type).
Differential Revision: https://reviews.llvm.org/D23568
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314389 91177308-0d34-0410-b5e6-96231b3b80d8
This patch supports all RV32I instructions as described in the RISC-V manual.
A future patch will add support for pseudoinstructions and other instruction
expansions (e.g. 0-arg fence -> fence iorw, iorw).
Differential Revision: https://reviews.llvm.org/D23566
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313485 91177308-0d34-0410-b5e6-96231b3b80d8
