Commit Graph

93784 Commits

Author SHA1 Message Date
Michael Kuperstein
f1860b7beb Make TwoAddressInstructionPass::rescheduleMIBelowKill subreg-aware
This fixes PR28824.

Differential Revision: https://reviews.llvm.org/D23220



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278370 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-11 17:38:33 +00:00
Matt Arsenault
d751c97ce5 AMDGPU: Fix crashes on memory functions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278369 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-11 17:31:42 +00:00
Matt Arsenault
9ffb824366 AArch64: Assert on analyzeBranch failing
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278366 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-11 17:22:59 +00:00
Michael Kuperstein
e99815b052 [AliasSetTracker] Delete dead code
Deletes unused remove() and containsPointer() interfaces. NFC.

Differential Revision: https://reviews.llvm.org/D23360


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278365 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-11 17:20:20 +00:00
Eugene Zelenko
c986ab210b Fix some Clang-tidy modernize and Include What You Use warnings.
Differential revision: https://reviews.llvm.org/D23291


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278364 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-11 17:20:18 +00:00
Matt Arsenault
f29c37acb0 AMDGPU: Remove custom getSubReg
This was kind of confusing, the subregister
class shouldn't really be necessary.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278362 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-11 17:15:32 +00:00
Matt Arsenault
ece2d8b253 AMDGPU: Remove unused tracking of flat instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278361 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-11 17:15:28 +00:00
Duncan P. N. Exon Smith
aba9f58b23 Hexagon: Avoid dereferencing end() in HexagonCopyToCombine::findPairable
Check for end() before skipping through debug values.  This avoids
dereferencing end() when the instruction is the final one in the basic
block.  (It still assumes that a debug value will not be the final
instruction in the basic block.  No tests seemed to violate that.)

Many Hexagon tests trigger this, but they happen to magically pass right
now.  I found this because WIP patches for PR26753 convert them into
crashes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278355 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-11 16:40:03 +00:00
Wei Ding
9bcebab62b AMDGPU : Add LLVM intrinsics for SAD related instructions.
Differential Revision: http://reviews.llvm.org/D23133

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278354 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-11 16:33:53 +00:00
Tim Northover
f1ef4a3eef GlobalISel: clear vreg mapping after translating each function
Otherwise we only materialize (shared) constants in the first function they
appear in. This doesn't go well.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278351 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-11 16:21:29 +00:00
Reid Kleckner
a4d7181fe4 Remove FIXME about asserting on the end iterator
After machine block placement, MBBs may not have terminators, and it is
appropriate to check for the end iterator here. We can fold the check
into the next if, as well. This look is really just looking for BBs that
end in CATCHRET.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278350 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-11 16:00:43 +00:00
Lang Hames
3f8d4e3f67 [MCJIT] Improve documentation and error handling for MCJIT::runFunction.
ExecutionEngine::runFunction is supposed to allow execution of arbitrary
function types, but MCJIT can only reasonably support a limited subset of
main-linke function types. This patch documents this limitation, and fixes
MCJIT::runFunction to abort with a meaningful error at runtime if called with
an unsupported function type.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278348 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-11 15:56:23 +00:00
Duncan P. N. Exon Smith
8949cc2a95 X86: Use operator lookup for operator==, NFC
Avoid relying on the MachineInstrBundleIterator operator== being
implemented as a member function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278347 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-11 15:51:29 +00:00
Duncan P. N. Exon Smith
9040acb5e3 IR: Don't cast the end iterator to Instruction*
End iterators are usually sentinels, not actually Instruction* at all.
Stop casting to it just to get an iterator back.

There is likely no observable functionality change here right now
(although this is relying on UB, I doubt it was triggering anything),
but I'll be removing the cast soon.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278346 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-11 15:45:04 +00:00
Duncan P. N. Exon Smith
91c138b3e0 CodeGen: Check for a terminator in llvm::getFuncletMembership
Check for an end iterator from MachineBasicBlock::getFirstTerminator in
llvm::getFuncletMembership.  If this is turned into an assertion, it
fires in 48 X86 testcases (for example,
CodeGen/X86/regalloc-spill-at-ehpad.ll).

Since this is likely a latent bug (shouldn't all basic blocks end with a
terminator?) I've filed PR28938.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278344 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-11 15:29:02 +00:00
Matthew Simpson
67914cbf05 [SLP] Make RecursionMaxDepth a command line option (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278343 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-11 15:28:45 +00:00
Sanjay Patel
16fc409d35 fix comment; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278342 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-11 15:23:56 +00:00
Sanjay Patel
583b94db9f use auto* with dyn_cast ; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278340 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-11 15:21:21 +00:00
Sanjay Patel
4636b0c422 getParent()->getParent() == getFunction() ; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278339 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-11 15:16:06 +00:00
Teresa Johnson
2d320e58a9 Restore "Resolution-based LTO API."
This restores commit r278330, with fixes for a few bot failures:
- Fix a late change I had made to the save temps output file that I
  missed due to existing files sitting on my disk
- Fix a bunch of Windows bot failures with "ambiguous call to overloaded
  function" due to confusion between llvm::make_unique vs
  std::make_unique (preface the new make_unique calls with "llvm::")
- Attempt to fix a modules bot failure by adding a missing include
  to LTO/Config.h.

Original change:

Resolution-based LTO API.

Summary:
This introduces a resolution-based LTO API. The main advantage of this API over
existing APIs is that it allows the linker to supply a resolution for each
symbol in each object, rather than the combined object as a whole. This will
become increasingly important for use cases such as ThinLTO which require us
to process symbol resolutions in a more complicated way than just adjusting
linkage.

Patch by Peter Collingbourne.

Reviewers: rafael, tejohnson, mehdi_amini

Subscribers: lhames, tejohnson, mehdi_amini, llvm-commits

Differential Revision: https://reviews.llvm.org/D20268

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278338 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-11 14:58:12 +00:00
Ehsan Amiri
d418a914db revert 278334
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278337 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-11 14:51:14 +00:00
Valery Pykhtin
d27913ee68 Revert "[AMDGPU] fix failure on printing of non-existing instruction operands."
This reverts revision 278333, newly added test failed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278336 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-11 14:22:05 +00:00
Ehsan Amiri
543fef7ea9 Extend trip count instead of truncating IV in LFTR, when legal
When legal, extending trip count in the loop control logic generates better code compared to truncating IV. This is because

(1) extending trip count is a loop invariant operation (see genLoopLimit where we prove trip count is loop invariant).
(2) Scalar Evolution seems to have problems understanding trunc when computing loop trip count. So removing them allows better analysis performed in Scalar Evolution. (In particular this fixes PR 28363 which is the motivation for this change).

I am not going to perform any performance test. Any degradation caused by this should be an indication of a bug elsewhere.

To prove legality, we rely on SCEV to prove zext(trunc(IV)) == IV (or similarly for sext). If this holds, we can prove equivalence of trunc(IV)==ExitCnt (1) and IV == zext(ExitCnt). Simply take zext of boths sides of (1) and apply the proven equivalence.

https://reviews.llvm.org/D23075



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278334 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-11 13:51:20 +00:00
Valery Pykhtin
3876e2e984 [AMDGPU] fix failure on printing of non-existing instruction operands.
Differential revision: https://reviews.llvm.org/D23323

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278333 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-11 13:49:46 +00:00
Teresa Johnson
6f0ab85031 Revert "Resolution-based LTO API."
This reverts commit r278330.

I made a change to the save temps output that is causing issues with the
bots. Didn't realize this because I had older output files sitting on
disk in my test output directory.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278331 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-11 13:03:56 +00:00
Teresa Johnson
9fd977036c Resolution-based LTO API.
Summary:
This introduces a resolution-based LTO API. The main advantage of this API over
existing APIs is that it allows the linker to supply a resolution for each
symbol in each object, rather than the combined object as a whole. This will
become increasingly important for use cases such as ThinLTO which require us
to process symbol resolutions in a more complicated way than just adjusting
linkage.

Patch by Peter Collingbourne.

Reviewers: rafael, tejohnson, mehdi_amini

Subscribers: lhames, tejohnson, mehdi_amini, llvm-commits

Differential Revision: https://reviews.llvm.org/D20268

Address review comments

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278330 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-11 12:56:40 +00:00
Simon Pilgrim
452ae8eb69 Fixed VS2015 (Update 3) warning - differing const/volatile qualifiers for overridden function
Dropped the const qualifier to match llvm::CallLowering::lowerCall

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278329 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-11 12:19:43 +00:00
Igor Breger
33ca8b83f6 [AVX512] Fix extractelement i1 lowering.
The previous implementation (not custom) doesn't enforce zeroing off upper bits. The assumption is that i1 PRODUCER (truncate and extractelement) must zero all upper bits, so i1 CONSUMER instructions ( test, zext, save, etc) can be done without additional zeroing.
Make extractelement i1 lowering custom for all vector i1.

Differential Revision: http://reviews.llvm.org/D23246

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278328 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-11 12:13:46 +00:00
Marina Yatsina
ac9ca3bbe7 Avoid false dependencies of undef machine operands
This patch helps avoid false dependencies on undef registers by updating the machine instructions' undef operand to use a register that the instruction is truly dependent on, or use a register with clearance higher than Pref.

Pseudo example:

loop:
xmm0 = ...
xmm1 = vcvtsi2sdl eax, xmm0<undef>
... = inst xmm0
jmp loop

In this example, selecting xmm0 as the undef register creates false dependency between loop iterations.
This false dependency cannot be solved by inserting an xor before vcvtsi2sdl because xmm0 is alive at the point of the vcvtsi2sdl instruction.
Selecting a different register instead of xmm0, especially a register that is not used in the loop, will eliminate this problem.

Differential Revision: https://reviews.llvm.org/D22466



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278321 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-11 07:32:08 +00:00
Craig Topper
d91ccf52e2 [AVX-512] Promote 512-bit integer loads to v8i64 similar to what is done for 128/256-bit vectors for overall consistency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278318 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-11 06:04:07 +00:00
Craig Topper
e0ce251bcc [AVX-512] Add patterns to allow EVEX encoded stores of v16i16/v8i16/v16i8/v32i8 even when BWI is not supported.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278317 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-11 06:04:04 +00:00
Craig Topper
bc13ca6202 [AVX-512] Fix the 128-bit and 256-bit nontemporal load patterns with elements type other than i64. These loads have all been promoted to v2i64/v4i64 loads so we need bitcasts or we end up selecting VMOVDQA32/VMOVDQU32 instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278316 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-11 06:04:00 +00:00
Xinliang David Li
b894886c6e [Profile] improve warning control option
Change --no-pgo-warn-missing to -pgo-warn-missing-function
and negate the default. /NFC

Add more test to make sure the warning is off by default




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278314 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-11 05:09:30 +00:00
Dominic Chen
a01f239d02 [WebAssembly] Cleanup trailing whitespace
Summary: Test for commit access.

Subscribers: jfb, dschuff

Differential Revision: https://reviews.llvm.org/D23392

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278313 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-11 04:10:56 +00:00
Easwaran Raman
a31d08bbe2 Make more fields of InlineParams Optional.
Differential revision: https://reviews.llvm.org/D23386


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278312 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-11 03:58:05 +00:00
Sanjoy Das
497124346e [Statepoints] Minor cosmetic change; NFC
The verification failure message was missing a space.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278309 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-11 00:56:46 +00:00
Chris Bieneman
50b70a6871 [MachOYAML] Don't output empty ExportTrie
The YAML representation was always outputting the root node of an export trie even if the trie was empty. While this doesn't really have any functional impact, it does add visual clutter to the yaml file.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278307 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-11 00:20:03 +00:00
Tim Northover
497466801a GlobalISel: support same ConstantExprs as Instructions.
It's more than just inttoptr, but the others can't be tested until we have
support for non-trivial constants (they currently get unavoidably folded to a
ConstantInt).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278303 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-10 23:02:41 +00:00
Tim Northover
3b3a95a083 GlobalISel: implement simple function calls on AArch64.
We're still limited in the arguments we support, but this at least handles the
basic cases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278293 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-10 21:44:01 +00:00
Changpeng Fang
4a0373d17a AMDGPU/SI: Implement amdgcn image intrinsics with sampler
Summary:
  This patch define and implement amdgcn image intrinsics with sampler.

    1. define vdata type to be llvm_anyfloat_ty, address type to be llvm_anyfloat_ty,
       and rsrc type to be llvm_anyint_ty. As a result, we expect the intrinsics name
       to have three suffixes to overload each of these three types;

    2. D128 as well as two other flags are implied in the three types, for example,
       if you use v8i32 as resource type, then r128 is 0!

    3. don't expose TFE flag, and other flags are exposed in the instruction order:
       unrm, glc, slc, lwe and da.

Differential Revision: http://reviews.llvm.org/D22838

Reviewed by:
  arsenm and tstellarAMD

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278291 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-10 21:15:30 +00:00
Piotr Padlewski
e70f4f796e Changed sign of LastCallToStaticBouns
Summary:
I think it is much better this way.
When I firstly saw line:
  Cost += InlineConstants::LastCallToStaticBonus;
I though that this is a bug, because everywhere where the cost is being reduced
it is usuing -=.

Reviewers: eraman, tejohnson, mehdi_amini

Subscribers: llvm-commits, mehdi_amini

Differential Revision: https://reviews.llvm.org/D23222

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278290 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-10 21:15:22 +00:00
Kyle Butt
0d1c7a1bea Codegen: Don't tail-duplicate blocks with un-analyzable fallthrough.
If AnalyzeBranch can't analyze a block and it is possible to
fallthrough, then duplicating the block doesn't make sense, as only one
block can be the layout predecessor for the un-analyzable fallthrough.

Submitted wit a test case, but NOTE: the test case doesn't currently
fail. However, the test case fails with D20505 and would have saved me
some time debugging.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278288 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-10 21:03:27 +00:00
Kyle Butt
3da1bfb213 CodeGen: If Convert blocks that would form a diamond when tail-merged.
The following function currently relies on tail-merging for if
conversion to succeed. The common tail of cond_true and cond_false is
extracted, and this then forms a diamond pattern that can be
successfully if converted.

If this block does not get extracted, either because tail-merging is
disabled or the threshold is higher, we should still recognize this
pattern and if-convert it.

Fixed a regression in the original commit. Need to un-reverse branches after
reversing them, or other conversions go awry.

define i32 @t2(i32 %a, i32 %b) nounwind {
entry:
        %tmp1434 = icmp eq i32 %a, %b           ; <i1> [#uses=1]
        br i1 %tmp1434, label %bb17, label %bb.outer

bb.outer:               ; preds = %cond_false, %entry
        %b_addr.021.0.ph = phi i32 [ %b, %entry ], [ %tmp10, %cond_false ]
        %a_addr.026.0.ph = phi i32 [ %a, %entry ], [ %a_addr.026.0, %cond_false ]
        br label %bb

bb:             ; preds = %cond_true, %bb.outer
        %indvar = phi i32 [ 0, %bb.outer ], [ %indvar.next, %cond_true ]
        %tmp. = sub i32 0, %b_addr.021.0.ph
        %tmp.40 = mul i32 %indvar, %tmp.
        %a_addr.026.0 = add i32 %tmp.40, %a_addr.026.0.ph
        %tmp3 = icmp sgt i32 %a_addr.026.0, %b_addr.021.0.ph
        br i1 %tmp3, label %cond_true, label %cond_false

cond_true:              ; preds = %bb
        %tmp7 = sub i32 %a_addr.026.0, %b_addr.021.0.ph
        %tmp1437 = icmp eq i32 %tmp7, %b_addr.021.0.ph
        %indvar.next = add i32 %indvar, 1
        br i1 %tmp1437, label %bb17, label %bb

cond_false:             ; preds = %bb
        %tmp10 = sub i32 %b_addr.021.0.ph, %a_addr.026.0
        %tmp14 = icmp eq i32 %a_addr.026.0, %tmp10
        br i1 %tmp14, label %bb17, label %bb.outer

bb17:           ; preds = %cond_false, %cond_true, %entry
        %a_addr.026.1 = phi i32 [ %a, %entry ], [ %tmp7, %cond_true ], [ %a_addr.026.0, %cond_false ]
        ret i32 %a_addr.026.1
}

Without tail-merging or diamond-tail if conversion:
LBB1_1:                                 @ %bb
                                        @ =>This Inner Loop Header: Depth=1
        cmp     r0, r1
        ble     LBB1_3
@ BB#2:                                 @ %cond_true
                                        @   in Loop: Header=BB1_1 Depth=1
        subs    r0, r0, r1
        cmp     r1, r0
        it      ne
        cmpne   r0, r1
        bgt     LBB1_4
LBB1_3:                                 @ %cond_false
                                        @   in Loop: Header=BB1_1 Depth=1
        subs    r1, r1, r0
        cmp     r1, r0
        bne     LBB1_1
LBB1_4:                                 @ %bb17
        bx      lr

With diamond-tail if conversion, but without tail-merging:
@ BB#0:                                 @ %entry
        cmp     r0, r1
        it      eq
        bxeq    lr
LBB1_1:                                 @ %bb
                                        @ =>This Inner Loop Header: Depth=1
        cmp     r0, r1
        ite     le
        suble   r1, r1, r0
        subgt   r0, r0, r1
        cmp     r1, r0
        bne     LBB1_1
@ BB#2:                                 @ %bb17
        bx      lr

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278287 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-10 20:45:56 +00:00
Jonathan Roelofs
9715a2d267 Fix UB in APInt::ashr
i64 -1, whose sign bit is the 0th one, can't be left shifted without invoking UB.

https://reviews.llvm.org/D23362


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278280 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-10 19:50:14 +00:00
Matt Arsenault
7616e5d399 AMDGPU: s_setpc_b64 should be an indirect branch
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278278 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-10 19:20:02 +00:00
Matt Arsenault
a9d5cfbb5d AMDGPU: Set sizes on control flow pseudos
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278276 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-10 19:11:51 +00:00
Matt Arsenault
054b698c76 AMDGPU: Remove empty file comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278275 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-10 19:11:48 +00:00
Matt Arsenault
0576028ed1 AMDGPU: Remove unnecessary cast
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278274 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-10 19:11:45 +00:00
Matt Arsenault
34c6b123f7 AMDGPU: Change insertion point of si_mask_branch
Insert before the skip branch if one is created.
This is a somewhat more natural placement relative
to the skip branches, and makes it possible to implement
analyzeBranch for skip blocks.

The test changes are mostly due to a quirk where
the block label is not emitted if there is a terminator
that is not also a branch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278273 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-10 19:11:42 +00:00
Matt Arsenault
898f0e0994 AMDGPU: Use CreateStackObject instead of CreateSpillStackObject
I'm not sure what the difference is, but no other target
uses this for emergency spill slots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278272 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-10 19:11:36 +00:00