Commit Graph

18273 Commits

Author SHA1 Message Date
Nico Weber f83ecb0d7e Revert r281715, it caused PR30475
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@282076 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-21 15:33:24 +00:00
Tim Northover c297159d2f GlobalISel: produce correct code for signext/zeroext ABI flags.
We still don't really have an equivalent of "AssertXExt" in DAG, so we don't
exploit the guarantees on the receiving side yet, but this should produce
conservatively correct code on iOS ABIs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@282069 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-21 12:57:45 +00:00
Simon Dardis abc7f410e9 [mips] LLVM PR/30197 - Tail call incorrectly clobbers arguments for mips
The postRA scheduler performs alias analysis to determine if stores and loads
can moved past each other. When a function has more arguments than argument
registers for the calling convention used, excess arguments are spilled onto the
stack. LLVM by default assumes that argument slots are immutable, unless the
function contains a tail call. Without the knowledge of that a function contains
a tail call site, stores and loads to fixed stack slots may be re-ordered
causing the out-going arguments to clobber the incoming arguments before the
incoming arguments are supposed to be dead.

Reviewers: vkalintiris

Differential Review: https://reviews.llvm.org/D24077



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@282063 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-21 09:43:40 +00:00
NAKAMURA Takumi bba417d327 llvm/test/CodeGen/NVPTX/zero-cs.ll: Relax an expression to match in -Asserts.
LLVM ERROR: Cannot select: 0x3607bf0: i32 = ExternalSymbol'__powidf2'

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@282053 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-21 04:43:11 +00:00
Jacques Pienaar 1d75557110 [NVPTX] Check if callsite is defined when computing argument allignment
Summary: In getArgumentAlignment check if the ImmutableCallSite pointer CS is non-null before dereferencing. If CS is 0x0 fall back to the ABI type alignment else compute the alignment as before.

Reviewers: eliben, jpienaar

Subscribers: jlebar, vchuravy, cfe-commits, jholewinski

Differential Revision: https://reviews.llvm.org/D9168

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@282045 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-21 01:57:57 +00:00
Petr Hosek 38ea316607 Mark ELF sections whose name start with .note as note
Previously, such section would be marked as SHT_PROGBITS which
makes it impossible to use an initialized C variable declaration
to emit an (allocated) ELF note. The new behavior is also consistent
with ELF assembly parser.

Differential Revision: https://reviews.llvm.org/D24692

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@282010 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-20 20:21:13 +00:00
Sanjay Patel ba03c81918 [x86] split up tests, regenerate checks
Note that we fail to eliminate 'or' with 0!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@282005 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-20 19:31:30 +00:00
Evandro Menezes 1bacc96e0e Revert "[AArch64] Use the reciprocal estimation machinery"
This reverts commit b7d42b0048f65346e9fa37fb65defeea7ce8c337 per request by
Eric Christopher <echristo@gmail.com> (v. http://bit.ly/2cmz6kW).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@282000 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-20 19:02:06 +00:00
Evandro Menezes ba27f9fd81 Revert "[AArch64] Properly validate the reciprocal estimation."
This reverts commit ad8ca1528242e2a4cb363e3779309e70eb7a430e per request by
Eric Christopher <echristo@gmail.com> (v. http://bit.ly/2cmz6kW).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281999 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-20 19:02:02 +00:00
Tim Northover a93f61a2c3 GlobalISel: split aggregates for PCS lowering
This should match the existing behaviour for passing complicated struct and
array types, in particular HFAs come through like that from Clang.

For C & C++ we still need to somehow support all the weird ABI flags, or at
least those that are present in the IR (signext, byval, ...), and stack-based
parameter passing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281977 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-20 15:20:36 +00:00
Simon Pilgrim e4f1232c49 [X86][SSE] Regenerate multiple combine tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281973 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-20 14:42:45 +00:00
Elena Demikhovsky 8e5c84a8d4 AVX-512: Fixed a bug in lowering saturated operations on KNL.
The generated code is still not optimal.

Differential Revision: https://reviews.llvm.org/D24723



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281966 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-20 11:02:26 +00:00
Craig Topper fd8c733710 [AVX-512] Use 512-bit vcvtps2ph/vcvtph2ps to implement fp_to_f16/f16_to_fp when F16C and VLX are not supported.
Fixes PR23941.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281958 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-20 05:44:47 +00:00
Matthias Braun b72235f318 BranchFolder: Fix invalid undef flags after merge.
It is legal to merge instructions with different undef flags; However we
must drop the undef flag from the merged instruction if it isn't present
everywhere.

This fixes http://llvm.org/PR30199

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281957 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-20 01:14:42 +00:00
Sanjay Patel f8408ab22c [x86] auto-generate checks
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281950 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-19 23:44:50 +00:00
Simon Pilgrim 4f6fc26807 [X86][SSE] Updated vector abs tests
Renamed and added v2i64 / v4i64 tests

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281937 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-19 20:50:35 +00:00
Matthias Braun b0731963da LiveRangeCalc: Fix reporting of invalid vreg usage in liveness calculation
Machine programs need a definition of each vreg before reaching a use
(the definition may come from an IMPLICIT_DEF instruction). This class
of errors is not detected by the MachineVerifier because of efficiency
concerns. LiveRangeCalc used to report these problems, make it do that
again (followup to r279625).

Also use report_fatal_error() instead of llvm_unreachable() as the error
reporting is only present in asserts build anyway.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281914 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-19 16:49:45 +00:00
Nico Weber ebd2807ce8 Revert r281841, it does not work on Windows (PR30443).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281905 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-19 15:22:04 +00:00
Tim Northover ab6de7f248 ARM: check alignment before transforming ldr -> ldm (or similar).
ldm and stm instructions always require 4-byte alignment on the pointer, but we
weren't checking this before trying to reduce code-size by replacing a
post-indexed load/store with them. Unfortunately, we were also dropping this
incormation in DAG ISel too, but that's easy enough to fix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281893 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-19 09:11:09 +00:00
Elena Demikhovsky 01736613c2 [X86 Codegen Test] Divided masked_memop into several files. NFC.
The masked_memop.ll became huge. I extracted AVX-512 specific tests into separate files.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281892 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-19 08:58:43 +00:00
Craig Topper d854787edd [X86,AVX-512] Use INSERT_SUBREG instead of SUBREG_TO_REG when the input is not the output of an instruction.
SUBREG_TO_REG is supposed to indicate that the super register has been zeroed, but we can't prove that if we don't know where it came from.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281885 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-19 02:53:43 +00:00
Craig Topper d5369d3bd4 [AVX-512] Add support for lowering fp_to_f16 and f16_to_fp when VLX is supported regardless of whether F16C is also supported.
Still need to add support for lowering using AVX512F when neither VLX or F16C is supported.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281884 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-19 02:53:37 +00:00
Dean Michael Berris 916b3667a3 [XRay] ARM 32-bit no-Thumb support in LLVM
This is a port of XRay to ARM 32-bit, without Thumb support yet. The XRay instrumentation support is moving up to AsmPrinter.
This is one of 3 commits to different repositories of XRay ARM port. The other 2 are:

https://reviews.llvm.org/D23932 (Clang test)
https://reviews.llvm.org/D23933 (compiler-rt)

Differential Revision: https://reviews.llvm.org/D23931

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281878 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-19 00:54:35 +00:00
Simon Pilgrim 428ba8ee90 [X86][SSE] Improve recognition of uitofp conversions that can be performed as sitofp
With D24253 we can now use SelectionDAG::SignBitIsZero with vector operations.

This patch uses SelectionDAG::SignBitIsZero to recognise that a zero sign bit means that we can use a sitofp instead of a uitofp (which is not directly support on pre-AVX512 hardware).

While AVX512 does provide support for uitofp, the conversion to sitofp should not cause any regressions.

Differential Revision: https://reviews.llvm.org/D24343

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281852 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-18 12:45:23 +00:00
Wei Mi f54e133dd2 Change the order of the splitted store from high - low to low - high.
It is a trivial change which could make the testcase easier to be reused
for the store splitting in CodeGenPrepare.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281846 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-18 06:10:32 +00:00
Simon Pilgrim 52c60cece6 [X86][SSE] Added vector udiv combine tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281842 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-17 22:02:23 +00:00
Simon Pilgrim 063b3271dc [X86][SSE] Added vector fcopysign combine tests
Also demonstrating the poor lowering of fcopysign...


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281841 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-17 21:31:34 +00:00
Simon Pilgrim 1982c8eed7 [X86][SSE] Added vector mul combine tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281839 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-17 20:06:16 +00:00
Simon Pilgrim cbaa900ad9 [X86][SSE] Improve target shuffle mask extraction
Add ability to extract vXi64 'vzext_movl' masks on 32-bit targets

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281834 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-17 18:50:54 +00:00
Simon Pilgrim 83d088fe4b [X86][AVX] Test target shuffle combining on 32 and 64-bit targets
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281833 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-17 18:42:41 +00:00
Simon Pilgrim db0c416394 [X86][AVX2] Add target shuffle constant folding tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281830 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-17 17:42:15 +00:00
Simon Pilgrim 679cf9558a [X86][AVX] Add target shuffle constant folding tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281829 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-17 17:41:14 +00:00
Simon Pilgrim aa105ad95d [X86][XOP] Add target shuffle constant folding tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281828 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-17 17:40:40 +00:00
Simon Pilgrim 05c5270a67 [X86][SSSE3] Add target shuffle constant folding tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281827 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-17 17:40:08 +00:00
Ron Lieberman 973dd0ece5 [Hexagon] segv while processing SUnit with nullNodePtr
Added BoundaryNode check to isBestZeroLatency function.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281825 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-17 16:21:09 +00:00
Matt Arsenault de82da5521 AMDGPU: Fix broken FrameIndex handling
We were trying to avoid using a FrameIndex operand in non-pointer
operands in a convoluted way, and would break because of
using TargetFrameIndex. The TargetFrameIndex should only be used
in the case where it makes sense to fold it as part of the addressing
mode, otherwise it requires materialization like a normal constant.
This wasn't working reliably and failed in the added testcase, hitting
the assert when processing the frame index.

The TargetFrameIndex was coming from trying to produce an AssertZext
limiting the maximum stack size. I'm not sure this was correct to begin
with, because it is apparently possible to have a single workitem
dispatch that requires all 4G of private memory.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281824 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-17 16:09:55 +00:00
Matt Arsenault 077ab85e5a AMDGPU: Push bitcasts through build_vector
This reduces the number of copies and reg_sequences
when using fp constant vectors. This significantly
reduces the code size in local-stack-alloc-bug.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281822 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-17 15:44:16 +00:00
Matt Arsenault 982faf27a3 AMDGPU: Use i64 scalar compare instructions
VI added eq/ne for i64, so use them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281800 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-17 02:02:19 +00:00
Tom Stellard 019f4de043 AMDGPU/SI: Fix kernel argument ABI for HSA
Summary: i8, i16, and f16 values are not extended to 32-bit in the HSA kernel ABI.

Reviewers: arsenm

Subscribers: arsenm, kzhuravl, wdng, nhaehnle, llvm-commits, yaxunl

Differential Revision: https://reviews.llvm.org/D24621

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281789 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 22:20:24 +00:00
Matt Arsenault 8f824feb12 AMDGPU: Allow some control flow intrinsics to be CSEd
These clean up some unnecessary or instructions in
cases with complex loops.

In the original testcase I noticed this, the same
or with exec was repeated 5 or 6 times in a row. With
this only one is emitted or sometimes a copy.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281786 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 22:11:18 +00:00
Tom Stellard 77361ae206 AMDGPU: Refactor kernel argument lowering
Summary:
The main challenge in lowering kernel arguments for AMDGPU is determing the
memory type of the argument.  The generic calling convention code assumes
that only legal register types can be stored in memory, but this is not the
case for AMDGPU.

This consolidates all the logic AMDGPU uses for deducing memory types into a single
function.  This will make it much easier to support different ABIs in the future.

Reviewers: arsenm

Subscribers: arsenm, wdng, nhaehnle, llvm-commits, yaxunl

Differential Revision: https://reviews.llvm.org/D24614

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281781 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 21:53:00 +00:00
Matt Arsenault 3a74bac021 AMDGPU: Use SOPK compare instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281780 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 21:41:16 +00:00
Tom Stellard 1961591989 AMDGPU/SI: Add support for triples with the mesa3d operating system
Summary:
mesa3d will use the same kernel calling convention as amdhsa, but it will
handle everything else like the default 'unknown' OS type.

Reviewers: arsenm

Subscribers: arsenm, llvm-commits, kzhuravl

Differential Revision: https://reviews.llvm.org/D22783

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281779 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 21:34:26 +00:00
Derek Schuff 740da34c34 [WebAssembly] Fix function types of CFGStackify tests
Make the function's declared type match its (lack of) return type

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281773 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 20:58:31 +00:00
Simon Pilgrim 839ecc81ef [X86][SSE] Added vector sub combine tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281769 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 20:00:51 +00:00
Simon Pilgrim b2c2d1f82a [X86][SSE] Added vector add combine tests
Some work great and others currently demonstrate the anti-vector bias prevalent in DAGCombiner

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281768 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 19:20:41 +00:00
Michael Kuperstein 6dc8c1ab98 Make test slightly more explicit. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281759 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 18:20:43 +00:00
Ahmed Bougacha c49f5e8a93 [AArch64][GlobalISel] Add default regbank mapping for int<>FP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281739 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 15:12:46 +00:00
Ahmed Bougacha d705c9fe79 [AArch64][GlobalISel] Add default regbank mapping for G_FCMP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281738 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 15:12:43 +00:00
Ahmed Bougacha 16527fa797 [AArch64][GlobalISel] Add default regbank mapping for FP ops.
These should have all their operands - even scalars - go on FPR.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281737 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 15:12:40 +00:00