Commit Graph

25359 Commits

Author SHA1 Message Date
Lama Saba 5bfef87829 [X86] - Avoid SFB pass - fix bug in updating the offsets for newly created copies
Change-Id: I169ab6fe7e187727c0298c2a1e2868a683f3e688

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332849 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-21 16:23:16 +00:00
Tim Northover b096d31bb6 ARM: be conservative when asked load/store alignment of weird type.
Chances are we'll be asked again after type legalization, but before that point
it's better to claim misaligned accesses aren't allowed than to assert.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332840 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-21 12:43:54 +00:00
Aleksandar Beserminji edeb7b8e33 [mips] Revert Merge MipsLongBranch and MipsHazardSchedule passes
Revert this patch due buildbot failure.

Differential Revision: https://reviews.llvm.org/D46641



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332837 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-21 11:38:52 +00:00
Aleksandar Beserminji b3845567bd [mips] Merge MipsLongBranch and MipsHazardSchedule passes
MipsLongBranchPass and MipsHazardSchedule passes are joined to one pass
because of mutual conflict. When MipsHazardSchedule inserts 'nop's, it
potentially breaks some jumps, so they have to be expanded to long
branches. When some branch is expanded to long branch, it potentially
creates a hazard situation, which should be fixed by adding nops.
New pass is called MipsBranchExpansion, it combines these two passes,
and runs them alternately until one of them reports no changes were made.

Differential Revision: https://reviews.llvm.org/D46641



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332834 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-21 10:20:02 +00:00
Simon Pilgrim 071d9bcd62 [X86][SSE] Support v4i32 rotations (PR37426)
As suggested by Fabian on PR37426, we can use PMULUDQ to perform v4i32 vector rotations as the upper 32bits of the multiply will contain the 'wrapped' bits of the rotation.

v8i16/v16i8 rotations would be straightforward to add to lowerRotate in the future - ideally we'd mostly share code with the vector shifts lowering.

Differential Revision: https://reviews.llvm.org/D46954

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332832 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-21 09:45:59 +00:00
Craig Topper aa228ef4a3 [X86] Remove mask arguments from permvar builtins/intrinsics. Use a select in IR instead.
Someday maybe we'll use selects for all intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332824 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-20 23:34:04 +00:00
Craig Topper 56669ed246 [X86] Add test cases to show missed rotate opportunities due to SimplifyDemandedBits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332815 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-20 02:32:45 +00:00
Haicheng Wu b508121673 [GlobalMerge] Exit early if only one global is to be merged
To save some compilation time and prevent some unnecessary changes.

Differential Revision: https://reviews.llvm.org/D46640

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332813 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-19 18:00:02 +00:00
Sanjay Patel 239df32c7d [x86] add more FP with FMF simplification tests; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332780 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-18 22:31:43 +00:00
Matt Arsenault 22ecb3d712 DAG: Fix crash on shift with large shift amounts
Fixes bug 37521.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332774 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-18 21:54:16 +00:00
Matt Arsenault cdbb0ae52b AMDGPU: Add pass to optimize reqd_work_group_size
Eliminate loads from the dispatch packet when they will have
a known value.

Also pattern match the code used by the library to handle partial
workgroup dispatches, which isn't necessary if reqd_work_group_size
is used.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332771 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-18 21:35:00 +00:00
Michael Berg ff2a8ccbe9 adding baseline fp fold tests for unsafe on and off
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332756 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-18 19:30:49 +00:00
Brendon Cahoon d5b9305f2a [Hexagon] Generate post-increment for floating point types
The code that generates post-increments for Hexagon considered
integer values only. This patch adds support to generate them for
floating point values, f32 and f64.

Differential Revision: https://reviews.llvm.org/D47036


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332748 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-18 18:14:44 +00:00
Simon Pilgrim 69d22499d3 [X86] Add GPR<->XMM Schedule Tags
BtVer2 - fix NumMicroOp and account for the Lat+6cy GPR->XMM and Lat+1cy XMm->GPR delays (see rL332737)

The high number of MOVD/MOVQ equivalent instructions meant that there were a number of missed patterns in SNB/Znver1:
SNB - add missing GPR<->MMX costs (taken from Agner / Intel AOM)
Znver1 - add missing GPR<->XMM MOVQ costs (taken from Agner)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332745 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-18 17:58:36 +00:00
Craig Topper ad7c2e9c6a [X86] Directly legalize v16i16/v8i16 vselect to vXi8 vselect to use VPBLENDVB
The intrinsic legalization for masked truncate uses ISD::TRUNCATE which can be constant folded by getNode. This prevents getVectorMaskingNode from seeing the ISD::TRUNCATE special case where it should emit X86ISD::SELECT instead of ISD::VSELECT. This causes a vselect with a v16i1 or v8i1 condition to be emitted during vector legalization. but vector legalization doesn't revisit nodes it creates. DAG combine will then promote this condition to match the result type. Then op legalization will try to legalize it, but the custom lowering hook returned SDValue(). But op legalization doesn't have an Expand for VSELECT because it expects vector legalization to have taken care of it. So the operation sticks around and fails in isel.

This patch adds a custom legalization hook to morph it to a vXi8 vselect instead.

This also simplifies the normal vXi16 vselect handling because vector legalization was normally expanding to AND/ANDN/OR and DAG combine was turning that into VBLENDVB. So we can skip a step by doing it directly.

Fixes PR37499

Differential Revision: https://reviews.llvm.org/D47025

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332743 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-18 17:48:06 +00:00
Than McIntosh a39a917dbf Revert changes from D46265.
This is a revert of the changes from https://reviews.llvm.org/D46265;
the new test introduced (test/CodeGen/X86/PR37310.mir) causes buildbot
failures.

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D47061

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332742 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-18 17:47:10 +00:00
Craig Topper 6af49b5c06 [X86] Update fast-isel test cases for _mm256_mask_cvtepi16_epi8 to match clang r332738.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332740 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-18 17:29:47 +00:00
Simon Pilgrim 1c0183accb [X86][BtVer2] Improve simulation of (V)PINSR values
Include the 6cy delay transferring from the GPR to FPU.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332737 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-18 17:09:41 +00:00
Simon Pilgrim 96a67f1256 [X86][BtVer2] Partial vector stores (inc MMX) have a 2cy latency
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332722 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-18 14:22:22 +00:00
Than McIntosh a739ddd3fe StackColoring: better handling of statically unreachable code
Summary:
Avoid assert/crash during liveness calculation in situations where the
incoming machine function has statically unreachable BBs.

Fixes PR37130.

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D46265

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332707 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-18 12:25:30 +00:00
Alexander Ivchenko 1fcee954a4 [X86][CET] Changing -fcf-protection behavior to comply with gcc (LLVM part)
This patch aims to match the changes introduced in gcc by
https://gcc.gnu.org/ml/gcc-cvs/2018-04/msg00534.html. The
IBT feature definition is removed, with the IBT instructions
being freely available on all X86 targets. The shadow stack
instructions are also being made freely available, and the
use of all these CET instructions is controlled by the module
flags derived from the -fcf-protection clang option. The hasSHSTK
option remains since clang uses it to determine availability of
shadow stack instruction intrinsics, but it is no longer directly used.

Comes with a clang patch (D46881).

Patch by mike.dvoretsky

Differential Revision: https://reviews.llvm.org/D46882



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332705 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-18 11:58:25 +00:00
Jonas Paulsson 3447c1011d [SystemZ] Fold AHIMux in foldMemoryOperandImpl.
AHIMux can be folded the same way as AHI.

Review: Ulrich Weigand

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332703 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-18 11:54:04 +00:00
Keno Fischer f5e705e803 [X86DomainReassignment] Hopefully fix buildbot failure
The Darwin build bot failed with:
```
llc -mcpu=skylake-avx512 -mtriple=x86_64-unknown-linux-gnu domain-reassignment-test.ll -o - | llvm-mc
--
Exit Code: 134

Command Output (stderr):
--
Assertion failed: (MAI->hasSingleParameterDotFile()), function EmitFileDirective, file lib/MC/MCAsmStreamer.cpp, line 1087.
```

Looks like this is because the `llvm-mc` command was missing a triple
directive and defaulting to MachO. Add the triple option.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332694 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-18 04:36:38 +00:00
Eli Friedman c7cc20b7d7 [MachineOutliner] Count savings from outlining in bytes.
Counting the number of instructions is both unintuitive and inaccurate.
On AArch64, this only affects the generated remarks and certain rare
pseudo-instructions, but it will have a bigger impact on other targets.

Differential Revision: https://reviews.llvm.org/D46921



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332685 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-18 01:52:16 +00:00
Keno Fischer ed72507052 [X86DomainReassignment] Don't compare stack-allocated values by address
Summary:
The Closure allocated in the main loop is allocated on the stack. However,
later in the code its address is taken (and used for comparisons). This
obviously doesn't work. In fact, the Closure will get the same stack address
during every loop iteration, rendering the check that intended to identify
Closure conflicts entirely ineffective. Fix this bug by giving every Closure
a unique ID and using that for comparison. Alternatively, we could heap
allocate the closure object.

Fixes PR37396
Fixes JuliaLang/julia#27032

Reviewers: craig.topper, guyblank

Reviewed By: craig.topper

Subscribers: vchuravy, llvm-commits

Differential Revision: https://reviews.llvm.org/D46800

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332682 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-18 01:03:01 +00:00
Keno Fischer 4464e8f60f [X86DomainReassignment] Don't delete IMPLICIT_DEF nodes
Summary:
We cannot simply delete IMPLICIT_DEF nodes. They may be used
later (e.g. by a PHI) and deleting them will cause later passes (e.g.
LiveVariables) to crash. However, it seems fine to ignore them for
purposes of the domain reassignment (as we do with PHI).

Fixes PR37430
Fixes JuliaLang/julia#27080

Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D46797

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332680 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-18 00:40:52 +00:00
Changpeng Fang 54a7d61d8c AMDGPU/SI: Don't promote alloca to vector for atomic load/store
Summary:
  Don't promote alloca to vector for atomic load/store

Reviewer:
  arsenm

Differential Revision:
  https://reviews.llvm.org/D46085

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332673 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-17 21:49:44 +00:00
Sanjay Patel c66bd0a430 [x86] preserve test intent by removing undef
We need to clean up the DAG floating-point undef logic.
This process is similar to how we handled integer undef
logic in https://reviews.llvm.org/D43141.

And as we did there, I'm trying to reduce the patch by
changing tests that would probably become meaningless
once we correct FP undef folding.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332648 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-17 18:43:44 +00:00
Sameer AbuAsal 6c8d8d769f [RISCV] Separate base from offset in lowerGlobalAddress
Summary:
When lowering global address, lower the base as a TargetGlobal first then
 create an SDNode for the offset separately and chain it to the address calculation

 This optimization will create a DAG where the base address of a global access will
 be reused between different access. The offset can later be folded into the immediate
 part of the memory access instruction.

  With this optimization we generate:

    lui a0, %hi(s)
    addi a0, a0, %lo(s) ; shared base address.

    addi a1, zero, 20 ; 2 instructions per access.
    sw a1, 44(a0)

    addi a1, zero, 10
    sw a1, 8(a0)

    addi a1, zero, 30
    sw a1, 80(a0)

    Instead of:

    lui a0, %hi(s+44) ; 3 instructions per access.
    addi a1, zero, 20
    sw a1, %lo(s+44)(a0)

    lui a0, %hi(s+8)
    addi a1, zero, 10
    sw a1, %lo(s+8)(a0)

    lui a0, %hi(s+80)
    addi a1, zero, 30
    sw a1, %lo(s+80)(a0)

    Which will save one instruction per access.

Reviewers: asb, apazos

Reviewed By: asb

Subscribers: rbar, johnrusso, simoncook, jordy.potman.lists, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, mgrang, apazos, asb, llvm-commits

Differential Revision: https://reviews.llvm.org/D46989

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332641 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-17 18:14:53 +00:00
Sanjay Patel 03da9798c1 [x86] preserve test intent by removing undef
We need to clean up the DAG floating-point undef logic.
This process is similar to how we handled integer undef
logic in https://reviews.llvm.org/D43141.

And as we did there, I'm trying to reduce the patch by
changing tests that would probably become meaningless
once we correct FP undef folding.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332640 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-17 18:13:58 +00:00
Sanjay Patel b231180388 [ARM] preserve test intent by removing undef
We need to clean up the DAG floating-point undef logic.
This process is similar to how we handled integer undef
logic in https://reviews.llvm.org/D43141.

And as we did there, I'm trying to reduce the patch by
changing tests that would probably become meaningless
once we correct FP undef folding.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332638 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-17 18:09:56 +00:00
Sanjay Patel 28e0f25edb [ARM] preserve test intent by removing undef
We need to clean up the DAG floating-point undef logic.
This process is similar to how we handled integer undef
logic in https://reviews.llvm.org/D43141.

And as we did there, I'm trying to reduce the patch by
changing tests that would probably become meaningless
once we correct FP undef folding.

Follow-up to:
https://reviews.llvm.org/rL332538
...because that change wasn't enough.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332637 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-17 18:08:27 +00:00
Sanjay Patel 19e6e2d115 [AArch64] preserve test intent by removing undef
We need to clean up the DAG floating-point undef logic.
This process is similar to how we handled integer undef
logic in D43141.

And as we did there, I'm trying to reduce the patch by
changing tests that would probably become meaningless
once we correct FP undef folding.

Follow-up to:
https://reviews.llvm.org/rL332534
...because that change wasn't enough.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332636 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-17 18:07:02 +00:00
Changpeng Fang ce74ac3067 AMDGPU/SI: Handle infinite loop for the structurizer to work with CFG with infinite loops.
Summary:
  The current StructurizeCFG pass only works for CFG with one exit. AMDGPUUnifyDivergentExitNodes combines multiple "return" blocks and/or "unreachable" blocks
to one exit block for the Structurizer to work. However, infinite loop is another kind of special "exit", and if we don't handle it, the case of multiple exits will prevent the structurizer from working.

In this work, for each infinite loop, we add a dummy edge to the "return" block, and thus the AMDGPUUnifyDivergentExitNodes pass will work with infinite loops.
This will make CFG with infinite loops be structurized.

Reviewer:
  nhaehnle

Differential Revision:
  https://reviews.llvm.org/D46340

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332625 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-17 16:45:01 +00:00
Alex Bradbury 938d593207 [RISCV] Set isReMaterializable on ADDI and LUI instructions
The isReMaterlizable flag is somewhat confusing, unlike most other instruction 
flags it is currently interpreted as a hint (mightBeRematerializable would be 
a better name). While LUI is always rematerialisable, for an instruction like 
ADDI it depends on its operands. TargetInstrInfo::isTriviallyReMaterializable 
will call TargetInstrInfo::isReallyTriviallyReMaterializable, which in turn 
calls TargetInstrInfo::isReallyTriviallyReMaterializableGeneric. We rely on 
the logic in the latter to pick out instances of ADDI that really are 
rematerializable.

The isReMaterializable flag does make a difference on a variety of test 
programs. The recently committed remat.ll test case demonstrates how stack 
usage is reduce and a unnecessary lw/sw can be removed. Stack usage in the 
Proc0 function in dhrystone reduces from 192 bytes to 112 bytes.

For the sake of completeness, this patch also implements 
RISCVRegisterInfo::isConstantPhysReg. Although this is called from a number of 
places, it doesn't seem to result in different codegen for any programs I've 
thrown at it. However, it is called in the rematerialisation codepath and it 
seems sensible to implement something correct here.

Differential Revision: https://reviews.llvm.org/D46182


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332617 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-17 15:51:37 +00:00
Simon Pilgrim fdf32950c6 [X86][BtVer2] ADC/SBB take 2cy on an ALU pipe, not 1cy like ADD/SUB
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332616 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-17 15:43:23 +00:00
Simon Pilgrim 87225e582e [X86] Split WriteADC/WriteADCRMW scheduler classes
For integer ALU instructions taking eflags as an input (ADC/SBB/ADCX/ADOX)




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332605 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-17 12:43:42 +00:00
Sanjay Patel 6e244de1d7 [Thumb2] fix typo in test from r332548
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332569 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-17 03:24:25 +00:00
Stanislav Mekhanoshin 31b4f49b9f [AMDGPU] Move lsr test. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332562 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-17 01:30:51 +00:00
Sanjay Patel 309c9c43a7 [Hexagon] preserve test intent by removing undef
We need to clean up the DAG floating-point undef logic.
This process is similar to how we handled integer undef
logic in D43141.

And as we did there, I'm trying to reduce the patch by
changing tests that would probably become meaningless
once we correct FP undef folding.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332550 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-16 22:49:08 +00:00
Sanjay Patel fa475c558d [PowerPC] preserve test intent by removing undef
We need to clean up the DAG floating-point undef logic.
This process is similar to how we handled integer undef
logic in D43141.

And as we did there, I'm trying to reduce the patch by
changing tests that would probably become meaningless
once we correct FP undef folding.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332549 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-16 22:48:48 +00:00
Sanjay Patel 9658229e84 [Thumb] preserve test intent by removing undef
We need to clean up the DAG floating-point undef logic.
This process is similar to how we handled integer undef
logic in D43141.

And as we did there, I'm trying to reduce the patch by
changing tests that would probably become meaningless
once we correct FP undef folding.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332548 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-16 22:47:51 +00:00
Sanjay Patel 1aa48506b9 [Thumb] preserve test intent by removing undef
We need to clean up the DAG floating-point undef logic.
This process is similar to how we handled integer undef
logic in D43141.

And as we did there, I'm trying to reduce the patch by
changing tests that would probably become meaningless
once we correct FP undef folding.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332547 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-16 22:47:42 +00:00
Simon Pilgrim 34b5ae7518 [X86] Update SNB/generic scheduler tests missed from rL332536
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332540 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-16 22:24:22 +00:00
Sanjay Patel 9be09777af [ARM] preserve test intent by removing undef
We need to clean up the DAG floating-point undef logic.
This process is similar to how we handled integer undef
logic in D43141.

And as we did there, I'm trying to reduce the patch by
changing tests that would probably become meaningless
once we correct FP undef folding.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332539 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-16 22:20:33 +00:00
Sanjay Patel 9b35a3acde [ARM] preserve test intent by removing undef
We need to clean up the DAG floating-point undef logic.
This process is similar to how we handled integer undef
logic in D43141.

And as we did there, I'm trying to reduce the patch by
changing tests that would probably become meaningless
once we correct FP undef folding.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332538 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-16 22:20:26 +00:00
Sanjay Patel 5cb89e921d [ARM] preserve test intent by removing undef
We need to clean up the DAG floating-point undef logic.
This process is similar to how we handled integer undef
logic in D43141.

And as we did there, I'm trying to reduce the patch by
changing tests that would probably become meaningless
once we correct FP undef folding.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332537 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-16 22:20:11 +00:00
Sanjay Patel 8aecd6a7a6 [AArch64] preserve test intent by removing undef
We need to clean up the DAG floating-point undef logic.
This process is similar to how we handled integer undef
logic in D43141.

And as we did there, I'm trying to reduce the patch by
changing tests that would probably become meaningless
once we correct FP undef folding.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332534 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-16 21:57:57 +00:00
Sanjay Patel f57d10b7e5 [ARM] preserve test intent by removing undef
We need to clean up the DAG floating-point undef logic.
This process is similar to how we handled integer undef
logic in D43141.

And as we did there, I'm trying to reduce the patch by
changing tests that would probably become meaningless
once we correct FP undef folding.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332533 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-16 21:57:19 +00:00
Sanjay Patel 398f674fff [ARM] preserve test intent by removing undef
We need to clean up the DAG floating-point undef logic.
This process is similar to how we handled integer undef
logic in D43141.

And as we did there, I'm trying to reduce the patch by
changing tests that would probably become meaningless
once we correct FP undef folding.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332532 91177308-0d34-0410-b5e6-96231b3b80d8
2018-05-16 21:57:00 +00:00