165733 Commits

Author SHA1 Message Date
Nekotekina
95e7c217de X86: disable K-masks for AVX512BW+VL
Their usage often generates code that is ineffective on SKX.
Use conservative approach for xmm/ymm byte/word vectors.
continuous-linux-continuous-linux-continuous-linux-continuous-linux-continuous-linux-master continuous-linux-continuous-linux-continuous-linux-continuous-linux-master continuous-linux-continuous-linux-continuous-linux-master continuous-linux-continuous-linux-master continuous-linux-continuous-master continuous-master
2018-06-19 22:54:24 +03:00
Nekotekina
bf766f3aaf X86: optimize VSELECT for v16i8 with shl + sign bit test 2018-06-19 22:34:57 +03:00
Nekotekina
e114ebcddb X86: change v64i8 sar by 7
Use ADDUS (add with unsigned saturation)
addus(0, 0) = 0
addus(0x80, 0x80) = 0xff
2018-06-19 22:18:37 +03:00
Nekotekina
6cac8565a9 X86: combine AND+OR to VPTERNLOG 2018-06-19 22:15:33 +03:00
Nekotekina
339a277566 X86: detect AVG (alternative pattern)
Pattern doesn't use zero/sign extensions.
Also handle signed and signed-unsigned cases.
2018-06-19 22:15:33 +03:00
Nekotekina
edf822875b X86: combine inversion of VPTERNLOG 2018-06-19 22:15:33 +03:00
Nekotekina
09e968fc41 X86: detect patterns for saturation arithmetic
Includes ADDUS, ADDS, SUBUS, SUBS
Patterns use carry/overflow calculation in sign bit
Also combine some related logic into VPTERNLOG
2018-06-19 22:15:28 +03:00
Nekotekina
b76dd412cb X86: LowerShift: new algorithm for vector-vector shifts
Emit pair of shifts of double size if possible
2018-06-19 22:11:46 +03:00
Nekotekina
866da2bdb7 X86: Fix/workaround Small Code Model for JIT
Force RIP-relative jump tables and global values
Force RIP-relative all zeros / all ones constants
These things were causing crashes due to use of absolute addressing
2018-06-19 22:11:46 +03:00
Nekotekina
22ec62f016 Appveyor + Travis 2018-06-19 22:10:23 +03:00
Krzysztof Parzyszek
c0ac3859b1 [Hexagon] Fix the value of HexagonII::TypeCVI_FIRST
This value is the first vector instruction type in numerical order. The
previous value was incorrect, leaving TypeCVI_GATHER outside of the range
for vector instructions. This caused vector .new instructions to be
incorrectly encoded in the presence of gather.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335065 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-19 18:09:54 +00:00
Craig Topper
fbe156db3c [X86] Initialize FMA3Info directly in its constructor instead of relying on std::call_once
FMA3Info only exists as a managed static. As far as I know the ManagedStatic construction proccess is thread safe. It doesn't look like we ever access the ManagedStatic object without immediately doing a query on it that would require the map to be populated. So I don't think we're ever deferring the calculation of the tables from the construction of the object.

So I think we should be able to just populate the FMA3Info map directly in the constructor and get rid of all of the initGroupsOnce stuff.

Differential Revision: https://reviews.llvm.org/D48194

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335064 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-19 18:06:52 +00:00
Craig Topper
54edf4671d [X86] Don't fold unaligned loads into SSE ROUNDPS/ROUNDPD for ceil/floor/nearbyint/rint/trunc.
Incorrect patterns were added in r334460. This changes them to check alignment properly for SSE.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335062 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-19 17:51:42 +00:00
Krzysztof Parzyszek
3e9f1c2ce4 [Hexagon] Enforce restrictions on packetizing cache instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335061 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-19 17:26:20 +00:00
Saleem Abdulrasool
b07f54afdc docs: document CodeView directives
Add documentation for assembler directives added to support CodeView
emission.

Patch by Ellis Hoag!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335058 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-19 16:47:31 +00:00
Simon Dardis
9331b2fae1 [mips] Mark microMIPS64 as being unsupported.
There are no provided instruction definitions for this architecture.

Reviewers: smaksimovic, atanasyan, abeserminji

Differential Revision: https://reviews.llvm.org/D48320


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335057 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-19 16:05:44 +00:00
Simon Dardis
58b1f43714 [mips] Fix the predicates of some aliases
Previously, some aliases were marked as not being available for microMIPS32R6,
but this was overridden at the top level.

Reviewers: atanasyan, abeserminji, smaksimovic

Differential Revision: https://reviews.llvm.org/D48321


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335053 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-19 15:25:01 +00:00
Simon Pilgrim
4c0259dd2e [SLPVectorizer] Remove default OperandValueKind arguments from getArithmeticInstrCost calls (NFC)
The getArithmeticInstrCost calls for shuffle vectors entry costs specify TargetTransformInfo::OperandValueKind arguments, but are just using the method's default values. This seems to be a copy + paste issue and doesn't affect the costs in anyway. The TargetTransformInfo::OperandValueProperties default arguments are already not being used.

Noticed while working on D47985.

Differential Revision: https://reviews.llvm.org/D48008

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335045 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-19 13:40:00 +00:00
Strahinja Petrovic
96f8f2ad39 [PowerPC] Fix label address calculation for ppc32
This patch fixes calculating address of label on ppc32 (for -fPIC).

Differential Revision: https://reviews.llvm.org/D46582


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335043 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-19 13:07:40 +00:00
Roman Lebedev
ba6893f382 llvm-exegesis: mark ~ExegesisTarget() as virtual. Fixes build.
/build/llvm/tools/llvm-exegesis/lib/X86/../Target.h:32:3: error: 'exegesis::ExegesisTarget' has virtual functions but non-virtual destructor [-Werror,-Wnon-virtual-dtor]
  ~ExegesisTarget();
  ^
/build/llvm/tools/llvm-exegesis/lib/X86/Target.cpp:15:7: error: 'exegesis::(anonymous namespace)::ExegesisX86Target' has virtual functions but non-virtual destructor [-Werror,-Wnon-virtual-dtor]
class ExegesisX86Target : public ExegesisTarget {
      ^

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335042 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-19 11:58:10 +00:00
Clement Courbet
41d0646d59 Re-land r335038 "[llvm-exegesis] A mechanism to add target-specific functionality.""
Fix typo: LLVM_NATIVE_ARCH -> LLVM_EXEGESIS_NATIVE_ARCH.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335041 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-19 11:28:59 +00:00
Clement Courbet
0dae1a0252 Revert r335038 "[llvm-exegesis] A mechanism to add target-specific functionality."
Breaks buildbots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335040 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-19 10:54:12 +00:00
Mikhail Dvoretckii
53ba989b54 [InstCombine] Replacing X86-specific rounding intrinsics with generic floor-ceil
This patch replaces calls to X86-specific intrinsics with floor-ceil semantics
with calls to target-independent @llvm.floor.* and @llvm.ceil.* intrinsics. This
doesn't affect the resulting machine code, as those intrinsics are lowered to
the same instructions, but exposes these specific rounding cases to generic
optimizations.

Differential Revision: https://reviews.llvm.org/D48067


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335039 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-19 10:49:12 +00:00
Clement Courbet
fdc767cc01 [llvm-exegesis] A mechanism to add target-specific functionality.
Summary: This is a step towards implementing memory operands and X87.

Reviewers: gchatelet

Subscribers: mgorny, tschuett, llvm-commits

Differential Revision: https://reviews.llvm.org/D48210

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335038 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-19 10:39:50 +00:00
Mikhail Dvoretckii
be59eb33a0 [X86] VRNDSCALE* folding from masked and scalar ffloor and fceil patterns
This patch handles back-end folding of generic patterns created by lowering the
X86 rounding intrinsics to native IR in cases where the instruction isn't a
straightforward packed values rounding operation, but a masked operation or a
scalar operation.

Differential Revision: https://reviews.llvm.org/D45203


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335037 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-19 10:37:52 +00:00
David Green
d6cd67b722 [LoopSimplifyCFG] Invalidate SCEV in LoopSimplifyCFG
LoopSimplifyCFG, being a loop pass, needs to preserve scalar
evolution. This invalidates SE for the loops altered during
block merging.

Differential Revision: https://reviews.llvm.org/D48258



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335036 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-19 09:43:36 +00:00
Roman Lebedev
00258393d4 [MCA][NFC] Add generic XOP resource tests
Summary:
Based on
* [[ https://support.amd.com/TechDocs/43479.pdf | AMD64 Architecture Programmer’s Manual Volume 6: 128-Bit and 256-Bit XOP and FMA4 Instructions ]],
* [[ https://support.amd.com/TechDocs/24594.pdf | AMD64 Architecture Programmer’s Manual Volume 3: General-Purpose and System Instructions]],
* https://en.wikipedia.org/wiki/XOP_instruction_set

Appears to be only supported in AMD's 15h generation, so only in b**d**ver[1-4],
for which currently llvm has no scheduling profiles.

Reviewers: RKSimon, craig.topper, andreadb, spatel

Reviewed By: RKSimon

Subscribers: gbedwell, llvm-commits

Differential Revision: https://reviews.llvm.org/D48264

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335034 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-19 09:21:27 +00:00
Roman Lebedev
857083aa70 [MCA][NFC] Add generic TBM resource tests
Summary:
Based on https://support.amd.com/TechDocs/24594.pdf,
https://en.wikipedia.org/wiki/Bit_Manipulation_Instruction_Sets#TBM_(Trailing_Bit_Manipulation)

Appears to be only supported in AMD's 15h generation, so only in b**d**ver[1-4],
for which currently llvm has no scheduling profiles.

Reviewers: RKSimon, craig.topper, simark, andreadb

Reviewed By: RKSimon

Subscribers: gbedwell, llvm-commits

Differential Revision: https://reviews.llvm.org/D48252

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335033 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-19 09:21:22 +00:00
Simon Pilgrim
eb242d5190 [SLPVectorizer] Pull out AltOpcode determination from reorderAltShuffleOperands.
Minor step towards making the alternate opcode system work with a wider range of opcode pairs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335032 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-19 09:16:06 +00:00
Bjorn Pettersson
339ffa4450 Remove valueCoversEntireFragment asserts in ConvertDebugDeclareToDebugValue
This is a fixup for r334830 causing problems in polly-aosp buildbot.

Focus in r334830 was to fix a problem seen with
ConvertDebugDeclareToDebugValue involving store instructions.
It also added some asserts to find out of similar problems
existed for the ConvertDebugDeclareToDebugValue functions
involving load and phi instructions. One of those asserts seems
to blow in the polly-aosp buildbot, so I'll revert the asserts
while debugging.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335031 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-19 08:41:34 +00:00
Adrian Kuegel
96f21df448 Add a factory method to ConstantDataArray that allows to pass in the data as StringRef
This simplifies the case if we already have access to the raw data that we need to store in a ConstantDataArray.
The new factor method can also be reused for implementing the factory method that gets the data as ArrayRef.

Differential Revision: https://reviews.llvm.org/D47706



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335028 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-19 08:12:28 +00:00
Florian Hahn
6517111aa9 [LoopInterchange] Move PHI handling to adjustLoopBranches.
This patch moves the logic to handle reduction PHI nodes to the end of
adjustLoopBranches. Reduction PHI nodes in the outer loop header can be
moved to the inner loop header and reduction PHI nodes from the inner loop
header can be moved to the outer loop header. In the latter situation,
we have to deal with 1 kind of PHI nodes:

    PHI nodes that are part of inner loop-only reductions.

We can replace the PHI node with the value coming from outside
the inner loop.

Reviewers: mcrosier, efriedma, karthikthecool

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D46198


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335027 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-19 08:03:24 +00:00
Mikhail Dvoretckii
f356e3e089 Test commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335026 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-19 07:55:10 +00:00
QingShan Zhang
21cf43199f If the arch is P9, we will select the DFLOADf32/DFLOADf64 pseudo instruction when we are loading a floating,
and expand it post RA basing on the register pressure. However, we miss to do the add-imm peephole for these pseudo instruction.

Differential Revision: https://reviews.llvm.org/D47568
Reviewed By: Nemanjai



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335024 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-19 06:54:51 +00:00
Roger Ferrer Ibanez
ef2db721db [RISCV] Add tests for overflow intrinsics
This is using the existing codegen so we can see the change once we custom
lower ISD::{U,S}{ADD,SUB}O nodes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335023 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-19 06:45:47 +00:00
Max Kazantsev
634dad1840 [SimplifyIndVars] Eliminate redundant truncs
This patch adds logic to deal with the following constructions:

  %iv = phi i64 ...
  %trunc = trunc i64 %iv to i32
  %cmp = icmp <pred> i32 %trunc, %invariant

Replacing it with
  %iv = phi i64 ...
  %cmp = icmp <pred> i64 %iv, sext/zext(%invariant)

In case if it is legal. Specifically, if `%iv` has signed comparison users, it is
required that `sext(trunc(%iv)) == %iv`, and if it has unsigned comparison
uses then we require `zext(trunc(%iv)) == %iv`. The current implementation
bails if `%trunc` has other uses than `icmp`, but in theory we can handle more
cases here (e.g. if the user of trunc is bitcast).

Differential Revision: https://reviews.llvm.org/D47928
Reviewed By: reames


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335020 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-19 04:48:34 +00:00
Craig Topper
e5b799ba09 [X86] Add the ability to force an EVEX2VEX mapping table entry from the .td files. Remove remaining manual table entries from the tablegen emitter.
This adds an EVEX2VEXOverride string to the X86 instruction class in X86InstrFormats.td. If this field is set it will add manual entry in the EVEX->VEX tables that doesn't check the encoding information.

Then use this mechanism to map VMOVDU/A8/16, 128-bit VALIGN, and VPSHUFF/I instructions to VEX instructions.

Finally, remove the manual table from the emitter.

This has the bonus of fully sorting the autogenerated EVEX->VEX tables by their EVEX instruction enum value. We may be able to use this to do a binary search for the conversion and get rid of the need to create a DenseMap.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335018 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-19 04:24:44 +00:00
Craig Topper
023b407c11 [X86] Add a new VEX_WPrefix encoding to tag EVEX instruction that have VEX.W==1, but can be converted to their VEX equivalent that uses VEX.W==0.
EVEX makes heavy use of the VEX.W bit to indicate 64-bit element vs 32-bit elements. Many of the VEX instructions were split into 2 versions with different masking granularity.

The EVEX->VEX table generate can collapse the two versions if the VEX version uses is tagged as VEX_WIG. But if the VEX version is instead marked VEX.W==0 we can't combine them because we don't know if there is also a VEX version with VEX.W==1.

This patch adds a new VEX_W1X tag that indicates the EVEX instruction encodes with VEX.W==1, but is safe to convert to a VEX instruction with VEX.W==0.

This allows us to remove a bunch of manual EVEX->VEX table entries. We may want to look into splitting up the VEX_WPrefix field which would simplify the disassembler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335017 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-19 04:24:42 +00:00
Sanjoy Das
1a6eaebd1c Revert "[SCEV] Add nuw/nsw to mul ops in StrengthenNoWrapFlags"
This reverts r334428.  It incorrectly marks some multiplications as nuw.  Tim
Shen is working on a proper fix.

Original commit message:

[SCEV] Add nuw/nsw to mul ops in StrengthenNoWrapFlags where safe.

Summary:
Previously we would add them for adds, but not multiplies.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335016 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-19 04:09:44 +00:00
Craig Topper
fe7e53ea94 [X86] Simplify the TSFlags checking code in EvexToVexInstPass. NFCI
The code was previously checking the L2 and L flag on 3 separate lines, treating the combination as an encoding. Instead its better to think of the L2 bit as being something that can't be done with VEX and early returning. Then we just need to check the L bit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335015 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-19 03:17:46 +00:00
Heejin Ahn
ce64173017 [WebAssembly] Remove an extra ';' at the end of a namespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335008 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-19 01:23:14 +00:00
Heejin Ahn
dba082adc8 [WebAssembly] Add more utility functions
Summary:
Added more utility functions that will be used in EH-related passes Also
changed `LoopBottom` function to `getBottom` and uses templates to be
able to handle other classes as well, which will be used in CFGSort
later.

Reviewers: dschuff

Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D48262

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335006 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-19 00:32:03 +00:00
Heejin Ahn
c430c83029 [WebAssembly] Add WasmEHFuncInfo for unwind destination information
Summary:
Add WasmEHFuncInfo and routines to calculate and fill in this struct to
keep track of unwind destination information. This will be used in
other EH related passes.

Reviewers: dschuff

Subscribers: sbc100, jgravelle-google, sunfish, chrib, llvm-commits

Differential Revision: https://reviews.llvm.org/D48263

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335005 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-19 00:26:39 +00:00
Eli Friedman
f6172a9f68 [ARM] Thumb2 constant cmp testcases.
Shows some missed optimizations for the -7929856 and -2166 testcases.
-7929856 is due to a bug in ARMTargetLowering::getARMCmp, I think;
the -2166 case is a missing pattern.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335004 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-19 00:14:10 +00:00
Eli Friedman
9ba2448193 [ARM] Testcase for Thumb1 cmp with constants.
Even if a comparison isn't legal, we should try to prefer constants
which can be materialized with a two-instruction sequence. (Thinking
about it a bit more, there might be some more clever sequence we could
generate for certain comparisons invoving powers of two, but I'm not
sure exactly what that would look like.)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335003 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-19 00:12:13 +00:00
Eli Friedman
959e5f8164 [ARM] Add Thumb1 coverage for cmn testcases.
There's a missed optimization for immediates: we can save two
instructions by using adds instead of movs+mvns+cmp.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335002 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-19 00:09:44 +00:00
Eli Friedman
f5b3e11164 [ARM] Testcase for missed optimization for masking.
When the result of masking is truncated to i16, we should try to use
"bic" instead of "and".



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335001 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-19 00:08:32 +00:00
Eli Friedman
7d6421e0ed [ARM] Testcase for missed optimization with i16 compare.
The result looks weird because the DAG actually has an explicit
shift; I haven't figured out why, exactly.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335000 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-19 00:07:30 +00:00
Derek Schuff
f135420eab [WebAssembly] Fixed disassembler unit test failure.
Summary: A recent commit forgot to update the unit tests.

Differential Revision: https://reviews.llvm.org/D48304

Patch by Wouter Van Oortmerssen

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334999 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-19 00:02:34 +00:00
Heejin Ahn
f1fc1ae9b7 [WebAssembly] Make rethrow instruction take a target BB argument
Summary:
This patch changes the rethrow instruction to take a BB argument in LLVM
backend, like `br` and `br_if`s. This BB is a target catch BB the
rethrow instruction unwinds to. This BB argument will be converted to an
relative depth immediate at the end of CFGStackify pass, as in the same
way of branches.

RETHROW_TO_CALLER is a codegen-only instruction that should be used when
a rethrow instruction does not have an unwind destination BB, i.e., it
should rethrow to its caller function.

Reviewers: dschuff

Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D48260

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334998 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-18 23:54:29 +00:00