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09e460662a
llvm/lib/Target/ARM
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Chris Lattner 09e460662a Completely eliminate def&use operands. Now a register operand is EITHER a 
def operand or a use operand.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30109 91177308-0d34-0410-b5e6-96231b3b80d8
2006-09-05 02:31:13 +00:00
..
.cvsignore Ignore generated files 2006-05-27 01:23:30 +00:00
ARM.h add more condition codes 2006-09-02 20:24:25 +00:00
ARM.td getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd. 2006-05-18 00:12:58 +00:00
ARMAsmPrinter.cpp use @ for comments 2006-08-25 17:55:16 +00:00
ARMFrameInfo.h use @ for comments 2006-08-25 17:55:16 +00:00
ARMInstrInfo.cpp change the addressing mode of the str instruction to reg+imm 2006-08-08 20:35:03 +00:00
ARMInstrInfo.h change the addressing mode of the str instruction to reg+imm 2006-08-08 20:35:03 +00:00
ARMInstrInfo.td add the "eq" condition code 2006-08-24 17:19:08 +00:00
ARMISelDAGToDAG.cpp add support for returning 64bit values 2006-09-04 19:05:01 +00:00
ARMRegisterInfo.cpp Completely eliminate def&use operands. Now a register operand is EITHER a 2006-09-05 02:31:13 +00:00
ARMRegisterInfo.h getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd. 2006-05-18 00:12:58 +00:00
ARMRegisterInfo.td Constify some methods. Patch provided by Anton Vayvod, thanks! 2006-08-17 22:00:08 +00:00
ARMTargetMachine.cpp Completely rearchitect the interface between targets and the pass manager. 2006-09-04 04:14:57 +00:00
ARMTargetMachine.h Completely rearchitect the interface between targets and the pass manager. 2006-09-04 04:14:57 +00:00
Makefile
README.txt add a README.txt 2006-08-22 12:22:46 +00:00

README.txt 

//===---------------------------------------------------------------------===//
// Random ideas for the ARM backend.
//===---------------------------------------------------------------------===//

Consider implementing a select with two conditional moves:

cmp x, y
moveq dst, a
movne dst, b