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3767f18861be3f8ad2b2f3e8caad022946debc6e
llvm/test/CodeGen/RISCV
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Shiva Chen 3767f18861 [RISCV] Avoid generating AssertZext for LP64 ABI when lowering floating LibCall 
The patch fixed the issue that RV64 didn't clear the upper bits
when return complex floating value with lp64 ABI.

float _Complex
complex_add(float _Complex a, float _Complex b)
{
   return a + b;
}

RealResult = zero_extend(RealA + RealB)
ImageResult = ImageA + ImageB
Return (RealResult | (ImageResult << 32))

The patch introduces shouldExtendTypeInLibCall target hook to suppress
the AssertZext generation when lowering floating LibCall.

Thanks to Eli's comments from the Bugzilla
https://bugs.llvm.org/show_bug.cgi?id=42820

Differential Revision: https://reviews.llvm.org/D65497

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370275 91177308-0d34-0410-b5e6-96231b3b80d8
2019-08-28 23:40:37 +00:00
..
GlobalISel
[RISCV GlobalISel] Adding initial GlobalISel infrastructure
2019-08-20 22:53:24 +00:00
add-before-shl.ll
[RISCV] Fix ICE in isDesirableToCommuteWithShift
2019-08-12 13:51:00 +00:00
addc-adde-sube-subc.ll
[RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV
2019-05-23 12:43:13 +00:00
addcarry.ll
[RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV
2019-05-23 12:43:13 +00:00
align.ll
[RISCV] Change function alignment to 4 bytes, and 2 bytes for RVC
2018-04-12 11:30:59 +00:00
alloca.ll
[RISCV] Expand function call to "call" pseudoinstruction
2018-04-25 14:19:12 +00:00
alu8.ll
[RISCV] Introduce codegen patterns for instructions introduced in RV64I
2018-11-30 09:38:44 +00:00
alu16.ll
[RISCV] Introduce codegen patterns for instructions introduced in RV64I
2018-11-30 09:38:44 +00:00
alu32.ll
[RISCV] Custom legalize i32 operations for RV64 to reduce signed extensions
2019-08-06 00:24:00 +00:00
alu64.ll
[RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV
2019-05-23 12:43:13 +00:00
analyze-branch.ll
[RISCV] Expand function call to "call" pseudoinstruction
2018-04-25 14:19:12 +00:00
arith-with-overflow.ll
[RISCV] Add tests for overflow intrinsics
2018-06-19 06:45:47 +00:00
atomic-cmpxchg-flag.ll
[RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV
2019-05-23 12:43:13 +00:00
atomic-cmpxchg.ll
[RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV
2019-05-16 13:56:23 +00:00
atomic-fence.ll
[RISCV][NFC] Add CHECK lines for atomic operations on RV64I
2019-01-11 19:46:48 +00:00
atomic-load-store.ll
[RISCV] Add codegen support for RV64A
2019-01-17 10:04:39 +00:00
atomic-rmw.ll
[MBP] Disable aggressive loop rotate in plain mode
2019-08-22 16:21:32 +00:00
bare-select.ll
[RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV
2019-05-23 12:43:13 +00:00
blockaddress.ll
[RISCV] Peephole optimisation for load/store of global values or constant addresses
2018-03-19 11:54:28 +00:00
branch-relaxation.ll
[RISCV] Match GNU tools canonical JALR and add aliases
2019-07-16 04:56:43 +00:00
branch.ll
[RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV
2019-05-23 12:43:13 +00:00
bswap-ctlz-cttz-ctpop.ll
[RISCV] Only mark fp as reserved if the function has a dedicated frame pointer
2019-03-13 16:33:45 +00:00
byval.ll
[RISCV] Separate base from offset in lowerGlobalAddress
2018-05-17 18:14:53 +00:00
callee-saved-fpr32s.ll
[RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV
2019-05-16 13:56:23 +00:00
callee-saved-fpr64s.ll
[RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV
2019-05-16 13:56:23 +00:00
callee-saved-gprs.ll
[RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV
2019-05-16 13:56:23 +00:00
calling-conv-ilp32-ilp32f-common.ll
[RISCV] Add codegen support for ilp32f, ilp32d, lp64f, and lp64d ("hard float") ABIs
2019-03-30 17:59:30 +00:00
calling-conv-ilp32-ilp32f-ilp32d-common.ll
[RISCV] Add codegen support for ilp32f, ilp32d, lp64f, and lp64d ("hard float") ABIs
2019-03-30 17:59:30 +00:00
calling-conv-ilp32.ll
[RISCV] Only mark fp as reserved if the function has a dedicated frame pointer
2019-03-13 16:33:45 +00:00
calling-conv-ilp32d.ll
[RISCV] Add codegen support for ilp32f, ilp32d, lp64f, and lp64d ("hard float") ABIs
2019-03-30 17:59:30 +00:00
calling-conv-ilp32f-ilp32d-common.ll
[RISCV] Add codegen support for ilp32f, ilp32d, lp64f, and lp64d ("hard float") ABIs
2019-03-30 17:59:30 +00:00
calling-conv-lp64-lp64f-common.ll
[RISCV] Add codegen support for ilp32f, ilp32d, lp64f, and lp64d ("hard float") ABIs
2019-03-30 17:59:30 +00:00
calling-conv-lp64-lp64f-lp64d-common.ll
[RISCV] Custom legalize i32 operations for RV64 to reduce signed extensions
2019-08-06 00:24:00 +00:00
calling-conv-lp64.ll
[RISCV] Avoid generating AssertZext for LP64 ABI when lowering floating LibCall
2019-08-28 23:40:37 +00:00
calling-conv-rv32f-ilp32.ll
Reapply: [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI
2019-01-25 20:22:49 +00:00
calling-conv-sext-zext.ll
[RISCV] Expand function call to "call" pseudoinstruction
2018-04-25 14:19:12 +00:00
calls.ll
[RISCV] Lower calls through PLT
2019-06-18 14:29:45 +00:00
codemodel-lowering.ll
[RISCV] Implement adding a displacement to a BlockAddress
2019-04-05 08:40:57 +00:00
compress-inline-asm.ll
[RISCV] Tablegen-driven Instruction Compression.
2018-04-06 21:07:05 +00:00
compress.ll
[RISCV] Add test changes missed from rL330293
2018-04-18 20:36:12 +00:00
disable-tail-calls.ll
[RISCV] Lower the tail pseudoinstruction
2018-05-23 22:44:08 +00:00
div.ll
[RISCV] Introduce codegen patterns for RV64M-only instructions
2019-01-12 07:43:06 +00:00
double-arith.ll
[RISCV] Implement RV64D codegen
2019-02-01 03:53:30 +00:00
double-bitmanip-dagcombines.ll
[RISCV] Implement RV64D codegen
2019-02-01 03:53:30 +00:00
double-br-fcmp.ll
[RISCV] Add seto pattern expansion
2019-04-01 09:54:14 +00:00
double-calling-conv.ll
[RISCV] Add DAGCombine for (SplitF64 (ConstantFP x))
2019-03-30 09:15:47 +00:00
double-convert.ll
[RISCV] Implement RV64D codegen
2019-02-01 03:53:30 +00:00
double-fcmp.ll
[RISCV] Add seto pattern expansion
2019-04-01 09:54:14 +00:00
double-frem.ll
[RISCV] Mark FREM as Expand
2018-11-15 14:46:11 +00:00
double-imm.ll
[RISCV] Add DAGCombine for (SplitF64 (ConstantFP x))
2019-03-30 09:15:47 +00:00
double-intrinsics.ll
[RISCV] Only mark fp as reserved if the function has a dedicated frame pointer
2019-03-13 16:33:45 +00:00
double-mem.ll
[RISCV] Only mark fp as reserved if the function has a dedicated frame pointer
2019-03-13 16:33:45 +00:00
double-previous-failure.ll
[RISCV] Add DAGCombine for (SplitF64 (ConstantFP x))
2019-03-30 09:15:47 +00:00
double-select-fcmp.ll
[RISCV] Add seto pattern expansion
2019-04-01 09:54:14 +00:00
double-stack-spill-restore.ll
[RISCV] Implement RV64D codegen
2019-02-01 03:53:30 +00:00
dwarf-eh.ll
[RISCV][NFC] Remove outdated TODO from test/CodeGen/RISCV/dwarf-eh.ll
2019-07-17 14:04:48 +00:00
exception-pointer-register.ll
[RISCV] Specify registers used in DWARF exception handling
2019-07-08 09:16:47 +00:00
fixups-diff.ll
[RISCV][MC] Don't fold symbol differences if requiresDiffExpressionRelocations is true
2018-08-16 11:26:37 +00:00
fixups-relax-diff.ll
[DebugInfo] Generate fixups as emitting DWARF .debug_frame/.eh_frame.
2019-07-19 02:03:34 +00:00
float-arith.ll
[RISCV] Add RV64F codegen support
2019-01-31 22:48:38 +00:00
float-bit-preserving-dagcombines.ll
[RISCV] Support Bit-Preserving FP in F/D Extensions
2019-06-07 12:20:14 +00:00
float-bitmanip-dagcombines.ll
[RISCV] Add RV64F codegen support
2019-01-31 22:48:38 +00:00
float-br-fcmp.ll
[RISCV] Add seto pattern expansion
2019-04-01 09:54:14 +00:00
float-convert.ll
[RISCV] Add RV64F codegen support
2019-01-31 22:48:38 +00:00
float-fcmp.ll
[RISCV] Add seto pattern expansion
2019-04-01 09:54:14 +00:00
float-frem.ll
[RISCV] Mark FREM as Expand
2018-11-15 14:46:11 +00:00
float-imm.ll
[RISCV] Add RV64F codegen support
2019-01-31 22:48:38 +00:00
float-intrinsics.ll
[RISCV] Only mark fp as reserved if the function has a dedicated frame pointer
2019-03-13 16:33:45 +00:00
float-mem.ll
[RISCV] Only mark fp as reserved if the function has a dedicated frame pointer
2019-03-13 16:33:45 +00:00
float-select-fcmp.ll
[RISCV] Add seto pattern expansion
2019-04-01 09:54:14 +00:00
flt-rounds.ll
[SelectionDAG] Support result type promotion for FLT_ROUNDS_
2018-11-30 13:18:33 +00:00
fp128.ll
[RISCV] Avoid unnecessary XOR for seteq/setne 0
2018-11-09 14:47:36 +00:00
frame-info.ll
[RISCV] Add CFI directives for RISCV prologue/epilog.
2019-06-12 03:04:22 +00:00
frame.ll
Replace "no-frame-pointer-*" function attributes with "frame-pointer"
2019-01-14 10:55:55 +00:00
frameaddr-returnaddr.ll
[SelectionDAG] Support promotion of FRAMEADDR/RETURNADDR operands
2018-11-30 10:02:06 +00:00
get-setcc-result-type.ll
[RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV
2019-05-23 12:43:13 +00:00
hoist-global-addr-base.ll
[RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV
2019-05-23 12:43:13 +00:00
i32-icmp.ll
[RISCV] Improve codegen for icmp {ne,eq} with a constant
2019-03-26 12:55:00 +00:00
imm-cse.ll
[RISCV] Add RISCV-specific TargetTransformInfo
2019-06-21 13:36:09 +00:00
imm.ll
Reapply: [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI
2019-01-25 20:22:49 +00:00
indirectbr.ll
[RISCV] Match GNU tools canonical JALR and add aliases
2019-07-16 04:56:43 +00:00
init-array.ll
[IR] Disallow llvm.global_ctors and llvm.global_dtors of the 2-field form in textual format
2019-05-15 02:35:32 +00:00
inline-asm-abi-names.ll
[RISCV] Allow ABI Names in Inline Assembly Constraints
2019-08-08 14:59:16 +00:00
inline-asm-clobbers.ll
[RISCV] Add support for lowering floating point inlineasm clobbers
2019-07-31 09:07:21 +00:00
inline-asm-d-abi-names.ll
[RISCV] Allow ABI Names in Inline Assembly Constraints
2019-08-08 14:59:16 +00:00
inline-asm-d-constraint-f.ll
[RISCV] Allow ABI Names in Inline Assembly Constraints
2019-08-08 14:59:16 +00:00
inline-asm-f-abi-names.ll
[RISCV] Allow ABI Names in Inline Assembly Constraints
2019-08-08 14:59:16 +00:00
inline-asm-f-constraint-f.ll
[RISCV] Allow ABI Names in Inline Assembly Constraints
2019-08-08 14:59:16 +00:00
inline-asm-i-constraint-i1.ll
[TargetLowering] Extend bool args to inline-asm according to getBooleanType
2019-05-22 16:16:15 +00:00
inline-asm-invalid.ll
Emit diagnostic if an inline asm constraint requires an immediate
2019-08-03 05:52:47 +00:00
inline-asm.ll
[RISCV] Lower inline asm constraint A for RISC-V
2019-08-16 10:28:34 +00:00
interrupt-attr-args-error.ll
[RISCV] Add support for _interrupt attribute
2018-07-26 17:49:43 +00:00
interrupt-attr-invalid.ll
[RISCV] Add support for _interrupt attribute
2018-07-26 17:49:43 +00:00
interrupt-attr-nocall.ll
[RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV
2019-05-16 13:56:23 +00:00
interrupt-attr-ret-error.ll
[RISCV] Add support for _interrupt attribute
2018-07-26 17:49:43 +00:00
interrupt-attr.ll
[RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV
2019-05-16 13:56:23 +00:00
jumptable.ll
[RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV
2019-05-23 12:43:13 +00:00
large-stack.ll
[RISCV] Only mark fp as reserved if the function has a dedicated frame pointer
2019-03-13 16:33:45 +00:00
legalize-fneg.ll
[RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV
2019-05-23 12:43:13 +00:00
lit.local.cfg
[RISCV] Initial codegen support for ALU operations
2017-10-19 21:37:38 +00:00
lsr-legaladdimm.ll
[RISCV] Implement isLegalAddImmediate
2018-04-26 13:00:37 +00:00
mattr-invalid-combination.ll
[RISCV] Add basic RV32E definitions and MC layer support
2019-03-22 11:21:40 +00:00
mem64.ll
[RISCV] Introduce codegen patterns for instructions introduced in RV64I
2018-11-30 09:38:44 +00:00
mem.ll
[RISCV] Separate base from offset in lowerGlobalAddress
2018-05-17 18:14:53 +00:00
mul.ll
[RISCV] Introduce codegen patterns for RV64M-only instructions
2019-01-12 07:43:06 +00:00
musttail-call.ll
[RISCV] Lower the tail pseudoinstruction
2018-05-23 22:44:08 +00:00
option-norelax.ll
[RISCV] Support .option relax and .option norelax
2018-11-12 14:25:07 +00:00
option-norvc.ll
[RISCV] Support .option rvc and norvc assembler directives
2018-05-11 17:30:28 +00:00
option-relax.ll
[RISCV] Support .option relax and .option norelax
2018-11-12 14:25:07 +00:00
option-rvc.ll
[RISCV] Match GNU tools canonical JALR and add aliases
2019-07-16 04:56:43 +00:00
pic-models.ll
[RISCV] Add lowering of addressing sequences for PIC
2019-06-11 12:57:47 +00:00
pr40333.ll
[RISCV] Custom-legalise 32-bit variable shifts on RV64
2019-01-25 05:04:00 +00:00
prefetch.ll
[SelectionDAG] Support promotion of PREFETCH operands
2018-11-30 10:06:31 +00:00
readcyclecounter.ll
[RISCV] Support @llvm.readcyclecounter() Intrinsic
2019-07-05 12:35:21 +00:00
rem.ll
[RISCV] Introduce codegen patterns for RV64M-only instructions
2019-01-12 07:43:06 +00:00
remat.ll
[MBP] Disable aggressive loop rotate in plain mode
2019-08-22 16:21:32 +00:00
rotl-rotr.ll
[RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV
2019-05-23 12:43:13 +00:00
rv32e.ll
[RISCV] Add basic RV32E definitions and MC layer support
2019-03-22 11:21:40 +00:00
rv32i-rv64i-float-double.ll
[RISCV] Avoid generating AssertZext for LP64 ABI when lowering floating LibCall
2019-08-28 23:40:37 +00:00
rv64d-double-convert.ll
[RISCV] Implement RV64D codegen
2019-02-01 03:53:30 +00:00
rv64f-float-convert.ll
[RISCV] Add RV64F codegen support
2019-01-31 22:48:38 +00:00
rv64i-complex-float.ll
[RISCV] Avoid generating AssertZext for LP64 ABI when lowering floating LibCall
2019-08-28 23:40:37 +00:00
rv64i-exhaustive-w-insts.ll
[RISCV] Custom legalize i32 operations for RV64 to reduce signed extensions
2019-08-06 00:24:00 +00:00
rv64i-single-softfloat.ll
[RISCV] Avoid generating AssertZext for LP64 ABI when lowering floating LibCall
2019-08-28 23:40:37 +00:00
rv64i-tricky-shifts.ll
[RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV
2019-05-23 12:43:13 +00:00
rv64i-w-insts-legalization.ll
[RISCV] Custom legalize i32 operations for RV64 to reduce signed extensions
2019-08-06 00:24:00 +00:00
rv64m-exhaustive-w-insts.ll
[RISCV] Custom legalize i32 operations for RV64 to reduce signed extensions
2019-08-06 00:24:00 +00:00
rv64m-w-insts-legalization.ll
[RISCV] Custom legalize i32 operations for RV64 to reduce signed extensions
2019-08-06 00:24:00 +00:00
sdata-limit-0.ll
[RISCV] Put data smaller than eight bytes to small data section
2019-04-11 04:59:13 +00:00
sdata-limit-4.ll
[RISCV] Put data smaller than eight bytes to small data section
2019-04-11 04:59:13 +00:00
sdata-limit-8.ll
[RISCV] Put data smaller than eight bytes to small data section
2019-04-11 04:59:13 +00:00
sdata-local-sym.ll
[RISCV] Put data smaller than eight bytes to small data section
2019-04-11 04:59:13 +00:00
select-cc.ll
[RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV
2019-05-23 12:43:13 +00:00
select-optimize-multiple.ll
[RISCV] Custom legalize i32 operations for RV64 to reduce signed extensions
2019-08-06 00:24:00 +00:00
select-optimize-multiple.mir
[RISCV] Fix test after r363757
2019-06-19 03:18:48 +00:00
setcc-logic.ll
[RISCV] Update setcc-logic.ll codegen test
2019-03-26 15:41:45 +00:00
sext-zext-trunc.ll
[RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV
2019-05-23 12:43:13 +00:00
shift-masked-shamt.ll
[RISCV] Eliminate unnecessary masking of promoted shift amounts
2018-10-12 23:18:52 +00:00
shifts.ll
[RISCV] Custom lower SHL_PARTS, SRA_PARTS, SRL_PARTS
2019-04-16 14:38:32 +00:00
split-offsets.ll
[DAGCombiner] [CodeGenPrepare] More comprehensive GEP splitting
2019-06-17 10:54:12 +00:00
stack-realignment-unsupported.ll
[RISCV] Minimal stack realignment support
2019-08-08 14:40:54 +00:00
stack-realignment.ll
[RISCV] Minimal stack realignment support
2019-08-08 14:40:54 +00:00
tail-calls.ll
[RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV
2019-05-23 12:43:13 +00:00
target-abi-invalid.ll
[RISCV] Support -target-abi at the MC layer and for codegen
2019-03-09 09:28:06 +00:00
target-abi-valid.ll
[RISCV] Add codegen support for ilp32f, ilp32d, lp64f, and lp64d ("hard float") ABIs
2019-03-30 17:59:30 +00:00
tls-models.ll
[RISCV] Add lowering of global TLS addresses
2019-06-19 08:40:59 +00:00
umulo-128-legalisation-lowering.ll
[RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV
2019-05-16 13:56:23 +00:00
vararg.ll
[RISCV] Custom legalize i32 operations for RV64 to reduce signed extensions
2019-08-06 00:24:00 +00:00
wide-mem.ll
[RISCV] Separate base from offset in lowerGlobalAddress
2018-05-17 18:14:53 +00:00
zext-with-load-is-free.ll
[RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV
2019-05-23 12:43:13 +00:00