llvm/test/CodeGen at 3c28f29dff4becdab18c3ab0a26775a2a64b44f6 - llvm

RPCS3/llvm

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Mikhail Maltsev 3c28f29dff [ARM] Add a register class for GPR pairs without SP and use it. NFCI

Summary:
Currently Thumb2InstrInfo.cpp uses a register class which is
auto-generated by tablegen. Such approach is fragile because
auto-generated classes might change when other register classes are
added. For example, before https://reviews.llvm.org/D62667
we were using GPRPair_with_gsub_1_in_rGPRRegClass, but had to
change it to GPRPair_with_gsub_1_in_GPRwithAPSRnospRegClass
because the former class stopped being generated (this did not change
the functionality though).

This patch adds a register class consisting of even-odd GPR register
pairs from (R0, R1) to (R10, R11), which excludes (R12, SP) and uses
it in Thumb2InstrInfo.cpp instead of
GPRPair_with_gsub_1_in_GPRwithAPSRnospRegClass.

Reviewers: ostannard, simon_tatham, dmgreen, efriedma

Reviewed By: simon_tatham

Subscribers: kristof.beyls, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D69026

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@374990 91177308-0d34-0410-b5e6-96231b3b80d8

2019-10-16 10:40:57 +00:00

AArch64

[DebugInfo] Remove some users of DBG_VALUEs IsIndirect field

2019-10-15 10:46:24 +00:00

AMDGPU

[AMDGPU] Extend the SI Load/Store optimizer

2019-10-16 10:17:02 +00:00

ARC

[lit] Delete empty lines at the end of lit.local.cfg NFC

2019-06-17 09:51:07 +00:00

ARM

[ARM] Add a register class for GPR pairs without SP and use it. NFCI