llvm/lib/Target/Sparc
2014-02-07 07:34:49 +00:00
..
AsmParser [Sparc] Emit correct encoding for atomic instructions. Also, add support for parsing CAS instructions to test the CAS encoding. 2014-02-07 07:34:49 +00:00
Disassembler [Sparc] Replace (unsigned)-1 with ~OU as suggested by Reid Kleckner. 2014-01-12 04:34:31 +00:00
InstPrinter [Sparc] Use SparcMCExpr::VariantKind itself as MachineOperand's target flags. 2014-02-07 02:36:06 +00:00
MCTargetDesc [Sparc] Emit relocations for Thread Local Storage (TLS) when integrated assembler is used. 2014-02-07 05:54:20 +00:00
TargetInfo Prune redundant dependencies in LLVMBuild.txt. 2013-12-11 00:30:57 +00:00
CMakeLists.txt [Sparc] Use %r_disp32 for pc_rel entries in gcc_except_table and eh_frame. 2014-01-29 04:51:35 +00:00
DelaySlotFiller.cpp [Sparc] Bundle instruction with delay slow and its filler. Now, we can use -verify-machineinstrs with SPARC backend. 2014-01-11 19:38:03 +00:00
LLVMBuild.txt [Sparc] Add initial implementation of disassembler for sparc 2014-01-06 08:08:58 +00:00
Makefile [Sparc] Add initial implementation of disassembler for sparc 2014-01-06 08:08:58 +00:00
README.txt Sparc: No functionality change. Cleanup whitespaces, comment formatting etc., 2013-06-04 18:33:25 +00:00
Sparc.h [Sparc] Lower and MachineInstr to MC and print assembly using MCInstPrinter. 2013-12-26 01:49:59 +00:00
Sparc.td Only generate the popc instruction for SPARC CPUs that implement it. 2014-01-26 06:09:59 +00:00
SparcAsmPrinter.cpp [Sparc] Emit correct relocations for PIC code when integrated assembler is used. 2014-02-07 04:24:35 +00:00
SparcCallingConv.td The SPARCv9 ABI returns a float in %f0. 2014-01-12 04:13:17 +00:00
SparcCodeEmitter.cpp [Sparc] Use SparcMCExpr::VariantKind itself as MachineOperand's target flags. 2014-02-07 02:36:06 +00:00
SparcFrameLowering.cpp SparcFrameLowering.cpp: Prune 'DL' [-Wunused-variable] 2013-11-25 00:52:46 +00:00
SparcFrameLowering.h [Sparc] Emit large negative adjustments to SP/FP with sethi+xor instead of sethi+or. This generates correct code for both sparc32 and sparc64. 2013-11-24 20:23:25 +00:00
SparcInstr64Bit.td [Sparc] Emit correct encoding for atomic instructions. Also, add support for parsing CAS instructions to test the CAS encoding. 2014-02-07 07:34:49 +00:00
SparcInstrAliases.td [Sparc] Emit retl/ret instead of jmp instruction. It improves the readability of the assembly generated. 2014-01-10 02:55:27 +00:00
SparcInstrFormats.td [Sparc] Emit correct encoding for atomic instructions. Also, add support for parsing CAS instructions to test the CAS encoding. 2014-02-07 07:34:49 +00:00
SparcInstrInfo.cpp [SparcV9] Use correct register class (I64RegClass) to hold the address of _GLOBAL_OFFSET_TABLE_ in sparcv9. 2014-01-29 03:35:08 +00:00
SparcInstrInfo.h [weak vtables] Remove a bunch of weak vtables 2013-11-19 00:57:56 +00:00
SparcInstrInfo.td [Sparc] Emit correct encoding for atomic instructions. Also, add support for parsing CAS instructions to test the CAS encoding. 2014-02-07 07:34:49 +00:00
SparcISelDAGToDAG.cpp ISelDAG: spot chain cycles involving MachineNodes 2013-09-22 08:21:56 +00:00
SparcISelLowering.cpp [Sparc] Emit correct relocations for PIC code when integrated assembler is used. 2014-02-07 04:24:35 +00:00
SparcISelLowering.h Implement atomicrmw operations in 32 and 64 bits for SPARCv9. 2014-01-24 06:23:31 +00:00
SparcJITInfo.cpp [Sparc] Save and restore float registers that may be used for parameter passing. 2014-01-31 01:53:08 +00:00
SparcJITInfo.h [Sparc] Implement JIT for SPARC. 2013-10-08 07:15:22 +00:00
SparcMachineFunctionInfo.cpp Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 2012-02-18 12:03:15 +00:00
SparcMachineFunctionInfo.h [Sparc] Add support for leaf functions in sparc backend. 2013-05-29 04:46:31 +00:00
SparcMCInstLower.cpp [Sparc] Use SparcMCExpr::VariantKind itself as MachineOperand's target flags. 2014-02-07 02:36:06 +00:00
SparcRegisterInfo.cpp [Sparc] Set %o7 as the return address register instead of %i7 in MCRegisterInfo. Also, add CFI instructions to initialize the frame correctly. 2014-02-01 18:54:16 +00:00
SparcRegisterInfo.h Remove getEHExceptionRegister and getEHHandlerRegister. 2013-10-07 13:39:22 +00:00
SparcRegisterInfo.td [Sparc] Added V9's extra floating point registers and their aliases. 2013-08-25 17:03:02 +00:00
SparcRelocations.h [SparcV9] Add support for JIT in Sparc64. 2014-01-24 07:10:19 +00:00
SparcSelectionDAGInfo.cpp Implement a bunch more TargetSelectionDAGInfo infrastructure. 2010-05-11 17:31:57 +00:00
SparcSelectionDAGInfo.h Implement a bunch more TargetSelectionDAGInfo infrastructure. 2010-05-11 17:31:57 +00:00
SparcSubtarget.cpp Clean up the Legal/Expand logic for SPARC popc. 2014-01-26 08:12:34 +00:00
SparcSubtarget.h Only generate the popc instruction for SPARC CPUs that implement it. 2014-01-26 06:09:59 +00:00
SparcTargetMachine.cpp Make the llvm mangler depend only on DataLayout. 2014-01-03 19:21:54 +00:00
SparcTargetMachine.h [Sparc] Implement JIT for SPARC. 2013-10-08 07:15:22 +00:00
SparcTargetObjectFile.cpp [Sparc] Use %r_disp32 for pc_rel entries in gcc_except_table and eh_frame. 2014-01-29 04:51:35 +00:00
SparcTargetObjectFile.h [Sparc] Use %r_disp32 for pc_rel entries in gcc_except_table and eh_frame. 2014-01-29 04:51:35 +00:00
SparcTargetStreamer.h Construct the MCStreamer before constructing the MCTargetStreamer. 2014-01-26 06:06:37 +00:00

To-do
-----

* Keep the address of the constant pool in a register instead of forming its
  address all of the time.
* We can fold small constant offsets into the %hi/%lo references to constant
  pool addresses as well.
* When in V9 mode, register allocate %icc[0-3].
* Add support for isel'ing UMUL_LOHI instead of marking it as Expand.
* Emit the 'Branch on Integer Register with Prediction' instructions.  It's
  not clear how to write a pattern for this though:

float %t1(int %a, int* %p) {
        %C = seteq int %a, 0
        br bool %C, label %T, label %F
T:
        store int 123, int* %p
        br label %F
F:
        ret float undef
}

codegens to this:

t1:
        save -96, %o6, %o6
1)      subcc %i0, 0, %l0
1)      bne .LBBt1_2    ! F
        nop
.LBBt1_1:       ! T
        or %g0, 123, %l0
        st %l0, [%i1]
.LBBt1_2:       ! F
        restore %g0, %g0, %g0
        retl
        nop

1) should be replaced with a brz in V9 mode.

* Same as above, but emit conditional move on register zero (p192) in V9
  mode.  Testcase:

int %t1(int %a, int %b) {
        %C = seteq int %a, 0
        %D = select bool %C, int %a, int %b
        ret int %D
}

* Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling
  with the Y register, if they are faster.

* Codegen bswap(load)/store(bswap) -> load/store ASI

* Implement frame pointer elimination, e.g. eliminate save/restore for
  leaf fns.
* Fill delay slots

* Implement JIT support

* Use %g0 directly to materialize 0. No instruction is required.