Igor Breger 2fe1f6e4f3 AVX512: Change encoding of vpshuflw and vpshufhw instructions. Implement WIG as W0 and not W1, like all other instruction have been implemented. ...

Add encoding tests.

Differential Revision: http://reviews.llvm.org/D13471

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249521 91177308-0d34-0410-b5e6-96231b3b80d8

2015-10-07 06:31:18 +00:00

..

AArch64

[MC layer][AArch64] llvm-mc accepts 4-bit immediate values for

2015-10-05 13:42:31 +00:00

AMDGPU

AMDGPU/SI: Add 64-bit versions of v_nop and v_clrexcp

2015-10-06 15:57:53 +00:00

ARM

Actually switch the arch when we see .arch. PR21695

2015-10-02 18:25:25 +00:00

AsmParser

[MC/AsmParser] Avoid setting MCSymbol.IsUsed in some cases

2015-08-31 17:44:53 +00:00

COFF

Fix pr24486.

2015-10-05 12:07:05 +00:00

Disassembler

[mips][disassembler] Changed CHECK-EB directives to CHECK so div/divu are tested.

2015-10-06 10:08:14 +00:00

ELF

Fix pr24486.

2015-10-05 12:07:05 +00:00

Hexagon

[Hexagon] Reapply r239097 with tests corrected for shuffling and duplexing.

2015-06-05 16:00:11 +00:00

MachO

[MC] Convert all the remaining tests from macho-dump to llvm-readobj.

2015-09-10 01:50:00 +00:00

Markup

MC: Simple example parser for MC assembly markup.

2012-10-31 23:24:13 +00:00

Mips

[mips][microMIPS] Implement JALRC16, JRCADDIUSP and JRC16 instructions

2015-10-05 14:00:09 +00:00

PowerPC

Scalar to vector conversions using direct moves

2015-08-13 17:40:44 +00:00

Sparc

[SPARCv9] Add support for the rdpr/wrpr instructions.

2015-10-04 09:11:22 +00:00

SystemZ

[SystemZ] Add assembly instructions for obtaining clock values as well as CPU features

2015-10-01 14:43:48 +00:00

X86

AVX512: Change encoding of vpshuflw and vpshufhw instructions. Implement WIG as W0 and not W1, like all other instruction have been implemented.

2015-10-07 06:31:18 +00:00