RPCSX/archived-xed
1
0
Fork 0
mirror of https://github.com/RPCSX/xed.git synced 2026-01-31 01:05:17 +01:00
Code Issues Packages Projects Releases Wiki Activity

Disambiguate iforms for VFPCLASS{PD,PS} mem forms, suffix with VL

Browse Source 
* Affected iforms:
   VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL128
   VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL256
   VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL512
   VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL128
   VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL256
   VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL512

Change-Id: Id258940634ae653de73f7ee6cc6d230068c0fe9d
(cherry picked from commit a79455d7eb729c6b6a887a5ced4705bfcc66a310)
This commit is contained in:
Mark Charney
2017-01-06 16:37:34 -05:00
parent eefe8bbcb5
commit 4a0a09a154
1 changed files with 6 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
datafiles/avx512-skx/skx-isa.xed.txt
View File

@@ -6479,7 +6479,7 @@ REAL_OPCODE: Y
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
PATTERN: EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL()
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
IFORM: VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512
IFORM: VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL128
}
@@ -6509,7 +6509,7 @@ REAL_OPCODE: Y
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
PATTERN: EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL()
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
IFORM: VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512
IFORM: VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL256
}
@@ -6539,7 +6539,7 @@ REAL_OPCODE: Y
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
PATTERN: EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL()
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b
IFORM: VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512
IFORM: VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL512
}
@@ -6569,7 +6569,7 @@ REAL_OPCODE: Y
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
PATTERN: EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
IFORM: VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512
IFORM: VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL128
}
@@ -6599,7 +6599,7 @@ REAL_OPCODE: Y
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
PATTERN: EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
IFORM: VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512
IFORM: VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL256
}
@@ -6629,7 +6629,7 @@ REAL_OPCODE: Y
ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED
PATTERN: EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL()
OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b
IFORM: VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512
IFORM: VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL512
}