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Have RIP-rel addressing work with 67 prefix

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* decoder shows EIP if 67 used for rip rel in 64b mode.
    looks nicer.

  * encoder works with EIP (and emits 67) if used for encoding.

Change-Id: Ie3a63c7562c90ea8e48ac24e89d6ac5d8b20a1b8
This commit is contained in:
Mark Charney
2017-06-23 23:41:20 -04:00
parent 4f2d7653c5
commit 94339eca9d
4 changed files with 20 additions and 10 deletions
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6
datafiles/xed-addressing-modes-new.txt
View File

@@ -1,6 +1,6 @@
#BEGIN_LEGAL
#
#Copyright (c) 2016 Intel Corporation
#Copyright (c) 2017 Intel Corporation
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
@@ -80,8 +80,8 @@ MODRM64alt32()::
REXB=1 MOD=0b00 RM=0b100 SIB() |
# Ignores rexb -- must duplicate to avoid don't-care problems
REXB=0 MOD=0b00 RM=0b101 | NEED_MEMDISP=32 BASE0=XED_REG_RIP SEG0=FINAL_DSEG() enc
REXB=1 MOD=0b00 RM=0b101 | NEED_MEMDISP=32 BASE0=XED_REG_RIP SEG0=FINAL_DSEG()
REXB=0 MOD=0b00 RM=0b101 | NEED_MEMDISP=32 BASE0=rIPa() SEG0=FINAL_DSEG() enc
REXB=1 MOD=0b00 RM=0b101 | NEED_MEMDISP=32 BASE0=rIPa() SEG0=FINAL_DSEG()
REXB=0 MOD=0b00 RM=0b110 | BASE0=ArSI() SEG0=FINAL_DSEG()
REXB=1 MOD=0b00 RM=0b110 | BASE0=Ar14() SEG0=FINAL_DSEG()

11
datafiles/xed-modrm-encode.txt
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@@ -1,6 +1,6 @@
#BEGIN_LEGAL
#
#Copyright (c) 2016 Intel Corporation
#Copyright (c) 2017 Intel Corporation
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
@@ -39,7 +39,7 @@ SEQUENCE MODRM_EMIT
DISP_NT_EMIT()
SEGMENT_DEFAULT_ENCODE()::
BASE0=XED_REG_RIP -> nothing # no segment for RIP
BASE0=rIPa() -> nothing # no segment for RIP/EIP
BASE0=ArSP() -> default_ss # default to SS
BASE0=ArBP() -> default_ss # default to SS
BASE0=@ -> default_ds # default to DS -- baseless
@@ -258,14 +258,16 @@ otherwise -> MOD=1 # might use SIB
MODRM_MOD_EA32_DISP32()::
BASE0=@ -> MOD=0 #no base (handles SIB=1 case)
BASE0=GPR32e() -> MOD=2 #some base, not RIP, might use SIB
BASE0=XED_REG_RIP mode64 -> MOD=0
BASE0=rIPa() mode64 -> MOD=0
##############################################################################
#### EAMODE64
##############################################################################
MODRM_MOD_EA64_DISP0()::
BASE0=XED_REG_EIP -> MOD=0 DISP_WIDTH=32 DISP=0 # base eip
BASE0=XED_REG_RIP -> MOD=0 DISP_WIDTH=32 DISP=0 # base rip
BASE0=XED_REG_RBP -> MOD=1 DISP_WIDTH=8 DISP=0 # ARG MODIFICATION
BASE0=XED_REG_R13 -> MOD=1 DISP_WIDTH=8 DISP=0 # ARG MODIFICATION
BASE0=XED_REG_RAX -> MOD=0
@@ -288,6 +290,7 @@ BASE0=GPR64e() -> MOD=1
MODRM_MOD_EA64_DISP32()::
BASE0=@ -> MOD=0 #no base, SIB=1 required (provided elsewhere)
BASE0=XED_REG_EIP -> MOD=0 #base eip
BASE0=XED_REG_RIP -> MOD=0 #base rip
BASE0=XED_REG_RAX -> MOD=2
BASE0=XED_REG_RBX -> MOD=2
@@ -357,6 +360,7 @@ BASE0=XED_REG_RBP -> DISP_WIDTH_0_8_32() RM=5 REXB=0
# When we do the MOD encoding, we fix the displacement at 4B.
BASE0=XED_REG_RIP -> RM=5 # not setting REXB FIXME?
BASE0=XED_REG_EIP -> RM=5 # not setting REXB FIXME?
# for r13 without a disp, we add a 1B disp so MOD will be 1
BASE0=XED_REG_R13 -> DISP_WIDTH_0_8_32() RM=5 REXB=1
@@ -387,6 +391,7 @@ BASE0=XED_REG_EBP -> DISP_WIDTH_0_8_32() RM=5 REXB=0
BASE0=XED_REG_R13D -> DISP_WIDTH_0_8_32() RM=5 REXB=1
BASE0=XED_REG_RIP mode64 -> RM=5
BASE0=XED_REG_EIP mode64 -> RM=5
MODRM_RM_ENCODE_EANOT16_SIB1()::
otherwise -> RM=4 # SIB will specify the REXB etc.

4
datafiles/xed-reg-tables.txt
View File

@@ -112,6 +112,10 @@ mode16 | OUTREG=XED_REG_EIP
mode32 | OUTREG=XED_REG_EIP
mode64 | OUTREG=XED_REG_RIP
xed_reg_enum_t rIPa()::
EASZ=2 | OUTREG=XED_REG_EIP
EASZ=3 | OUTREG=XED_REG_RIP
#######################################################################
# Expand the generic registers using the effective address size EOSZ - limit 32b
#######################################################################

9
examples/xed-enc-lang.c
View File

@@ -1,6 +1,6 @@
/*BEGIN_LEGAL
Copyright (c) 2016 Intel Corporation
Copyright (c) 2017 Intel Corporation
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -457,10 +457,11 @@ parse_encode_request(ascii_encode_request_t areq)
rc = xed_gpr_reg_class(mem_bis.base_reg);
rci = xed_gpr_reg_class(mem_bis.index_reg);
if (rc == XED_REG_CLASS_GPR32 || rci == XED_REG_CLASS_GPR32)
if (mem_bis.base_reg == XED_REG_EIP)
xed_encoder_request_set_effective_address_size(&req, 32);
if (rc == XED_REG_CLASS_GPR16 || rci == XED_REG_CLASS_GPR16)
else if (rc == XED_REG_CLASS_GPR32 || rci == XED_REG_CLASS_GPR32)
xed_encoder_request_set_effective_address_size(&req, 32);
else if (rc == XED_REG_CLASS_GPR16 || rci == XED_REG_CLASS_GPR16)
xed_encoder_request_set_effective_address_size(&req, 16);
// fill in the memory fields