140706 Commits

Author SHA1 Message Date
Joerg Sonnenberger
0e71d50f7e Fix requirements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286527 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 23:53:45 +00:00
Matthias Braun
773603e851 ScheduleDAGInstrs: Ignore dependencies of constant physregs
There is no need to track dependencies for constant physregs, as they
don't change their value no matter in what order you read/write to them.

Differential Revision: https://reviews.llvm.org/D26221

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286526 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 23:46:44 +00:00
Matthias Braun
a46113773f Timer: Remove group-less NamedRegionTimer constructor.
The NamedRegionTimer initializer without a group name puts the Timer
into the "Misc" group and is (nearly) unused. Remove it.

The only user of this constructor appears to be the HexagonGenInsert pass,
which creates a counter without group to count the complete execution
time of that pass, however since every pass gets a counter by the
PassManager anyway this should be unnecessary. Also removed the
pointless TimerGroup there.

Differential Revision: https://reviews.llvm.org/D25582

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286524 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 23:36:44 +00:00
Evandro Menezes
3f647d62d1 [DAG Combiner] Fix the native computation of the Newton series for reciprocals
The generic infrastructure to compute the Newton series for reciprocal and
reciprocal square root was conceived to allow a target to compute the series
itself.  However, the original code did not properly consider this condition
if returned by a target.  This patch addresses the issues to allow a target
to compute the series on its own.

Differential revision: https://reviews.llvm.org/D22975

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286523 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 23:31:06 +00:00
Tim Northover
b020491725 GlobalISel: fix mistaken comment change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286517 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 22:47:38 +00:00
Simon Pilgrim
c5bdc92c0d [SelectionDAG] Add support for vector demandedelts in ADD/SUB opcodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286516 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 22:41:49 +00:00
Justin Lebar
a145558c9a [LSR] Tweak loop-strength-reduce-crash test. Test-only change.
Run opt instead of llc, and update the comment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286515 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 22:37:13 +00:00
Peter Collingbourne
ca668e1942 IR: Introduce inrange attribute on getelementptr indices.
If the inrange keyword is present before any index, loading from or
storing to any pointer derived from the getelementptr has undefined
behavior if the load or store would access memory outside of the bounds of
the element selected by the index marked as inrange.

This can be used, e.g. for alias analysis or to split globals at element
boundaries where beneficial.

As previously proposed on llvm-dev:
http://lists.llvm.org/pipermail/llvm-dev/2016-July/102472.html

Differential Revision: https://reviews.llvm.org/D22793

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286514 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 22:34:55 +00:00
Simon Pilgrim
d31cbc45ab [X86] Updated knownbits vector ADD/SUB test
In preparation for demandedelts support

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286513 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 22:34:12 +00:00
Simon Pilgrim
d3f442dd4d [X86] Add knownbits vector ADD test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286511 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 22:21:04 +00:00
Matthias Braun
fc1b3b34fd ScheduleDAGInstrs: Slightly simplify code; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286510 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 22:11:00 +00:00
Simon Pilgrim
7a98835990 [SelectionDAG] Add support for splatted vectors in SUB opcode
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286509 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 21:57:42 +00:00
Simon Pilgrim
d2d5b99bae [X86] Add knownbits vector SUB test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286508 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 21:50:23 +00:00
Matthias Braun
2821987cf3 RegisterCoalescer: Ignore interferences for constant physregs
When copying to/from a constant register interferences can be ignored.

Also update the documentation for isConstantPhysReg() to make it more
obvious that this transformation is valid.

Differential Revision: https://reviews.llvm.org/D26106

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286503 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 21:22:47 +00:00
Yaxun Liu
a2ee7d2991 AMDGPU: Emit runtime metadata as a note element in .note section
Currently runtime metadata is emitted as an ELF section with name .AMDGPU.runtime_metadata.

However there is a standard way to convey vendor specific information about how to run an ELF binary, which is called vendor-specific note element (http://www.netbsd.org/docs/kernel/elf-notes.html).

This patch lets AMDGPU backend emits runtime metadata as a note element in .note section.

Differential Revision: https://reviews.llvm.org/D25781


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286502 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 21:18:49 +00:00
Zachary Turner
a6269f0326 Fix type ambiguity with std::max
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286498 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 20:35:21 +00:00
Zachary Turner
67e788099e Fix initialization order error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286497 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 20:23:32 +00:00
Zachary Turner
48fbf5cc1a [Support] Improve flexibility of binary blob formatter.
This makes it possible to indent a binary blob by a certain
number of bytes, and also makes some things more idiomatic.
Finally, it integrates this binary blob formatter into ScopedPrinter
which used to have its own implementation of this algorithm.

Differential Revision: https://reviews.llvm.org/D26477

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286495 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 20:16:45 +00:00
Zachary Turner
ab792ca2d9 [PDB] Begin adding documentation for the PDB file format.
Differential Revision: https://reviews.llvm.org/D26374

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286491 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 19:24:21 +00:00
Adam Nemet
e13ecb7d13 [opt-viewer] Avoid duplicated remarks
This can happen if a pass is run multiple times or if the code is in a
header file which is included multiple times.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286489 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 18:42:56 +00:00
Davide Italiano
b7798f4fb6 [Target] Rename X86/ARM Assembly printer to reflect reality.
This shows up a lot profiling LTO testcases with -time-passes, so
better have a non confusing name.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286488 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 18:39:31 +00:00
Eugene Zelenko
31593faf06 Fix some Clang-tidy modernize-use-default and readability-redundant-member-init and Include What You Use warnings; other minor fixes.
Differential revision: https://reviews.llvm.org/D26087


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286484 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 18:02:34 +00:00
Nico Weber
2e53b7150a Revert r286437 r286438, they caused PR30976
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286483 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 17:55:41 +00:00
Adam Nemet
9bf32e200d [OptDiag] Remove non-printable chars from function name
The r283656 did this in the remark arguments.  We also need to do this
in the main function attribute as that is written to YAML as well.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286482 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 17:47:03 +00:00
Simon Pilgrim
9ae088bf72 [SelectionDAG] Add support for vector demandedelts in TRUNCATE opcodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286481 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 17:43:52 +00:00
Dehao Chen
fb6e3a842a Add comments about why we put LoopSink pass at the very late stage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286480 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 17:42:18 +00:00
Simon Pilgrim
68c986108b [X86] Add knownbits vector TRUNC test
In preparation for demandedelts support

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286477 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 17:24:33 +00:00
Teresa Johnson
62e70770b5 Restore part of "[ThinLTO] Prevent exporting of locals used/defined in module level asm"
This restores the part of r286297 that didn't require adding a
dependency from the Analysis to Object library. There are two parts
to the original fix, and this will address the handling for the case
where locals are used in module level asm.

The part that requires functionality in libObject handles local defs
in module level asm, and was reverted because our downstream build
of clang builds lib/Bitcode into a single library, and this new
dependency introduced a cycle there. I am trying to get that fixed
(see D26502), so for now that change isn't being restored

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286475 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 16:57:32 +00:00
Simon Pilgrim
a7d6813516 Use common SDLoc. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286473 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 16:47:09 +00:00
Simon Pilgrim
e84f684084 [SelectionDAG] Add support for vector demandedelts in MUL opcodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286471 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 16:27:42 +00:00
Asaf Badouh
1d957ffe5a reproducer for pr29002
https://reviews.llvm.org/D26449

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286470 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 16:27:27 +00:00
Tom Stellard
0deee390af AMDGPU: Add VI i16 support
Patch By: Wei Ding

Differential Revision: https://reviews.llvm.org/D18049

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286464 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 16:02:37 +00:00
Simon Pilgrim
3cc5ea94f2 [X86] Add knownbits vector MUL test
In preparation for demandedelts support

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286463 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 15:57:33 +00:00
Simon Pilgrim
2eb0b40c6a [SelectionDAG] Add support for vector demandedelts in SRA opcodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286461 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 15:05:09 +00:00
Sanjay Patel
80dc268da9 [InstCombine] auto-generate better checks; NFC
Note that the existing metadata checking was re-added by hand because the 
script doesn't currently know how to generate checks for lines outside of 
functions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286460 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 14:58:17 +00:00
Simon Pilgrim
dbb1fda971 [X86] Add knownbits vector arithmetic shift test
In preparation for demandedelts support

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286457 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 14:46:24 +00:00
Simon Pilgrim
0c5b3f0761 [DAGCombiner] Correctly extract the ConstOrConstSplat shift value for SHL nodes
We were failing to extract a constant splat shift value if the shifted value was being masked.

The (shl (and (setcc) N01CV) N1CV) -> (and (setcc) N01CV<<N1CV) combine was unnecessarily preventing this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286454 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 14:35:09 +00:00
Chad Rosier
1f5dcd896f Remove unnecessary check prefix directives. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286453 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 14:28:44 +00:00
Simon Pilgrim
3cc160451c [DAGCombiner] Show missed opportunity to UNDEF out-of-range SHL
Fails to match constant shift value due to presence of AND mask.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286452 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 14:19:45 +00:00
Tobias Grosser
541a4fd75d [RegionInfo] Add three tests that include infinite loops
These examples are variations that were inspired from a small subgraph taken
from paper.ll which are interesting as they show certain issues with infinite
loops.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286450 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 13:56:19 +00:00
Simon Pilgrim
f524b350db [SelectionDAG] Add support for vector demandedelts in SHL/SRL opcodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286448 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 13:52:42 +00:00
Simon Pilgrim
6392d731a4 [X86] Add knownbits vector logical shift test
In preparation for demandedelts support

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286447 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 13:34:17 +00:00
Oliver Stannard
4a04eb017b [ARM] Thumb2 LDR (literal) should accept PC as the destination
The version of this instruction with the .w suffix already correctly accepts
this, but the alias without the .w did not.

Differential Revision: https://reviews.llvm.org/D26499



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286446 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 13:20:41 +00:00
Sanjoy Das
b2e86a3cab [SCEVExpander] Hoist unsigned divisons when safe
That is, when the divisor is a constant non-zero.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286438 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 07:56:12 +00:00
Sanjoy Das
ea50f98cad [SCEVExpander] Don't hoist divisions
Fixes PR30942.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286437 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 07:56:09 +00:00
Sanjoy Das
32c88043af Lift out a helper lambda; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286436 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 07:56:05 +00:00
Craig Topper
79013e50a6 [AVX-512] Allow legacy cvtpd2dq intrinsics to select EVEX encoded instruction when available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286435 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 07:47:17 +00:00
Craig Topper
89432488d2 [AVX-512][X86] Convert avx_cvtt_ps2dq_256 and sse2_cvttps2dq intrinsics to ISD::FP_TO_SINT in the intrinsics table and delete patterns. While nearby also move CVTDQ2PS patterns into their instructions.
This allows these intrinsics to also use EVEX instructons.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286434 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 07:24:52 +00:00
Craig Topper
70894ee006 [X86] Convert int_x86_avx_cvtt_pd2dq_256 to fp_to_sint using the intrinsics table. Removes extra patterns and allows legacy intrinsic to select EVEX encoded instructions when available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286433 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 06:45:39 +00:00
Craig Topper
7cf26e1149 [X86] Move some custom patterns into the currently empty pattern of their corresponding instructions. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286432 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 06:45:37 +00:00