40670 Commits

Author SHA1 Message Date
Matthias Braun
773603e851 ScheduleDAGInstrs: Ignore dependencies of constant physregs
There is no need to track dependencies for constant physregs, as they
don't change their value no matter in what order you read/write to them.

Differential Revision: https://reviews.llvm.org/D26221

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286526 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 23:46:44 +00:00
Simon Pilgrim
c5bdc92c0d [SelectionDAG] Add support for vector demandedelts in ADD/SUB opcodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286516 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 22:41:49 +00:00
Justin Lebar
a145558c9a [LSR] Tweak loop-strength-reduce-crash test. Test-only change.
Run opt instead of llc, and update the comment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286515 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 22:37:13 +00:00
Peter Collingbourne
ca668e1942 IR: Introduce inrange attribute on getelementptr indices.
If the inrange keyword is present before any index, loading from or
storing to any pointer derived from the getelementptr has undefined
behavior if the load or store would access memory outside of the bounds of
the element selected by the index marked as inrange.

This can be used, e.g. for alias analysis or to split globals at element
boundaries where beneficial.

As previously proposed on llvm-dev:
http://lists.llvm.org/pipermail/llvm-dev/2016-July/102472.html

Differential Revision: https://reviews.llvm.org/D22793

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286514 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 22:34:55 +00:00
Simon Pilgrim
d31cbc45ab [X86] Updated knownbits vector ADD/SUB test
In preparation for demandedelts support

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286513 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 22:34:12 +00:00
Simon Pilgrim
d3f442dd4d [X86] Add knownbits vector ADD test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286511 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 22:21:04 +00:00
Simon Pilgrim
7a98835990 [SelectionDAG] Add support for splatted vectors in SUB opcode
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286509 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 21:57:42 +00:00
Simon Pilgrim
d2d5b99bae [X86] Add knownbits vector SUB test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286508 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 21:50:23 +00:00
Matthias Braun
2821987cf3 RegisterCoalescer: Ignore interferences for constant physregs
When copying to/from a constant register interferences can be ignored.

Also update the documentation for isConstantPhysReg() to make it more
obvious that this transformation is valid.

Differential Revision: https://reviews.llvm.org/D26106

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286503 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 21:22:47 +00:00
Yaxun Liu
a2ee7d2991 AMDGPU: Emit runtime metadata as a note element in .note section
Currently runtime metadata is emitted as an ELF section with name .AMDGPU.runtime_metadata.

However there is a standard way to convey vendor specific information about how to run an ELF binary, which is called vendor-specific note element (http://www.netbsd.org/docs/kernel/elf-notes.html).

This patch lets AMDGPU backend emits runtime metadata as a note element in .note section.

Differential Revision: https://reviews.llvm.org/D25781


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286502 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 21:18:49 +00:00
Adam Nemet
9bf32e200d [OptDiag] Remove non-printable chars from function name
The r283656 did this in the remark arguments.  We also need to do this
in the main function attribute as that is written to YAML as well.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286482 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 17:47:03 +00:00
Simon Pilgrim
9ae088bf72 [SelectionDAG] Add support for vector demandedelts in TRUNCATE opcodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286481 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 17:43:52 +00:00
Simon Pilgrim
68c986108b [X86] Add knownbits vector TRUNC test
In preparation for demandedelts support

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286477 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 17:24:33 +00:00
Teresa Johnson
62e70770b5 Restore part of "[ThinLTO] Prevent exporting of locals used/defined in module level asm"
This restores the part of r286297 that didn't require adding a
dependency from the Analysis to Object library. There are two parts
to the original fix, and this will address the handling for the case
where locals are used in module level asm.

The part that requires functionality in libObject handles local defs
in module level asm, and was reverted because our downstream build
of clang builds lib/Bitcode into a single library, and this new
dependency introduced a cycle there. I am trying to get that fixed
(see D26502), so for now that change isn't being restored

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286475 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 16:57:32 +00:00
Simon Pilgrim
e84f684084 [SelectionDAG] Add support for vector demandedelts in MUL opcodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286471 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 16:27:42 +00:00
Asaf Badouh
1d957ffe5a reproducer for pr29002
https://reviews.llvm.org/D26449

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286470 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 16:27:27 +00:00
Tom Stellard
0deee390af AMDGPU: Add VI i16 support
Patch By: Wei Ding

Differential Revision: https://reviews.llvm.org/D18049

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286464 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 16:02:37 +00:00
Simon Pilgrim
3cc5ea94f2 [X86] Add knownbits vector MUL test
In preparation for demandedelts support

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286463 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 15:57:33 +00:00
Simon Pilgrim
2eb0b40c6a [SelectionDAG] Add support for vector demandedelts in SRA opcodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286461 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 15:05:09 +00:00
Sanjay Patel
80dc268da9 [InstCombine] auto-generate better checks; NFC
Note that the existing metadata checking was re-added by hand because the 
script doesn't currently know how to generate checks for lines outside of 
functions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286460 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 14:58:17 +00:00
Simon Pilgrim
dbb1fda971 [X86] Add knownbits vector arithmetic shift test
In preparation for demandedelts support

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286457 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 14:46:24 +00:00
Simon Pilgrim
0c5b3f0761 [DAGCombiner] Correctly extract the ConstOrConstSplat shift value for SHL nodes
We were failing to extract a constant splat shift value if the shifted value was being masked.

The (shl (and (setcc) N01CV) N1CV) -> (and (setcc) N01CV<<N1CV) combine was unnecessarily preventing this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286454 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 14:35:09 +00:00
Chad Rosier
1f5dcd896f Remove unnecessary check prefix directives. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286453 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 14:28:44 +00:00
Simon Pilgrim
3cc160451c [DAGCombiner] Show missed opportunity to UNDEF out-of-range SHL
Fails to match constant shift value due to presence of AND mask.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286452 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 14:19:45 +00:00
Tobias Grosser
541a4fd75d [RegionInfo] Add three tests that include infinite loops
These examples are variations that were inspired from a small subgraph taken
from paper.ll which are interesting as they show certain issues with infinite
loops.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286450 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 13:56:19 +00:00
Simon Pilgrim
f524b350db [SelectionDAG] Add support for vector demandedelts in SHL/SRL opcodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286448 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 13:52:42 +00:00
Simon Pilgrim
6392d731a4 [X86] Add knownbits vector logical shift test
In preparation for demandedelts support

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286447 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 13:34:17 +00:00
Oliver Stannard
4a04eb017b [ARM] Thumb2 LDR (literal) should accept PC as the destination
The version of this instruction with the .w suffix already correctly accepts
this, but the alias without the .w did not.

Differential Revision: https://reviews.llvm.org/D26499



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286446 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 13:20:41 +00:00
Craig Topper
79013e50a6 [AVX-512] Allow legacy cvtpd2dq intrinsics to select EVEX encoded instruction when available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286435 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 07:47:17 +00:00
Craig Topper
89432488d2 [AVX-512][X86] Convert avx_cvtt_ps2dq_256 and sse2_cvttps2dq intrinsics to ISD::FP_TO_SINT in the intrinsics table and delete patterns. While nearby also move CVTDQ2PS patterns into their instructions.
This allows these intrinsics to also use EVEX instructons.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286434 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 07:24:52 +00:00
Craig Topper
70894ee006 [X86] Convert int_x86_avx_cvtt_pd2dq_256 to fp_to_sint using the intrinsics table. Removes extra patterns and allows legacy intrinsic to select EVEX encoded instructions when available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286433 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 06:45:39 +00:00
Craig Topper
5ffdf013bf [AVX-512] Add test cases to show missed opportunities for using VALIGND/Q to handle shuffles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286425 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 03:39:19 +00:00
Sanjay Patel
9c5e4bac4a [InstCombine] avoid infinite loop from shuffle-extract-insert sequence (PR30923)
Removing the limitation in visitInsertElementInst() causes several regressions
because we're not prepared to fold sequences of shuffles or inserts and extracts
separated by shuffles. Fixing that appears to be a difficult mission because we
are purposely trying to avoid creating shuffles with arbitrary shuffle masks
because some targets may choke on those.

https://llvm.org/bugs/show_bug.cgi?id=30923


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286423 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-10 00:15:14 +00:00
Peter Collingbourne
027f4d03c6 Re-apply r286384, "X86: Introduce the "relocImm" ComplexPattern, which represents a relocatable immediate.", with a fix for 32-bit x86.
Teach X86InstrInfo::analyzeCompare() not to crash on CMP and SUB instructions
that take a global address operand.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286420 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-09 23:53:43 +00:00
Dylan McKay
619ca04281 [AVR] Add a selection of CodeGen tests
Summary: This adds all of the CodeGen tests which currently pass.

Reviewers: arsenm, kparzysz

Subscribers: japaric, wdng

Differential Revision: https://reviews.llvm.org/D26388

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286418 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-09 23:46:52 +00:00
Dylan McKay
64af2512f1 [AVR] Add all of the machine code test suite
Summary: This adds all of the AVR machine code tests.

Reviewers: arsenm, kparzysz

Subscribers: wdng, japaric

Differential Revision: https://reviews.llvm.org/D26387

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286417 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-09 23:46:25 +00:00
Tim Northover
e6797b7d75 GlobalISel: translate invoke and landingpad instructions
Pretty bare-bones support for exception handling (no weird MSVC stuff, no SjLj
etc), but it should get things going.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286407 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-09 22:39:54 +00:00
Dehao Chen
746789378b Update vectorization debug info unittest.
Summary:
The change will test the change in r286159.
The idea behind the change: Make the dbg location different between loop header and preheader/exit. Originally, dbg location 21 exists in 3 BBs: preheader, header, critical edge (exit). Update the debug location of inside the loop header from !21 to !22 so that it will reflect the correct location.

Reviewers: probinson

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D26428

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286403 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-09 22:25:19 +00:00
Sanjay Patel
b347251bf7 [InstCombine] regenerate checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286402 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-09 22:21:58 +00:00
Sanjay Patel
c4a40a2d62 [InstCombine] regenerate checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286399 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-09 21:41:34 +00:00
Krzysztof Parzyszek
5d84a0761e [Hexagon] Separate Hexagon subreg indices for different register classes
For pairs of 32-bit registers: isub_lo, isub_hi.
For pairs of vector registers: vsub_lo, vsub_hi.

Add generic subreg indices: ps_sub_lo, ps_sub_hi, and a function
  HexagonRegisterInfo::getHexagonSubRegIndex(RegClass, GenericSubreg)
that returns the appropriate subreg index for RegClass.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286377 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-09 16:19:08 +00:00
Krzysztof Parzyszek
0f89628001 [Hexagon] Eliminate Insert4 pseudo-instruction, use combines instead
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286368 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-09 14:16:29 +00:00
Alexandros Lamprineas
32054b584b [ARM] Loop Strength Reduction crashes when targeting ARM or Thumb.
Scalar Evolution asserts when not all the operands of an Add Recurrence
Expression are loop invariants. Loop Strength Reduction should only
create affine Add Recurrences, so that both the start and the step of
the expression are loop invariants.

Differential Revision: https://reviews.llvm.org/D26185

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286347 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-09 08:53:07 +00:00
Craig Topper
1f641ae1c5 [AVX-512] Add lowering to cvttpd2udq/cvttps2udq for fptoui v2f64/2f32 to 2i32
This patch adds support for fptoui to 2i32 from both 2f64 and 2f32, building on Simon's change for the signed version in r284459 and using AVX-512 instructions.

If we don't have VLX support we need to use a 512-bit operation for v2f64->v2i32 and extract the result.

It also recognises that cvttpd2udq zeroes the upper 64-bits of the xmm result.

Differential Revision: https://reviews.llvm.org/D26331

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286345 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-09 07:48:51 +00:00
Craig Topper
45b3e8f9df [X86] Lower AVX512 and SSE intrinsics for CVTTPD2DQ to X86ISD::CVTTPD2DQ.
Summary: This allows the SSE intrinsic to use the EVEX instruction when available. It also fixes EVEX to not use a weird (v4i32 (fp_to_sint v2f64)) node and it merges some isel patterns. This also fixes some cases that weren't combining vzmovl with cvttpd2dq to remove extra moves.

Reviewers: delena, zvi, RKSimon

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D26330

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286344 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-09 07:31:32 +00:00
Craig Topper
106bb1fe2d [AVX-512] Add more varied alignments to tests for storing the lower 128-bits of a 256 or 512-bit subvector extract.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286343 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-09 05:38:47 +00:00
Craig Topper
4c1b9a2ab6 [AVX-512] Use alignedstore256 in patterns that look for stores of the lower 256-bits of a 512-bit vector to use a 256-bit aligned store.
Previously we were only checking for 16 byte alignment instead of 32 byte alignment. Fixes PR30947.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286342 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-09 05:31:57 +00:00
Craig Topper
89f0495611 [AVX-512] Add test cases to demonstrate PR30947. We accidentally use 32 byte aligned store instructions when the original store was only 16 byte aligned if the store is from the lower bits of a subvector extract.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286341 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-09 05:31:53 +00:00
Craig Topper
f43d5aff8d [AVX-512] Make VBMI instruction set enabling imply that the BWI instruction set is also enabled.
Summary:
This is needed to make the v64i8 and v32i16 types legal for the 512-bit VBMI instructions. Fixes PR30912.

Reviewers: delena, zvi

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D26322

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286339 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-09 04:50:48 +00:00
Mehdi Amini
129c9fcdb8 Revert "[ThinLTO] Prevent exporting of locals used/defined in module level asm"
This reverts commit r286297.
Introduces a dependency from libAnalysis to libObject, which I missed
during the review.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286329 91177308-0d34-0410-b5e6-96231b3b80d8
2016-11-09 01:45:13 +00:00