41539 Commits

Author SHA1 Message Date
Sebastian Pop
0ed0bfd718 machine combiner: fix pretty printer
we used to print UNKNOWN instructions when the instruction to be printer was not
yet inserted in any BB: in that case the pretty printer would not be able to
compute a TII as the instruction does not belong to any BB or function yet.
This patch explicitly passes the TII to the pretty-printer.

Differential Revision: https://reviews.llvm.org/D27645

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290228 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-21 01:41:12 +00:00
George Burgess IV
1ced44b92a [Analysis] Centralize objectsize lowering logic.
We're currently doing nearly the same thing for @llvm.objectsize in
three different places: two of them are missing checks for overflow,
and one of them could subtly break if InstCombine gets much smarter
about removing alloc sites. Seems like a good idea to not do that.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290214 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-20 23:46:36 +00:00
Chris Bieneman
4138b67a0a Revert "[ObjectYAML] Support for DWARF debug_info section"
This reverts commit r290204.

Still breaking bots... In a meeting now, so I can't fix it immediately.

Bot URL:
http://lab.llvm.org:8011/builders/clang-s390x-linux/builds/2415

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290209 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-20 22:36:42 +00:00
Chris Bieneman
0ef22e255c [ObjectYAML] Support for DWARF debug_info section
This patch adds support for YAML<->DWARF for debug_info sections.

This re-lands r290147, after fixing the issue that caused bots to fail (thank you UBSan!).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290204 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-20 21:35:31 +00:00
Peter Collingbourne
36fc3f6000 IR: Eliminate non-determinism in the module summary analysis.
Also make the summary ref and call graph vectors immutable. This means
a smaller API surface and fewer places to audit for non-determinism.

Differential Revision: https://reviews.llvm.org/D27875

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290200 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-20 21:12:28 +00:00
Eli Friedman
1e77c707b7 [ARM] Implement isExtractSubvectorCheap.
See https://reviews.llvm.org/D6678 for the history of
isExtractSubvectorCheap. Essentially the same considerations apply
to ARM.

This temporarily breaks the formation of vpadd/vpaddl in certain cases;
AddCombineToVPADDL essentially assumes that we won't form VUZP shuffles.
See https://reviews.llvm.org/D27779 for followup fix.

Differential Revision: https://reviews.llvm.org/D27774



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290198 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-20 20:05:07 +00:00
Eli Friedman
967c9cbd8f [ARM] Generate checks for shuffle tests using update_llc_test_checks.py.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290196 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-20 19:33:24 +00:00
Matt Arsenault
256f8018fa AMDGPU: Allow 16-bit types in inline asm constraints
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290193 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-20 19:06:12 +00:00
Matt Arsenault
4bcae756d4 AMDGPU: Run fp combine tests on VI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290192 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-20 18:55:11 +00:00
Matt Arsenault
44e57608d4 AMDGPU: Don't add same instruction multiple times to worklist
When the instruction is processed the first time, it may be
deleted resulting in crashes. While the new test adds the same
user to the worklist twice, this particular case doesn't crash
but I'm not sure why.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290191 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-20 18:55:06 +00:00
Tom Stellard
38206ae07e AMDGPU/SI: Add a MachineMemOperand when lowering llvm.amdgcn.buffer.load.*
Reviewers: arsenm, nhaehnle, mareko

Subscribers: kzhuravl, wdng, yaxunl, llvm-commits, tony-tye

Differential Revision: https://reviews.llvm.org/D27834

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290184 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-20 17:19:44 +00:00
Tom Stellard
11d071bf72 AMDGPU/SI: Add a MachineMemOperand to MIMG instructions
Summary:
Without a MachineMemOperand, the scheduler was assuming MIMG instructions
were ordered memory references, so no loads or stores could be reordered
across them.

Reviewers: arsenm

Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, tony-tye

Differential Revision: https://reviews.llvm.org/D27536

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290179 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-20 15:52:17 +00:00
Chandler Carruth
54cffa1811 [PM] Provide an initial, minimal port of the inliner to the new pass manager.
This doesn't implement *every* feature of the existing inliner, but
tries to implement the most important ones for building a functional
optimization pipeline and beginning to sort out bugs, regressions, and
other problems.

Notable, but intentional omissions:
- No alloca merging support. Why? Because it isn't clear we want to do
  this at all. Active discussion and investigation is going on to remove
  it, so for simplicity I omitted it.
- No support for trying to iterate on "internally" devirtualized calls.
  Why? Because it adds what I suspect is inappropriate coupling for
  little or no benefit. We will have an outer iteration system that
  tracks devirtualization including that from function passes and
  iterates already. We should improve that rather than approximate it
  here.
- Optimization remarks. Why? Purely to make the patch smaller, no other
  reason at all.

The last one I'll probably work on almost immediately. But I wanted to
skip it in the initial patch to try to focus the change as much as
possible as there is already a lot of code moving around and both of
these *could* be skipped without really disrupting the core logic.

A summary of the different things happening here:

1) Adding the usual new PM class and rigging.

2) Fixing minor underlying assumptions in the inline cost analysis or
   inline logic that don't generally hold in the new PM world.

3) Adding the core pass logic which is in essence a loop over the calls
   in the nodes in the call graph. This is a bit duplicated from the old
   inliner, but only a handful of lines could realistically be shared.
   (I tried at first, and it really didn't help anything.) All told,
   this is only about 100 lines of code, and most of that is the
   mechanics of wiring up analyses from the new PM world.

4) Updating the LazyCallGraph (in the new PM) based on the *newly
   inlined* calls and references. This is very minimal because we cannot
   form cycles.

5) When inlining removes the last use of a function, eagerly nuking the
   body of the function so that any "one use remaining" inline cost
   heuristics are immediately refined, and queuing these functions to be
   completely deleted once inlining is complete and the call graph
   updated to reflect that they have become dead.

6) After all the inlining for a particular function, updating the
   LazyCallGraph and the CGSCC pass manager to reflect the
   function-local simplifications that are done immediately and
   internally by the inline utilties. These are the exact same
   fundamental set of CG updates done by arbitrary function passes.

7) Adding a bunch of test cases to specifically target CGSCC and other
   subtle aspects in the new PM world.

Many thanks to the careful review from Easwaran and Sanjoy and others!

Differential Revision: https://reviews.llvm.org/D24226

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290161 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-20 03:15:32 +00:00
Adrian Prantl
7b500b4bdf [IR] Remove the DIExpression field from DIGlobalVariable.
This patch implements PR31013 by introducing a
DIGlobalVariableExpression that holds a pair of DIGlobalVariable and
DIExpression.

Currently, DIGlobalVariables holds a DIExpression. This is not the
best way to model this:

(1) The DIGlobalVariable should describe the source level variable,
    not how to get to its location.

(2) It makes it unsafe/hard to update the expressions when we call
    replaceExpression on the DIGLobalVariable.

(3) It makes it impossible to represent a global variable that is in
    more than one location (e.g., a variable with multiple
    DW_OP_LLVM_fragment-s).  We also moved away from attaching the
    DIExpression to DILocalVariable for the same reasons.

This reapplies r289902 with additional testcase upgrades and a change
to the Bitcode record for DIGlobalVariable, that makes upgrading the
old format unambiguous also for variables without DIExpressions.

<rdar://problem/29250149>
https://llvm.org/bugs/show_bug.cgi?id=31013
Differential Revision: https://reviews.llvm.org/D26769

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290153 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-20 02:09:43 +00:00
Chris Bieneman
23755c9509 Revert "[ObjectYAML] Support for DWARF debug_info section"
This reverts commit r290147.

This commit is breaking a bot (http://lab.llvm.org:8011/builders/clang-atom-d525-fedora-rel/builds/621). I don't have time to investigate at the moment, so I'll revert for now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290148 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-20 00:42:06 +00:00
Chris Bieneman
eca8f9afc6 [ObjectYAML] Support for DWARF debug_info section
This patch adds support for YAML<->DWARF for debug_info sections.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290147 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-20 00:26:24 +00:00
Eli Friedman
97cbb36487 Add ARM support to update_llc_test_checks.py
Just the minimal support to get it working at the moment.

Includes checks for test/CodeGen/ARM/vzip.ll as an example.

Differential Revision: https://reviews.llvm.org/D27829



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290144 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-19 23:09:51 +00:00
Chris Bieneman
c2813d918a [ObjectYAML] Support for DWARF Pub Sections
This patch adds support for YAML<->DWARF round tripping for pub* section data. The patch supports both GNU and non-GNU style entries.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290139 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-19 22:22:12 +00:00
Sanjay Patel
1fd371a473 [InstCombine] use commutative matcher for pattern with commutative operators
This is a case that was missed in:
https://reviews.llvm.org/rL290067
...and it would regress if we fix operand complexity (PR28296).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290127 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-19 18:35:37 +00:00
Sanjay Patel
63e1cbe0bb [InstCombine] add folds for icmp (umin|umax X, Y), X
This is a follow-up to:
https://reviews.llvm.org/rL289855 (https://reviews.llvm.org/D27531)
https://reviews.llvm.org/rL290111


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290118 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-19 17:32:37 +00:00
Florian Hahn
c8f0c8614b [LoopVersioning] Require loop-simplify form for loop versioning.
Summary:
Requiring loop-simplify form for loop versioning ensures that the
runtime check block always dominates the exit block.
    
This patch closes #30958 (https://llvm.org/bugs/show_bug.cgi?id=30958).

Reviewers: silviu.baranga, hfinkel, anemet, ashutosh.nema

Subscribers: ashutosh.nema, mzolotukhin, efriedma, hfinkel, llvm-commits

Differential Revision: https://reviews.llvm.org/D27469

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290116 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-19 17:13:37 +00:00
Konstantin Zhuravlyov
76d41d2938 [AMDGPU] When unifying metadata, add operands to named metadata individually
Differential Revision: https://reviews.llvm.org/D27725


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290114 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-19 16:54:24 +00:00
Sanjay Patel
21b74be87d [InstCombine] add folds for icmp (smax X, Y), X
This is a follow-up to:
https://reviews.llvm.org/rL289855 (D27531)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290111 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-19 16:28:53 +00:00
Diana Picus
7678e12d91 [ARM] GlobalISel: Add more checks to test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290108 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-19 14:08:11 +00:00
Diana Picus
af01848eb7 [ARM] GlobalISel: Minor style fixup in test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290107 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-19 14:08:06 +00:00
Diana Picus
ce4dc1f41b [ARM] GlobalISel: Lower i8 and i16 register args
This allows lowering i8 and i16 arguments if they can fit in the registers. Note
that the lowering is incomplete - ABI extensions are handled in a subsequent
patch.

(Last part of)
Differential Revision: https://reviews.llvm.org/D27704

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290106 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-19 14:08:02 +00:00
Diana Picus
07b3834b44 [ARM] GlobalISel: Allow i8 and i16 adds
Teach the instruction selector and legalizer that it's ok to have adds with 8 or
16-bit integers.

This is the second part of https://reviews.llvm.org/D27704

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290105 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-19 14:07:56 +00:00
Diana Picus
f2838d8814 [ARM] GlobalISel: Select i8 and i16 copies
Teach the instruction selector that it's ok to copy small values from physical
registers.

First part of https://reviews.llvm.org/D27704

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290104 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-19 14:07:50 +00:00
Diana Picus
9950c0fd74 [ARM] GlobalISel: Lower more than 4 arguments
This adds support for lowering more than 4 arguments (although still i32 only).
It uses the handleAssignments / ValueHandler infrastructure extracted from
the AArch64 backend in r288658.

Differential Revision: https://reviews.llvm.org/D27195

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290098 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-19 11:55:41 +00:00
Sam Kolton
a8a17674a4 AMDGPU: [AMDGPU] Assembler: add .hsa_code_object_metadata directive for functime metadata V2.0
Summary:
Added pair of directives .hsa_code_object_metadata/.end_hsa_code_object_metadata.
Between them user can put YAML string that would be directly put to the generated note. E.g.:
'''
.hsa_code_object_metadata
    {
        amd.MDVersion: [ 2, 0 ]
    }
.end_hsa_code_object_metadata
'''
Based on D25046

Reviewers: vpykhtin, nhaustov, yaxunl, tstellarAMD

Subscribers: arsenm, kzhuravl, wdng, nhaehnle, mgorny, tony-tye

Differential Revision: https://reviews.llvm.org/D27619

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290097 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-19 11:43:15 +00:00
Diana Picus
abc24acb9f [ARM] GlobalISel: Support loading from the stack
Add support for selecting simple G_LOAD and G_FRAME_INDEX instructions (32-bit
scalars only). This will be useful for functions that need to pass arguments on
the stack.

First part of https://reviews.llvm.org/D27195.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290096 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-19 11:26:31 +00:00
Dean Michael Berris
62e99e136f [XRay] Fix assertion failure on empty machine basic blocks (PR 31424)
The original version of the code in XRayInstrumentation.cpp assumed that
functions may not have empty machine basic blocks (or that the first one
couldn't be). This change addresses that by special-casing that specific
situation.

We provide two .mir test-cases to make sure we're handling this
appropriately.

Fixes llvm.org/PR31424.

Reviewers: chandlerc

Subscribers: varno, llvm-commits

Differential Revision: https://reviews.llvm.org/D27913

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290091 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-19 09:20:38 +00:00
Daniel Jasper
47d6abcc05 Add files I seem to have dropped in my revert (r290086).
Sorry!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290087 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-19 08:32:13 +00:00
Daniel Jasper
8de3a54f07 Revert @llvm.assume with operator bundles (r289755-r289757)
This creates non-linear behavior in the inliner (see more details in
r289755's commit thread).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290086 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-19 08:22:17 +00:00
Tom de Vries
717d868685 [FileCheck] Fix --strict-whitespace --match-full-lines -- add test-case
Add test-case that was missing in "[FileCheck] Fix --strict-whitespace
--match-full-lines" commit.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290070 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-18 21:04:47 +00:00
Sanjay Patel
6fd764e6d9 [InstCombine] use commutative matchers for patterns with commutative operators
Background/motivation - I was circling back around to:
https://llvm.org/bugs/show_bug.cgi?id=28296

I made a simple patch for that and noticed some regressions, so added test cases for
those with rL281055, and this is hopefully the minimal fix for just those cases.

But as you can see from the surrounding untouched folds, we are missing commuted patterns
all over the place, and of course there are no regression tests to cover any of those cases.

We could sprinkle "m_c_" dust all over this file and catch most of the missing folds, but 
then we still wouldn't have test coverage, and we'd still miss some fraction of commuted 
patterns because they require adjustments to the match order.

I'm aware of the concern about the potential compile-time performance impact of adding 
matches like this (currently being discussed on llvm-dev), but I don't think there's any
evidence yet to suggest that handling commutative pattern matching more thoroughly is not
a worthwhile goal of InstCombine.

Differential Revision: https://reviews.llvm.org/D24419


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290067 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-18 18:49:48 +00:00
Daniel Jasper
43d95abf3f Revert r289955 and r289962. This is causing lots of ASAN failures for us.
Not sure whether it causes and ASAN false positive or whether it
actually leads to incorrect code or whether it even exposes bad code.
Hans, I'll get you instructions to reproduce this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290066 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-18 14:36:38 +00:00
Michael Zuckerman
1a2b5e0641 [X86] [AVX512] Minor fix in encoding of scalar EVEX instructions. NFC.
Commit on behalf of Gadi Haber  

Removed EVEX_V512 prefix from scalar EVEX instructions since HW ignores L'L bits anyway (LIG). 4 instructions are modified.
The changed encodings are validated with XED.
Rviewers: delena, igorb

Differential revision: https://reviews.llvm.org/D27802


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290065 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-18 14:29:00 +00:00
Simon Pilgrim
06557aae22 [X86][SSE] Add support for combining target shuffles to SHUFPS.
As discussed on D27692, the next step will be to allow cross-domain shuffles once the combined shuffle depth passes a certain point.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290064 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-18 14:26:02 +00:00
Craig Topper
abfa815607 [X86][SSE][AVX-512] Convert FAND/FOR/FXOR/FANDN nodes to integer operations if they are available. This will allow a bunch of patterns to be removed.
These nodes are only emitted for lowering FABS/FNEG/FNABS/FCOPYSIGN. Ideally we just wouldn't create these nodes if SSE2 or higher is available, but it was simple to just convert them in DAG combine.

For SSE2, AVX, and AVX512 with DQI this is no functional change as the execution domain fixing pass ensures the right domain is selected regardless of the ISD opcode.

For AVX-512 without DQI we end up using integer instructions since the floating point versions aren't available. But we were already doing that for any logical operations in code that didn't come from FABS/FNEG/FNABS/FCOPYSIGN so this seems no worse. And we get the benefit of being able to fold broadcasts now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290060 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-18 07:54:23 +00:00
Craig Topper
f28829d488 [AVX-512] Use EVEX encoded XOR instruction for zeroing scalar registers when DQI and VLX instructions are available.
This can give the register allocator more registers to use.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290057 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-18 06:23:14 +00:00
Craig Topper
cbfbeeef12 [AVX-512] Make sure VLX is also enabled before using EVEX encoded logic ops for scalars. I missed this in r290049.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290055 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-18 04:17:00 +00:00
Matt Arsenault
0f11f29f4b AMDGPU: Fix broken check prefix in test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290050 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-17 20:03:59 +00:00
Craig Topper
226ab62dea [AVX-512] Use EVEX encoded logic operations for scalar types when they are available. This gives the register allocator more registers to work with.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290049 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-17 19:26:00 +00:00
Craig Topper
9f7b68dc8e [AVX-512] Update scalar logic test to show missed opportunity to use EVEX encoded logic instructions to get more registers to use.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290048 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-17 19:25:55 +00:00
Matthias Braun
9e6cedb0a4 Revert "AArch64CollectLOH: Rewrite as block-local analysis."
It is still breaking Chrome. http://llvm.org/PR31361

This reverts commit r290026.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290047 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-17 18:53:11 +00:00
Matthias Braun
2d747dda15 Move test to correct directory
See also test/CodeGen/MIR/README

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290032 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-17 02:16:26 +00:00
Evgeniy Stepanov
0fe21065dd Revert "[GVNHoist] Move GVNHoist to function simplification part of pipeline."
This reverts r289696, which caused TSan perf regression.

See PR31382.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290030 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-17 01:53:15 +00:00
Matthias Braun
d5a8735657 AArch64CollectLOH: Rewrite as block-local analysis.
Re-apply r288561: Liveness tracking should be correct now after r290014.

Previously this pass was using up to 5% compile time in some cases which
is a bit much for what it is doing. The pass featured a full blown
data-flow analysis which in the default configuration was restricted to a
single block.

This rewrites the pass under the assumption that we only ever work on a
single block. This is done in a single pass maintaining a state machine
per general purpose register to catch LOH patterns.

Differential Revision: https://reviews.llvm.org/D27329

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290026 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-17 01:15:59 +00:00
Mike Aizatsky
77972972a3 [sancov] skip dead files from computations
Differential Revision: https://reviews.llvm.org/D27863

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290017 91177308-0d34-0410-b5e6-96231b3b80d8
2016-12-17 00:11:48 +00:00