136236 Commits

Author SHA1 Message Date
Kevin Enderby
d5adfbcabc More fixes to get good error messages for bad archives.
Fixed the last incorrect uses of llvm_unreachable() in the code
which were actually just cases of errors in the input Archives.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277540 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 22:58:55 +00:00
Sanjay Patel
a1c5f9f963 [InstCombine] replace dyn_casts with matches; NFCI
Clean-up before changing this to allow folds for vectors.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277538 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 22:38:33 +00:00
Kostya Serebryany
2ca02f6ea0 [sanitizer] Implement a __asan_default_options() equivalent for Scudo
Summary:
Currently, the Scudo Hardened Allocator only gets its flags via the SCUDO_OPTIONS environment variable.
With this patch, we offer the opportunity for programs to define their own options via __scudo_default_options() which behaves like __asan_default_options() (weak symbol).
A relevant test has been added as well, and the documentation updated accordingly.
I also used this patch as an opportunity to rename a few variables to comply with the LLVM naming scheme, and replaced a use of Report with dieWithMessage for consistency (and to avoid a callback).

Reviewers: llvm-commits, kcc

Differential Revision: https://reviews.llvm.org/D23018

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277536 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 22:25:38 +00:00
Matt Arsenault
94166e75ac AMDGPU: fdiv -1, x -> rcp -x
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277535 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 22:25:04 +00:00
Piotr Padlewski
c2a3bce22d Imported statistics types changes
Reviewers: tejohnson, eraman

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D22980

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277534 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 22:18:47 +00:00
George Burgess IV
4968ef3366 [CFLAA] Be more conservative with values we haven't seen.
There were issues with simply reporting AttrUnknown on
previously-unknown values in CFLAnders. So, we now act *entirely*
conservatively for values we haven't seen before. As in the prior patch
(r277362), writing a lit test for this isn't exactly trivial. If someone
wants a test badly, I'm willing to try to write one.

Patch by Jia Chen.

Differential Revision: https://reviews.llvm.org/D23077


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277533 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 22:17:25 +00:00
Daniel Berlin
35142a98ef Move to having a single real instructionClobbersQuery
Summary: We really want to move towards MemoryLocOrCall (or fix AA) everywhere, but for now, this lets us have a single instructionClobbersQuery.

Reviewers: george.burgess.iv

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D23072

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277530 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 21:57:52 +00:00
Rui Ueyama
9222178199 PDB: Mark extended file pages as free by default.
BitVector::extend initializes extended bits as true by default.
That is not desirable because new pages should be initially free.

Differential Revision: https://reviews.llvm.org/D23048

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277529 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 21:56:37 +00:00
Krzysztof Parzyszek
8d96db9629 [Hexagon] Recognize vcombine in copy propagation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277528 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 21:49:20 +00:00
Michael Zolotukhin
559102f2be [LoopUnroll] Fix a PowerPC test broken by r277524.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277527 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 21:43:25 +00:00
Michael Zolotukhin
9ef092dcb0 [LoopUnroll] Switch the default value of -unroll-runtime-epilog back to its original value.
As agreed in post-commit review of r265388, I'm switching the flag to
its original value until the 90% runtime performance regression on
SingleSource/Benchmarks/Stanford/Bubblesort is addressed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277524 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 21:24:14 +00:00
Lang Hames
f8cfb2fa65 [lli] Add the ability for OrcLazyJIT to accept multiple input modules.
LLI already supported passing multiple input modules to MCJIT via the
-extra-module option. This patch adds the plumbing to pass these modules to
the OrcLazy JIT too.

This functionality will be used in an upcoming test case for weak symbol
handling.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277521 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 21:00:40 +00:00
Artem Belevich
23d7717d3d [NVPTX] remove unnecessary named metadata update that happens to break debug info.
Also added test case to verify IR changes done by NVPTXGenericToNVVM pass.

Differential Revision: https://reviews.llvm.org/D22837

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277520 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 20:58:24 +00:00
Wei Mi
ba9543ccae [LoopVectorize] Change comment for isOutOfScope in collectLoopUniforms, NFC
Update comment for isOutOfScope and add a testcase for uniform value being used
out of scope.

Differential Revision: https://reviews.llvm.org/D23073


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277515 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 20:27:49 +00:00
Tim Northover
22b561a27e AArch64: properly calculate cmpxchg status in FastISel.
We were relying on the misleadingly-names $status result to actually be the
status. Actually it's just a scratch register that may or may not be valid (and
is the inverse of the real ststus anyway). Success can be determined by
comparing the value loaded against the one we wanted to see for "cmpxchg
strong" loops like this.

Should fix PR28819.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277513 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 20:22:36 +00:00
Daniel Berlin
558bab8534 Fixes for post-commit review comments on r277480
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277510 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 20:02:21 +00:00
Sanjoy Das
55fcee64a9 [IRCE] Rename variable; NFC
There is nothing "Original" about "OriginalLoopInfo".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277506 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 19:32:01 +00:00
Sanjoy Das
ee53c92338 [IRCE] Preserve DomTree and LCSSA
This changes IRCE to "preserve" LCSSA and DomTree by recomputing them.
It still does not preserve LoopSimplify.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277505 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 19:31:54 +00:00
Nicolai Haehnle
87d298325f AMDGPU: Stay in WQM for non-intrinsic stores
Summary:
Two types of stores are possible in pixel shaders: stores to memory that are
explicitly requested at the API level, and stores that are an implementation
detail of register spilling or lowering of arrays.

For the first kind of store, we must ensure that helper pixels have no effect
and hence WQM must be disabled. The second kind of store must always be
executed, because the written value may be loaded again in a way that is
relevant for helper pixels as well -- and there are no externally visible
effects anyway.

This is a candidate for the 3.9 release branch.

Reviewers: arsenm, tstellarAMD, mareko

Subscribers: arsenm, kzhuravl, llvm-commits

Differential Revision: https://reviews.llvm.org/D22675

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277504 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 19:31:14 +00:00
Albert Gutowski
3db929534b test commit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277503 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 19:25:17 +00:00
Michael Zolotukhin
bc280d0f4f [LoopUnroll] Ensure we create prolog loops in simplified form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277502 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 19:19:31 +00:00
Nirav Dave
0fa8922515 Fix handling of end-of-line preprocessor comments Attempt 2
Attempt 2: Retryign after Tsan.mman test fix.

Attempt 1: Recommitting after fixing test.

When parsing assembly where the line comment syntax is not hash, the
lexer cannot distinguish between hash's that start a hash line comment
and one that is part of an assembly statement and must be distinguished
during parsing. Previously, this was incompletely handled by not checking
for EndOfStatement at the end of statements and interpreting hash
prefixed statements as comments.

Change EndOfStatement Parsing to check for Hash comments and reintroduce
Hash statement parsing to catch previously handled cases.

Reviewers: rnk, majnemer

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D23017

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277501 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 19:17:54 +00:00
Nicolai Haehnle
a8461187eb AMDGPU: Track physical registers in SIWholeQuadMode
Summary:
There are cases where uniform branch conditions are computed in VGPRs, and
we didn't correctly mark those as WQM.

The stray change in basic-branch.ll is because invoking the LiveIntervals
analysis leads to the detection of a dead register that would otherwise not
be seen at -O0.

This is a candidate for the 3.9 branch, as it fixes a possible hang.

Reviewers: arsenm, tstellarAMD, mareko

Subscribers: arsenm, llvm-commits, kzhuravl

Differential Revision: https://reviews.llvm.org/D22673

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277500 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 19:17:37 +00:00
Ahmed Bougacha
af5f07500c [AArch64][GlobalISel] Replace test REQUIRES with lit.local.cfg. NFC.
I forgot the REQUIRES once (see r277486).
Let's prevent it from happening again.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277499 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 19:04:29 +00:00
Ahmed Bougacha
9ce2f98aaa [AArch64] Remove useless 'import re' from CodeGen lit.local.cfg. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277498 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 19:04:25 +00:00
Krzysztof Parzyszek
1b1291fbbb [Hexagon] Prefer _io over _rr for 64-bit store with constant offset
Identify patterns where the address is aligned to an 8-byte boundary,
but both the base address and the constant offset are both proper
multiples of 4. In such cases, extract Base+4 into a separate instruc-
tion, and use S2_storerd_io, instead of using S4_storerd_rr.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277497 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 18:50:05 +00:00
Krzysztof Parzyszek
aeac124408 [Hexagon] Remove unused option
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277496 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 18:39:32 +00:00
Krzysztof Parzyszek
a4e94ebbb2 [Hexagon] Improvements to address mode checks in TargetLowering
- Implement getOptimalMemOpType.
- Check BaseOffset in isLegalAddressingMode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277494 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 18:34:31 +00:00
Nirav Dave
c37e7b92f8 [MC] Fix Intel Operand assembly parsing for .set ids
Recommitting after fixing overaggressive fastpath return in parsing.

Fix intel syntax special case identifier operands that refer to a constant
(e.g. .set <ID> n) to be interpreted as immediate not memory in parsing.

Associated commit to fix clang test commited shortly.

Reviewers: rnk

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D22585

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277489 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 17:56:03 +00:00
Ahmed Bougacha
93a0b1235f [AArch64][GlobalISel] Add REQUIRES: global-isel to verifier tests.
I thought the directory had a lit.local.cfg, but it doesn't.
I'll add one, but for now, add the REQUIRES line. While there,
move the triple into the IR and add a datalayout.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277486 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 17:19:35 +00:00
Daniel Berlin
c1f8f3a65f MSVC 2013 does not implement C++11 unions properly, so remove the anoymous union for now,
and leave a FIXME.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277485 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 16:59:51 +00:00
Ahmed Bougacha
9618468f1c [GlobalISel] Set the Selected MF property.
None of GlobalISel requires the property, but this lets us use the
verifier instead of rolling our own "all instructions selected" check.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277484 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 16:49:25 +00:00
Ahmed Bougacha
35426be67b [GlobalISel] Verify Selected MF property.
After instruction selection, there should be no pre-isel generic
instructions remaining, nor should generic virtual registers be
used. Verify that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277483 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 16:49:22 +00:00
Ahmed Bougacha
fc114db3c4 [GlobalISel] Add Selected MachineFunction property.
Selected: the InstructionSelect pass ran and all pre-isel generic
instructions have been eliminated; i.e., all instructions are now
target-specific or non-pre-isel generic instructions (e.g., COPY).

Since only pre-isel generic instructions can have generic virtual register
operands, this also means that all generic virtual registers have been
constrained to virtual registers (assigned to register classes) and that
all sizes attached to them have been eliminated.

This lets us enforce certain invariants across passes.
This property is GlobalISel-specific, but is always available.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277482 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 16:49:19 +00:00
Daniel Berlin
c32071c252 Rewrite the use optimizer to be less memory intensive and 50% faster.
Fixes PR28670

Summary:
Rewrite the use optimizer to be less memory intensive and 50% faster.
Fixes PR28670

The new use optimizer works like a standard SSA renaming pass, storing
all possible versions a MemorySSA use could get in a stack, and just
tracking indexes into the stack.
This uses much less memory than caching N^2 alias query results.
It's also a lot faster.

The current version defers phi node walking to the normal walker.

Reviewers: george.burgess.iv

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D23032

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277480 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 16:24:03 +00:00
Artur Pilipenko
e2e5c0738c [LVI] NFC. Sink a condition type check from the caller down to getValueFromCondition
This is a preparatory refactoring to support conditions other than ICmpInst.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277479 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 16:20:48 +00:00
Ahmed Bougacha
7abac75bf9 [GlobalISel] Set and require RegBankSelected MF property.
The InstructionSelect pass assumes that RegBankSelect ran; set the
property on all tests (thereby verifying the test inputs) and require
it in the pass.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277477 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 16:17:18 +00:00
Ahmed Bougacha
1f82c34de8 [GlobalISel] Verify RegBankSelected MF property.
RegBankSelected functions shouldn't have any generic virtual
register not assigned to a bank. Verify that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277476 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 16:17:15 +00:00
Ahmed Bougacha
31c3e4f363 [GlobalISel] Add RegBankSelected MachineFunction property.
RegBankSelected: the RegBankSelect pass ran and all generic virtual
registers have been assigned to a register bank.

This lets us enforce certain invariants across passes.
This property is GlobalISel-specific, but is always available.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277475 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 16:17:10 +00:00
Matthew Simpson
155b8551c6 [LV] Generate both scalar and vector integer induction variables
This patch enables the vectorizer to generate both scalar and vector versions
of an integer induction variable for a given loop. Previously, we only
generated a scalar induction variable if we knew all its users were going to be
scalar. Otherwise, we generated a vector induction variable. In the case of a
loop with both scalar and vector users of the induction variable, we would
generate the vector induction variable and extract scalar values from it for
the scalar users. With this patch, we now generate both versions of the
induction variable when there are both scalar and vector users and select which
version to use based on whether the user is scalar or vector.

Differential Revision: https://reviews.llvm.org/D22869

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277474 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 15:25:16 +00:00
Ahmed Bougacha
d170182063 [GlobalISel] Set, require, and verify Legalized MF property.
RegBankSelect and InstructionSelect run after the legalizer and
require a Legalized function: check that all instructions are legal.

Note that this should be in the MachineVerifier, but it can't use the
MachineLegalizer as it's currently in the separate GlobalISel library.
Note that the RegBankSelect verifier checks have the same layering
problem, but we only use inline methods so end up not needing to link
against the GlobalISel library.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277472 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 15:10:32 +00:00
Ahmed Bougacha
a877bb83bf [AArch64][GlobalISel] Mark basic binops/memops as legal.
We currently use and test these, and select most of them. Mark them
as legal even though we don't go through the full ir->asm flow yet.

This doesn't currently have standalone tests, but the verifier will
soon learn to check that the regbankselect/select tests are legal.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277471 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 15:10:28 +00:00
Ahmed Bougacha
46fe427fc7 [GlobalISel] Add Legalized MachineFunction property.
Legalized: The MachineLegalizer ran; all pre-isel generic instructions
have been legalized, i.e., all instructions are now one of:
  - generic and always legal (e.g., COPY)
  - target-specific
  - legal pre-isel generic instructions.

This lets us enforce certain invariants across passes.
This property is GlobalISel-specific, but is always available.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277470 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 15:10:25 +00:00
Nirav Dave
07d957665f Revert "[MC] Fix handling of end-of-line preprocessor comments"
Causes TSan failure on PPC64

This reverts commit r277459.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277468 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 15:08:52 +00:00
Dan Gohman
143e93e010 [WebAssembly] Remove a README.txt entry that is now implemented.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277467 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 14:53:44 +00:00
Artur Pilipenko
e6be5e76b2 [LVI] NFC. Fix a typo getValueFromFromCondition -> getValueFromCondition
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277466 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 14:44:32 +00:00
Ahmed Bougacha
3797d93a1e [CodeGen] Generalize MachineFunctionProperties::print comma handling.
This is only used for debug prints, but the previous hardcoded ", "
caused it to be printed unnecessarily when OnlySet, and is annoying
when adding new properties.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277465 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 14:42:57 +00:00
Ahmed Bougacha
6a35fcace7 [GlobalISel] Require isSSA in GISel passes.
The GISel passes don't make sense on non-SSA functions.
All GISel tests already set isSSA. Enforce that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277464 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 14:42:55 +00:00
Matthew Simpson
90b7f569d8 [LV] Untangle the concepts of uniform and scalar
This patch refactors the logic in collectLoopUniforms and
collectValuesToIgnore, untangling the concepts of "uniform" and "scalar". It
adds isScalarAfterVectorization along side isUniformAfterVectorization to
distinguish the two. Known scalar values include those that are uniform,
getelementptr instructions that won't be vectorized, and induction variables
and induction variable update instructions whose users are all known to be
scalar.

This patch includes the following functional changes:

- In collectLoopUniforms, we mark uniform the pointer operands of interleaved
  accesses. Although non-consecutive, these pointers are treated like
  consecutive pointers during vectorization.

- In collectValuesToIgnore, we insert a value into VecValuesToIgnore if it
  isScalarAfterVectorization rather than isUniformAfterVectorization. This
  differs from the previous functionaly in that we now add getelementptr
  instructions that will not be vectorized into VecValuesToIgnore.

This patch also removes the ValuesNotWidened set used for induction variable
scalarization since, after the above changes, it is now equivalent to
isScalarAfterVectorization.

Differential Revision: https://reviews.llvm.org/D22867

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277460 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 14:29:41 +00:00
Nirav Dave
22973d396c [MC] Fix handling of end-of-line preprocessor comments
Recommitting after fixing test.

When parsing assembly where the line comment syntax is not hash, the
lexer cannot distinguish between hash's that start a hash line comment
and one that is part of an assembly statement and must be distinguished
during parsing. Previously, this was incompletely handled by not checking
for EndOfStatement at the end of statements and interpreting hash
prefixed statements as comments.

Change EndOfStatement Parsing to check for Hash comments and reintroduce
Hash statement parsing to catch previously handled cases.

Reviewers: rnk, majnemer

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D23017

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277459 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 14:25:49 +00:00