147304 Commits

Author SHA1 Message Date
Reid Kleckner
3282f4edba [lit] Revert to old execution strategy while I debug these pickling errors
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299565 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-05 17:16:37 +00:00
Reid Kleckner
3f58a16d8e [lit] Use Python 3 style print to satisfy some bots
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299564 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-05 17:05:31 +00:00
Matthias Braun
5b76b2964c ARMFrameLowering: Slight cleanups; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299562 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-05 16:58:41 +00:00
Reid Kleckner
e514965f7e [lit] Use process pools for test execution by default
Summary:
This drastically reduces lit test execution startup time on Windows. Our
previous strategy was to manually create one Process per job and manage
the worker pool ourselves. Instead, let's use the worker pool provided
by multiprocessing.  multiprocessing.Pool(jobs) returns almost
immediately, and initializes the appropriate number of workers, so they
can all start executing tests immediately. This avoids the ramp-up
period that the old implementation suffers from.  This appears to speed
up small test runs.

Here are some timings of the llvm-readobj tests on Windows using the
various execution strategies:

 # multiprocessing.Pool:
$ for i in `seq 1 3`; do tim python ./bin/llvm-lit.py -sv ../llvm/test/tools/llvm-readobj/ --use-process-pool |& grep real: ; done
real: 0m1.156s
real: 0m1.078s
real: 0m1.094s

 # multiprocessing.Process:
$ for i in `seq 1 3`; do tim python ./bin/llvm-lit.py -sv ../llvm/test/tools/llvm-readobj/ --use-processes |& grep real: ; done
real: 0m6.062s
real: 0m5.860s
real: 0m5.984s

 # threading.Thread:
$ for i in `seq 1 3`; do tim python ./bin/llvm-lit.py -sv ../llvm/test/tools/llvm-readobj/ --use-threads |& grep real: ; done
real: 0m9.438s
real: 0m10.765s
real: 0m11.079s

I kept the old code to launch processes in case this change doesn't work
on all platforms that LLVM supports, but at some point I would like to
remove both the threading and old multiprocessing execution strategies.

Reviewers: modocache, rafael

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D31677

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299560 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-05 16:44:56 +00:00
Renato Golin
9331ebeba7 [ARM] Try to re-enable MachineBranchProb.ll for ARM/AArch64
Commit r298799 changed code that made the XFAIL on MachineBranchProb.ll
irrelevant, but some configurations still failed. I can't reproduce it
locally, so I'm hoping that enabling this will tell me if some
configurations will really fail or if they were just too slow.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299558 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-05 16:27:11 +00:00
Sanjay Patel
81a71c4756 [InstCombine] add tests for missing icmp fold (PR32524)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299557 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-05 16:21:38 +00:00
Dmitry Preobrazhensky
8067b87e5f [AMDGPU][MC] Fix for Bug 28167 + LIT tests
Corrected src0 for v_writelane_b32:
- Enabled inline constants and literals for SI/CI (VOP2)
- Enabled inline constants for VI (VOP3)

Reviewers: vpykhtin, arsenm

https://reviews.llvm.org/D31463

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299555 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-05 16:08:21 +00:00
Nirav Dave
af1205bfae [SystemZ] Prevent Merging Bitcast with non-normal loads
Fixes PR32505.

Reviewers: uweigand, jonpa

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D31609

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299552 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-05 15:42:48 +00:00
Davide Italiano
6bc97db3ed [yaml2obj] Factor out error handling code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299551 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-05 15:18:16 +00:00
Davide Italiano
cfe642f7ae [llvm-ar] Remove unneeded std::, NFCI.
This makes it more consistent with other exit() calls in llvm-ar
(and the tools in general).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299549 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-05 15:05:05 +00:00
Davide Italiano
6edf98cd9d [llvm-ar] errors go on stderr and not on stdout.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299548 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-05 14:52:17 +00:00
Jonathan Roelofs
50982d318e Respect CMAKE_INSTALL_MANDIR for sphinx generated manpages
This is a re-work of r297516, which was reverted in r297545.

https://reviews.llvm.org/D30906


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299547 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-05 14:49:46 +00:00
Davide Italiano
4561efc963 [yaml2obj] Improve error message when output file cannot be opened.
Patch by Sam Clegg!

Differential Revision:  https://reviews.llvm.org/D31351

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299546 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-05 14:44:00 +00:00
Matthew Simpson
a9eefb0375 [LV] Make test case more robust
This test case depends on the loop being vectorized without forcing the
vectorization factor. If the profitability ever changes in the future (due to
cost model improvements), the test may no longer work as intended. Instead of
checking the resulting IR, we should just check the instruction costs. The
costs will be computed regardless if vectorization is profitable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299545 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-05 14:34:13 +00:00
Sanjay Patel
a070c921e5 [DAGCombiner] add and use TLI hook to convert and-of-seteq / or-of-setne to bitwise logic+setcc (PR32401)
This is a generic combine enabled via target hook to reduce icmp logic as discussed in:
https://bugs.llvm.org/show_bug.cgi?id=32401

It's likely that other targets will want to enable this hook for scalar transforms, 
and there are probably other patterns that can use bitwise logic to reduce comparisons.

Note that we are missing an IR canonicalization for these patterns, and we will probably
prefer the pair-of-compares form in IR (shorter, more likely to fold).

Differential Revision: https://reviews.llvm.org/D31483



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299542 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-05 14:09:39 +00:00
Jonas Paulsson
4a035b600a [DAGCombiner] Don't make a BUILD_VECTOR with operands of illegal type.
When DAGCombiner visits a SIGN_EXTEND_INREG of a BUILD_VECTOR with
constant operands, a new BUILD_VECTOR node will be created transformed
constants.

Llvm-stress found a case where the new BUILD_VECTOR had constant operands
of an illegal type, because the (legal) element type is in fact not a legal
scalar type.

This patch changes this so that the new BUILD_VECTOR has the same operand
type as the old one.

Review: Eli Friedman, Nirav Dave
https://bugs.llvm.org//show_bug.cgi?id=32422

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299540 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-05 13:45:37 +00:00
Sanjay Patel
0a06935a2e [InstCombine] add tests for missing add canonicalization; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299539 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-05 13:33:10 +00:00
Daniel Sanders
be2d374747 [globalisel][tablegen] Fix patterns involving multiple ComplexPatterns.
Summary:
Temporaries are now allocated to operands instead of predicates and this
allocation is used to correctly pair up the rendered operands with the
matched operands.

Previously, ComplexPatterns were allocated temporaries independently in the
Src Pattern and Dst Pattern, leading to mismatches. Additionally, the Dst
Pattern failed to account for the allocated index and therefore always used
temporary 0, 1, ... when it should have used base+0, base+1, ...

Thanks to Aditya Nandakumar for noticing the bug.

Depends on D30539

Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar

Reviewed By: rovka

Subscribers: igorb, dberris, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D31054

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299538 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-05 13:14:03 +00:00
Sam Kolton
4523389543 [AMDGPU] SDWA peephole: enable by default
Reviewers: vpykhtin, rampitec, arsenm

Subscribers: qcolombet, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye

Differential Revision: https://reviews.llvm.org/D31671

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299536 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-05 12:00:45 +00:00
Alexander Kornienko
9544eb39b6 Fix WebAssembly after r299529.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299535 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-05 11:50:43 +00:00
Simon Pilgrim
a71e6d97d5 [X86][SSE] Renamed combine to make it clear that it only handles the vector shift by immediate opcodes. NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299532 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-05 10:44:42 +00:00
James Molloy
f05816007b [AArch64] Crypto requires FP.
So if FP is disabled, crypto should also be disabled.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299531 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-05 10:44:38 +00:00
Alex Bradbury
ff1254b6f8 Add MCContext argument to MCAsmBackend::applyFixup for error reporting
A number of backends (AArch64, MIPS, ARM) have been using
MCContext::reportError to report issues such as out-of-range fixup values in
their TgtAsmBackend. This is great, but because MCContext couldn't easily be
threaded through to the adjustFixupValue helper function from its usual
callsite (applyFixup), these backends ended up adding an MCContext* argument
and adding another call to applyFixup to processFixupValue. Adding an
MCContext parameter to applyFixup makes this unnecessary, and even better -
applyFixup can take a reference to MCContext rather than a potentially null
pointer.

Differential Revision: https://reviews.llvm.org/D30264


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299529 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-05 10:16:14 +00:00
James Molloy
3a168569fc [LAA] Correctly return a half-open range in expandBounds
This is a latent bug that's been hanging around for a while. For a loop-invariant
pointer, expandBounds would return the range {Ptr, Ptr}, but this was interpreted
as a half-open range, not a closed range. So we ended up planting incorrect
bounds checks. Even worse, they were tautological, so we ended up incorrectly
executing the optimized loop.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299526 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-05 09:24:26 +00:00
Gor Nishanov
f202abfbd6 [coroutines] Add syntax coloring to examples in Coroutines.rst
Subscribers: EricWF

Differential Revision: https://reviews.llvm.org/D31699

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299517 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-05 05:26:26 +00:00
Akira Hatanaka
1115fbdce4 [ObjCArc] Do not dereference an invalidated iterator.
Fix a bug in ARC contract pass where an iterator that pointed to a
deleted instruction was dereferenced.

It appears that tryToContractReleaseIntoStoreStrong was incorrectly
assuming that a call to objc_retain would not immediately follow a call
to objc_release.

rdar://problem/25276306



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299507 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-05 03:44:09 +00:00
Lang Hames
9be01ddb13 [RuntimeDyld] Remove an unused static member left over from r299449.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299497 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-05 01:43:59 +00:00
Bob Haarman
ed735da23f ThinLTOBitcodeWriter: handle aliases first in filterModule
Summary: This change fixes a "local linkage requires default visibility" assert when attempting to build LLVM with ThinLTO on Windows.

Reviewers: pcc, tejohnson, mehdi_amini

Reviewed By: pcc

Subscribers: llvm-commits, Prazek

Differential Revision: https://reviews.llvm.org/D31632


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299491 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-05 00:42:07 +00:00
Ahmed Bougacha
e339e10540 [X86] Relax assert in broadcast-of-subvector lowering.
Before r294774, there was a problem when lowering broadcasts to use
128-bit subvectors.

When we looked through a bitcast to find the broadcast input, we'd keep
using the original type, so you'd end up with things like:
  (v8f32 (broadcast
    (v4f32 (extract_subvector
      (v8i32 V),
      ...))
    ))

r294774 fixed it to always emit subvectors with the scalar type of the
original source.

It also introduced some asserts, to check that we use scalars with
the same size, and vectors with the same number of elements.

The scalar size equality is checked earlier when looking through bitcasts,
and is a useful assert.

However, the number of elements don't have to be identical: we're always
going to extract a 128-bit subvector, and we can have different size
inputs if we looked through a concat_vector to find a 256-bit source.

Relax the overzealous assert.

Replace it with a check of the original source vector being 256 or 512
bits.  If it's 128 bits, we can't extract_subvector from it.

Fixes PR32371.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299490 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-05 00:14:39 +00:00
Matt Arsenault
73135b623b Allow targets to opt-in to codegen in SCC order
Decouple this setting from EnableIRPA.

To support function calls on AMDGPU, it is necessary to
report the global register usage throughout the kernel's
call graph, so callees need to be handled first.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299487 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-04 23:44:46 +00:00
Daniel Berlin
4977b97dfc Re-apply MemorySSA: Add support for caching clobbering access in
stores with some fixes.

Summary:
This enables us to cache the clobbering access for stores, despite the
fact that we can't rewrite the use-def chains themselves.

Early testing shows that, after this change, for larger testcases, it
will be a significant net positive (memory and time) to remove the
walker caching.

Reviewers: george.burgess.iv, davide

Subscribers: Prazek, llvm-commits

Differential Revision: https://reviews.llvm.org/D31567

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299486 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-04 23:43:10 +00:00
Daniel Berlin
d8050a7d38 Revert "MemorySSA: Add support for caching clobbering access in stores"
This reverts revision r299322.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299485 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-04 23:43:04 +00:00
Petr Hosek
802fcd9c3e [MC] Set defaults based on section names and support name suffixes
Set correct default flags and section type based on its name for .text,
.data, .bss, .init_array, .fini_array, .preinit_array, .tdata, and .tbss
and support section name suffixes for .data.*, .rodata.*, .text.*,
.bss.*, .tdata.* and .tbss.* which matches the behavior of GAS.

Fixes PR31888.

Differential Revision: https://reviews.llvm.org/D30229

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299484 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-04 23:32:45 +00:00
Ahmed Bougacha
6f50c7fe4a [AArch64] Avoid partial register deps on insertelt of load into lane 0.
This improves upon r246462: that prevented FMOVs from being emitted
for the cross-class INSERT_SUBREGs by disabling the formation of
INSERT_SUBREGs of LOAD.  But the ld1.s that we started selecting
caused us to introduce partial dependencies on the vector register.

Avoid that by using SCALAR_TO_VECTOR: it's a first-class citizen that
is folded away by many patterns, including the scalar LDRS that we
want in this case.

Credit goes to Adam for finding the issue!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299482 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-04 22:55:53 +00:00
Evgeniy Stepanov
8719ab145a Change section flag character for SHF_LINK_ORDER to "o".
GAS uses "m" as a compatibility alias for "M" (SHF_MERGE).

"o" is free, except on ia64, where it already means SHF_LINK_ORDER.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299479 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-04 22:35:08 +00:00
Craig Topper
862117b6f4 [InstCombine] Add test cases for various add/subtracts of constants(scalar, splat, and vector) with phis and selects. Improvements coming in a future commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299476 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-04 22:22:30 +00:00
Rafael Espindola
7cc76f28bd [lit] Add a minimum export implementation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299475 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-04 22:20:18 +00:00
Sanjay Patel
828ad8830a [InstCombine] rename variable for easier reading; NFC
We usually give constants a 'C' somewhere in the name...


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299474 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-04 22:06:03 +00:00
Craig Topper
7597f2aad7 [InstCombine] Turn subtract of vectors of i1 into xor like we do for scalar i1. Matches what we already do for add.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299472 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-04 21:44:56 +00:00
Balaram Makam
340999bcb9 [AArch64] Add missing schedinfo, check completeness for Falkor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299468 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-04 21:15:53 +00:00
Keno Fischer
54eda94389 [ExecutionDepsFix] Don't revisit true dependencies
If an instruction has a true dependency, it makes sense for to use that
register for any undef read operands in the same instruction (we'll have
to wait for that register to become available anyway). This logic
was already implemented. However, the code would then still try to
revisit that instruction and break the dependency (and always fail,
since by definition a true dependency has to be live before the
instruction). Avoid revisiting such instructions as a performance
optimization. No functional change.

Differential Revision: https://reviews.llvm.org/D30173

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299467 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-04 20:30:47 +00:00
Craig Topper
d6c407ebd6 [InstCombine] Support folding and/or/xor with a constant vector RHS into selects and phis
Currently we only fold with ConstantInt RHS. This generalizes to any Constant RHS.

Differential Revision: https://reviews.llvm.org/D31610



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299466 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-04 20:26:25 +00:00
Petr Hosek
75d650872f [AArch64][Fuchsia] Allow -mcmodel=kernel for --target=aarch64-fuchsia
This mode is just like -mcmodel=small except that it moves the
thread pointer from TPIDR_EL0 to TPIDR_EL1.

Patch by Roland McGrath.

Differential Revision: https://reviews.llvm.org/D31624

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299462 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-04 19:51:53 +00:00
Craig Topper
80bfe66e42 [InstCombine] Add test cases for missing combines of phis with and/or/xor with constant argument. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299460 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-04 19:31:21 +00:00
Yi Kong
4dd33e6269 Implement host CPU detection for AArch64
This shares detection logic with ARM(32), since AArch64 capable CPUs may
also run in 32-bit system mode.

We observe weird /proc/cpuinfo output for MSM8992 and MSM8994, where
they report all CPU cores as one single model, depending on which CPU
core the kernel is running on. As a workaround, we hardcode the known
CPU part name for these SoCs.

For big.LITTLE systems, this patch would only return the part name of
the first core (usually the little core). Proper support will be added
in a follow-up change.

Differential Revision: D31675

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299458 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-04 19:06:04 +00:00
Matt Arsenault
dce3b51aea Verifier: Check some amdgpu calling convention restrictions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299457 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-04 18:43:11 +00:00
Balaram Makam
5d76ab9dec [AArch64] Refine Falkor Machine Model - Part 2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299456 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-04 18:42:14 +00:00
Coby Tayree
983e1a1b99 [X86][inline-asm] Add support for MS 'EVEN' directive
MS assembly syntax provide us with the 'EVEN' directive as a synonymous to at&t '.even'.
This patch include the (small, simple) changes need to allow it.

Test is provided at the following (clang-side) review:
https://reviews.llvm.org/D27418

Differential Revision: https://reviews.llvm.org/D27417



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299453 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-04 17:57:23 +00:00
Craig Topper
c1eaf3a1f1 [InstCombine] Add more test cases for missing combines of selects with and/or/xor with constant argument. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299450 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-04 17:48:08 +00:00
Lang Hames
e65aa1c44e [RuntimeDyld] Make RuntimeDyld honor the ProcessAllSections flag.
When the ProcessAllSections flag (introduced in r204398) is set RuntimeDyld is
supposed to make a call to the client's memory manager for every section in each
object that is loaded. Due to some missing checks, this was not happening in all
cases. This patch adds the missing cases, and fixes the Orc unit test that
verifies correct behavior for ProcessAllSections (The unit test had been
silently bailing out due to an ordering issue: a change in the test order meant
that this unit-test was running before the native target was registered. This
issue has also been fixed in this patch).

This fixes <rdar://problem/22789965>



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299449 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-04 17:03:49 +00:00