Commit Graph

150903 Commits

Author SHA1 Message Date
Guy Blank
415c667680 [DAGCombiner] Add another combine from build vector to shuffle
Add support for combining a build vector to a shuffle.
When the build vector is of extracted elements from 2 vectors (vec1, vec2) where vec2 is 2 times smaller than vec1.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305883 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-21 07:38:41 +00:00
Max Kazantsev
a0c83f81b9 [SCEV] Make MulOpsInlineThreshold lower to avoid excessive compilation time
MulOpsInlineThreshold option of SCEV is defaulted to 1000, which is inadequately high.
When constructing SCEVs of expressions like:

  x1 = a * a
  x2 = x1 * x1
  x3 = x2 * x2
    ...

We actually have huge SCEVs with max allowed amount of operands inlined.
Such expressions are easy to get from unrolling of loops looking like

  x = a
  for (i = 0; i < n; i++)
    x = x * x

Or more tricky cases where big powers are involved. If some non-linear analysis
tries to work with a SCEV that has 1000 operands, it may lead to excessively long
compilation. The attached test does not pass within 1 minute with default threshold.

This patch decreases its default value to 32, which looks much more reasonable if we
use analyzes with complexity O(N^2) or O(N^3) working with SCEV.

Differential Revision: https://reviews.llvm.org/D34397


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305882 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-21 07:28:13 +00:00
Rafael Espindola
6716382e29 Simplify test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305881 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-21 06:42:56 +00:00
Dean Michael Berris
e479ac85d5 [XRay] Reduce synthetic references emitted by XRay
Summary:
When we're building with XRay instrumentation, we use a trick that
preserves references from the function to a function sled index. This
index table lives in a separate section, and without this trick the
linker is free to garbage-collect this section and all the segments it
refers to. Until we're able to tell the linkers to preserve these
sections, we use this reference trick to keep around both the index and
the entries in the instrumentation map.

Before this change we emitted both a synthetic reference to the label in
the instrumentation map, and to the entry in the function map index.
This change removes the first synthetic reference and only emits one
synthetic reference to the index -- the index entry has the references
to the labels in the instrumentation map, so the linker will still
preserve those if the function itself is preserved.

This reduces the amount of synthetic references we emit from 16 bytes to
just 8 bytes in x86_64, and similarly to other platforms.

Reviewers: dblaikie

Subscribers: javed.absar, kpw, pelikan, llvm-commits

Differential Revision: https://reviews.llvm.org/D34340

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305880 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-21 06:39:42 +00:00
Serguei Katkov
608be862ff [ImplicitNullChecks] Uphold an invariant in areMemoryOpsAliased
Right now areMemoryOpsAliased has an assertion justified as:

MMO1 should have a value due it comes from operation we'd like to use
as implicit null check.
assert(MMO1->getValue() && "MMO1 should have a Value!");
However, it is possible for that invariant to not be upheld in the
following situation (conceptually):

Null check %RAX
NotNullSucc:

%RAX = LEA %RSP, 16            // I0
%RDX = MOV64rm %RAX            // I1
With the current code, we will have an early exit from
ImplicitNullChecks::isSuitableMemoryOp on I0 with SR_Unsuitable.
However, I1 will look plausible (since it loads from %RAX) and
will go ahead and call areMemoryOpsAliased(I1, I0). This will cause
us to fail the assert mentioned above since I1 does not load from an
IR level value and thus is allowed to have a non-Value base address.

The fix is to bail out earlier whenever we see an unsuitable
instruction overwrite PointerReg. This would guarantee that when we
call areMemoryOpsAliased, we're guaranteed to be looking at an
instruction that loads from or stores to an IR level value.

Original Patch Author: sanjoy
Reviewers: sanjoy, mkazantsev, reames
Reviewed By: sanjoy
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D34385


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305879 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-21 06:38:23 +00:00
Davide Italiano
84fac2c58c [NewGVN] Fix a bug that made the store verifier less effective.
We weren't actually checking for duplicated stores, as the condition
was always actually false. This was found by Coverity, and I have
no clue how to trigger this in real-world code (although I
 tried for a bit).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305867 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-20 22:57:40 +00:00
Kevin Enderby
f8a3ad7e76 Updated llvm-objdump with Mach-O files and the -objc-meta-data option so
that it symbolically prints the superclass when it has dyld bind info for it.

rdar://7638823


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305866 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-20 22:55:11 +00:00
Rafael Espindola
7188ced755 clang-format a region.
It will make a followup patch easier to read.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305865 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-20 22:53:29 +00:00
Lang Hames
16d0f5a96b Add a cantFail overload for Expected-reference (Expected<T&>) types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305863 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-20 22:18:02 +00:00
Reid Kleckner
09ff5f277b [codeview] YAMLize all section offsets and indices in symbol records
We forgot to serialize these because llvm-readobj didn't dump them. They
are typically all zeros in an object file. The linker fills them in with
relocations before adding them to the PDB. Now we can properly round
trip these symbols through pdb2yaml -> yaml2pdb.

I made these fields optional with a zero default so that we can elide
them from our test cases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305857 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-20 21:19:22 +00:00
Adrian Prantl
c843d3c027 Revert "Add previously accidentally uncommitted testcase for r305599."
This reverts commit r305852.

The testcase already exists but I moved it to the X86 directory on a
using a different machine and got confused...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305856 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-20 21:14:29 +00:00
Rafael Espindola
7e23430b99 Make this test a bit more strict. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305855 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-20 21:11:58 +00:00
Adrian Prantl
5773fa6550 Fix a crash in DwarfDebug::validThroughout.
The instruction it falls over on is an IMPLICT_DEF that also happens
to be the only instruction in its lexical scope. That LexicalScope has
never been created because its range is empty. This patch skips over
all meta-instructions instead of just DBG_VALUEs.

Thanks to David Blaikie for providing a testcase!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305853 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-20 21:08:52 +00:00
Adrian Prantl
7b0eca9819 Add previously accidentally uncommitted testcase for r305599.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305852 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-20 21:08:19 +00:00
Kevin Enderby
21b864cd12 Change llvm-objdump with Mach-O files and the -info-plist option with the
-no-leading-headers option so that it does not print the leading header.

rdar://27378808


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305849 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-20 21:00:25 +00:00
Anna Thomas
076f819db2 [Statepoint] Add helper functions for GCRelocate and GCResult
These functions isGCRelocate and isGCResult are
similar to isStatepoint(const Value*).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305847 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-20 20:54:57 +00:00
Saleem Abdulrasool
ce9c73a84d Support: chunk writing on Linux
This is a workaround for large file writes.  It has been witnessed that
write(2) failing with EINVAL (22) due to a large value (>2G).  Thanks to
James Knight for the help with coming up with a sane test case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305846 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-20 20:51:51 +00:00
Matt Arsenault
84b3660bac AMDGPU: Allow vectorization of packed types
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305844 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-20 20:38:06 +00:00
Reid Kleckner
d3be377704 [codeview] Fully initialize DataSym when mapping from YAML
In the object file, the section index and relative offset are typically
zero, so make these YAML fields optional with a default.

It looks like there may be more partially initialized symbol records,
but this should fix the msan bot.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305842 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-20 20:34:37 +00:00
Stanislav Mekhanoshin
64373efcab [AMDGPU] Fix illegal shrink of V_SUBB_U32 and V_ADDC_U32
If there is an immediate operand we shall not shrink V_SUBB_U32
and V_ADDC_U32, it does not fit e32 encoding.

Differential Revison: https://reviews.llvm.org/D34291

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305840 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-20 20:33:44 +00:00
Michael Gottesman
864e349715 [cmake] Add support for using the standalone leaks sanitizer with LLVM.
This commit causes LLVM_USE_SANITIZER to now accept the "Leaks" option. This
will cause cmake to pass in -fsanitize=leak in all of the appropriate places.

I am making this change so that I can setup a linux bot that only detects
leaks.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305839 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-20 20:28:07 +00:00
Matt Arsenault
f958f31ecf AMDGPU: Start adding global_* instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305838 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-20 19:54:14 +00:00
Aditya Nandakumar
e669404357 [GISel]: NFC. Add comment to G_FMA opcode as requested in rL305824
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305837 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-20 19:52:29 +00:00
Aditya Nandakumar
c7c608fe5e [GISel]: Add G_FMA opcode for fused multiply adds
https://reviews.llvm.org/D34372

Reviewed by dsanders

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305824 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-20 19:25:23 +00:00
Matt Arsenault
5516bd1387 AMDGPU: Do operand folding in program order
Before it was possible to partially fold use instructions
before the defs. After the xor is folded into a copy, the same
mov can end up in the fold list twice, so on the second attempt
it will fail expecting to see a register to fold.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305821 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-20 18:56:32 +00:00
Zachary Turner
6ebce80ed1 [PDB] Don't write uninitialized bytes to a PDB file.
There were certain fields that we didn't know how to write, as
well as various padding bytes that we would ignore.  This leads
to garbage data in the PDB.  While not strictly necessary, we
should initialize these bytes to something meaningful, as it
makes for easier binary comparison between PDBs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305819 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-20 18:50:55 +00:00
Zachary Turner
d6d2feb9a7 Remove diff pedantic mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305818 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-20 18:50:30 +00:00
Matthias Braun
0cc137e051 RegisterScavenging: Followup to r305625
This does some improvements/cleanup to the recently introduced
scavengeRegisterBackwards() functionality:

- Rewrite findSurvivorBackwards algorithm to use the existing
  LiveRegUnit::accumulateBackward() code. This also avoids the Available
  and Candidates bitset and just need 1 LiveRegUnit instance
  (= 1 bitset).
- Pick registers in allocation order instead of register number order.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305817 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-20 18:43:14 +00:00
Matt Arsenault
73854fd751 AMDGPU: Preserve undef when folding register operands
If the source was a copy of an undef register, this would
produce a read of an undefined register which is a verifier
error.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305816 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-20 18:41:31 +00:00
Stanislav Mekhanoshin
423a449bd5 [AMDGPU] Eliminate SGPR to VGPR copy when possible
SGPRs are generally cheaper, so try to use them over VGPRs.

Differential Revision: https://reviews.llvm.org/D34130

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305815 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-20 18:32:42 +00:00
Matt Arsenault
4cabef582f AMDGPU: Fix crash with undef vreg input operand
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305814 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-20 18:28:02 +00:00
Hiroshi Inoue
3ee2a16f0f [PowerPC] fix trivial typos in comment, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305813 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-20 17:53:33 +00:00
Simon Pilgrim
1313d75cd2 [CostModel][X86] Add scalar arithmetic cost tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305810 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-20 17:10:27 +00:00
Simon Pilgrim
7359f171d7 [CostModel][X86] Declare costs variables based on type
The alphabetical progression isn't that useful

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305808 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-20 17:04:46 +00:00
Craig Topper
b1618d24d3 [TableGen] Take a parameter by reference instead of pointer so we don't have to add & on both callers. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305807 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-20 16:34:37 +00:00
Craig Topper
c4a82c8d4b [TableGen] Use range based for loop. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305806 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-20 16:34:35 +00:00
Yuka Takahashi
bc5df29fed [GSoC] Flag value completion for clang
This is patch for GSoC project, bash-completion for clang.

To use this on bash, please run `source clang/utils/bash-autocomplete.sh`.
bash-autocomplete.sh is code for bash-completion.

In this patch, Options.td was mainly changed in order to add value class
in Options.inc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305805 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-20 16:31:31 +00:00
Sanjay Patel
aab686b3f7 [x86] enable CGP memcmp() expansion for 2/4/8 byte sizes
There are a couple of potential improvements as seen in the IR and asm:
1. We're unnecessarily extending to a larger type to compare values.
2. The codegen for (select cond, 1, -1) could avoid a cmov.
(or we could change the order of the compares, so we have a select with 0 operand)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305802 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-20 15:58:30 +00:00
Simon Pilgrim
85838270a5 [X86][SSE] Relax 0/-1 vector element insertion to work for any vector with >=16bit elements
Shuffle lowering/combining now does a good job for 256/512-bit vectors - we don't need to prevent this

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305801 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-20 15:19:02 +00:00
Tim Northover
f37b0dbf16 DAG: correctly legalize UMULO.
We were incorrectly sign extending into the high word (as you would for
SMULO) when legalizing UMULO in terms of a wider full multiplication.

Patch by James Duley.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305800 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-20 15:01:38 +00:00
Vassil Vassilev
46f62d55fa D33466: Make file non-executable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305795 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-20 14:20:48 +00:00
Sanjay Patel
031043b243 [InstCombine] fix code/test comments for r305792; NFC
These diffs were in the last version of the patch in D33342,
but I accidentally committed the previous rev. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305793 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-20 12:45:46 +00:00
Sanjay Patel
3e4188dc6c [InstCombine] try to canonicalize xor-of-icmps to and-of-icmps
We have a large portfolio of folds for and-of-icmps and or-of-icmps in InstSimplify and InstCombine, 
but hardly anything for xor-of-icmps. Rather than trying to rethink and translate all of those folds, 
we can use the truth table definition of xor:

X ^ Y --> (X | Y) & !(X & Y)

...to see if we can convert the xor to and/or and then use the existing folds.

http://rise4fun.com/Alive/J9v

Differential Revision: https://reviews.llvm.org/D33342


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305792 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-20 12:40:55 +00:00
Daniel Sanders
a4b49d696a [globalisel][tablegen] Add support for COPY_TO_REGCLASS.
Summary:
As part of this
* Emitted instructions now have named MachineInstr variables associated
  with them. This isn't particularly important yet but it's a small step
  towards multiple-insn emission.
* constrainSelectedInstRegOperands() is no longer hardcoded. It's now added
  as the ConstrainOperandsToDefinitionAction() action. COPY_TO_REGCLASS uses
  an alternate constraint mechanism ConstrainOperandToRegClassAction() which
  supports arbitrary constraints such as that defined by COPY_TO_REGCLASS.

Reviewers: ab, qcolombet, t.p.northover, rovka, kristof.beyls, aditya_nandakumar

Reviewed By: ab

Subscribers: javed.absar, igorb, llvm-commits

Differential Revision: https://reviews.llvm.org/D33590



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305791 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-20 12:36:34 +00:00
Simon Pilgrim
35b14a7d5d Fix Wdocumentation warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305790 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-20 12:28:33 +00:00
Simon Pilgrim
9210abe4ea [X86][SSE] Dropped old INSERT_VECTOR_ELT lowering TODO
Target shuffle combining now supports the matching of INSERT_VECTOR_ELT/PINSRW/PINSRB for merging multiple insertions into shuffles/bitmasks.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305788 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-20 10:33:34 +00:00
Simon Pilgrim
2bba203993 Fixed test name. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305787 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-20 10:24:06 +00:00
Igor Breger
bf052b5a08 [GlobalISel][X86] fix compilation error ( -Werror=unused-function )
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305786 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-20 09:40:57 +00:00
Haojian Wu
921867e7f1 [SelectionDAG] Fix an use-after-free issue introduced in r305775.
vector.back() will be invalidated when memory reallocation happens.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305785 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-20 09:29:43 +00:00
Igor Breger
515e735353 [GlobalISel][X86] Get correct RegClass for given RegBank.
Summary:
In some cases RegClass depends on target feature. Hight (16-31) vector registers exist only if AVX512f available.
Split from https://reviews.llvm.org/D33665

Reviewers: qcolombet, t.p.northover, zvi, guyblank

Reviewed By: t.p.northover, guyblank

Subscribers: guyblank, rovka, llvm-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D33952

Conflicts:
	test/CodeGen/X86/GlobalISel/select-memop-scalar.mir

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305784 91177308-0d34-0410-b5e6-96231b3b80d8
2017-06-20 09:15:10 +00:00