44032 Commits

Author SHA1 Message Date
Simon Pilgrim
8b6100048e [X86][MMX] Add fast-isel support for MMX non-temporal writes
Differential Revision: https://reviews.llvm.org/D31754

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299852 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-10 16:58:07 +00:00
Sanjay Patel
ea87eb616e [InstCombine] fix matching of or-of-icmps constants (PR32524)
Also, make the same change in and-of-icmps and remove a hack for detecting that case.

Finally, add some FIXME comments because the code duplication here is awful.

This should fix the remaining IR problem noted in:
https://bugs.llvm.org/show_bug.cgi?id=32524



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299851 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-10 16:55:57 +00:00
Adrian McCarthy
95d726af97 Improves pretty printing of variable types in llvm-pdbdump
* Adds support for pointers to arrays, which was missing
* Adds some tests
* Improves consistency of const and volatile qualifiers
* Eliminates non-composable special case code for arrays and function by using
  a more general recursive approach
* Has a hack for getting the calling convention into the right spot for
  pointer-to-functions

Given the rapid changes happenning in llvm-pdbdump, this may be difficult to
merge.

Differential Revision: https://reviews.llvm.org/D31832

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299848 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-10 16:43:09 +00:00
Craig Topper
4ed87e3dc1 [InstCombine] Support folding of add instructions with vector constants into select operations
We currently only fold scalar add of constants into selects. This improves this to support vectors too.

Differential Revision: https://reviews.llvm.org/D31683



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299847 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-10 16:40:00 +00:00
Sanjay Patel
31ad416f00 [InstCombine] add test for PR32524; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299846 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-10 16:28:08 +00:00
Diana Picus
af6290684b [ARM] GlobalISel: Support G_FPOW for float and double
Legalize to a libcall.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299841 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-10 09:27:39 +00:00
Craig Topper
17e3b0ef51 [InstCombine] Make sure we preserve fast math flags when folding fp instructions into phi nodes
Summary: I noticed in the select folding code that we copied fast math flags, but did not do the same for the similar handling in phi nodes. This patch fixes that to do the same thing as select

Reviewers: spatel, davide, majnemer, hfinkel

Reviewed By: davide

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D31690

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299838 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-10 07:00:10 +00:00
Craig Topper
dbe1448360 [InstCombine] use m_c_And and m_c_Xor to handle commuted versions of a transform.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299837 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-10 06:53:28 +00:00
Craig Topper
d178fa97c3 [InstCombine] Add test cases demonstrating missing handling for the commuted version of a transform. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299836 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-10 06:53:25 +00:00
Xin Tong
64aab18a2e [SCCP] Resolve indirect branch target when possible.
Summary:
Resolve indirect branch target when possible.
This potentially eliminates more basicblocks and result in better evaluation for phi and other things.

Reviewers: davide, efriedma, sanjoy

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D30322

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299830 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-10 00:33:25 +00:00
Sanjay Patel
e093a14cd1 [InstCombine] remove duplicate test; NFC
I moved this test to 'not.ll' in r299824 but accidentally added a copy here.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299828 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-09 21:45:52 +00:00
Sanjay Patel
d0196ef8d2 [SimplifyCFG] auto-generate better checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299825 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-09 16:16:32 +00:00
Sanjay Patel
8009ba263a [InstCombine] auto-generate better checks; NFC
Also, move a test next to its sibling to eliminate a file with just one test.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299824 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-09 15:44:59 +00:00
Hal Finkel
cfe441c874 [MemorySSA] Fix use of pointsToConstantMemory in isUseTriviallyOptimizableToLiveOnEntry
In isUseTriviallyOptimizableToLiveOnEntry, pointsToConstantMemory needs to be
called on the load's pointer operand, not on the result of the load (which
might not even be a pointer).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299823 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-09 12:57:50 +00:00
Craig Topper
239032f668 [InstCombine] Extend some OR combines to support vectors.
This adds support for these combines for vectors
(X^C)|Y -> (X|Y)^C iff Y&C == 0
Y|(X^C) -> (X|Y)^C iff Y&C == 0

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299822 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-09 06:12:41 +00:00
Craig Topper
c5f68270ad [InstCombine] Extend a canonicalization check to apply to vector constants too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299821 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-09 06:12:39 +00:00
Craig Topper
35b55965c4 [InstCombine] Add test cases to show missing support for vectors in an OR combine. Also add the commuted versions. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299820 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-09 06:12:36 +00:00
Matt Arsenault
1ad9b2d946 AMDGPU: Actually write nops for writeNopData
Before this was just writing 0s, which ends up looking like a
v_cndmask_b32 v0, s0, v0, vcc. Write out an encoded s_nop instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299816 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-08 21:28:38 +00:00
Coby Tayree
b28be420c0 [AsmParser]Emit an error if a macro has two (or more) parameters sharing the same name
Introducing a new error to macro parameters' parsing:
currently, llvm-mc won't complain if a macro have two (or more) named params with the same name.
this behavior is false, as there's no merit in having some params sharing a name.
now, instead of tolerate such a phenomena - emit an appropriate error.

Differential Revision: https://reviews.llvm.org/D31674


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299815 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-08 20:29:03 +00:00
Gor Nishanov
3cc8445f85 [coroutines] Make CoroSplit pass deterministic
coro-split-after-phi.ll test was flaky due to non-determinism in
the coroutine frame construction that was sorting the spill
vector using a pointer to a def as a part of the key.

The sorting was intended to make sure that spills for the same def
are kept together, however, we populate the vector by processing
defs in order, so the spill entires will end up together anyways.

This change removes spill sorting and restores the determinism
in the test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299809 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-08 00:49:46 +00:00
Eli Friedman
251a136db4 [ARM] Prefer BIC over BFC in ARM mode.
BIC is generally faster, and it can put the output in a different
register from the input.

We already do this in Thumb2 mode; not sure why the equivalent fix
never got applied to ARM mode.

Differential Revision: https://reviews.llvm.org/D31797



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299803 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-07 22:01:23 +00:00
Aditya Nandakumar
80726a4dd8 [GlobalISel]: Fix bug where we can report GISelFailure on erased instructions
The original instruction might get legalized and erased and expanded
into intermediate instructions and the intermediate instructions might
fail legalization. This end up in reporting GISelFailure on the erased
instruction.
Instead report GISelFailure on the intermediate instruction which failed
legalization.

Reviewed by: ab

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299802 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-07 21:49:30 +00:00
Petr Hosek
7fa217a524 [AArch64] Allow global register asm("x18") or asm("w18") under -ffixed-x18
When using -ffixed-x18, the x18 (or w18) register can safely be used
with the "global register variable" GCC extension, but the backend
fails to recognize it.

Patch by Roland McGrath.

Differential Revision: https://reviews.llvm.org/D31793

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299799 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-07 20:41:58 +00:00
Reid Kleckner
f095cc03e1 De-flake a test that is failing due to coroutine spill insertion non-determinism
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299791 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-07 18:02:53 +00:00
Simon Dardis
0bea7aaa6f Revert "[SelectionDAG] Enable target specific vector scalarization of calls and returns"
This reverts commit r299766. This change appears to have broken the MIPS
buildbots. Reverting while I investigate.

Revert "[mips] Remove usage of debug only variable (NFC)"

This reverts commit r299769. Follow up commit.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299788 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-07 17:25:05 +00:00
Stanislav Mekhanoshin
abcd91992d [AMDGPU] Unroll more to eliminate phis and conditions
Increase threshold to unroll a loop which contains an "if" statement
whose condition defined by a PHI belonging to the loop. This may help
to eliminate if region and potentially even PHI itself, saving on
both divergence and registers used for the PHI.

Add a small bonus for each of such "if" statements.

Differential Revision: https://reviews.llvm.org/D31693

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299779 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-07 16:26:28 +00:00
Dehao Chen
d8cebd13cb Use PMADDWD to expand reduction in a loop
Summary:
PMADDWD can help improve 8/16 bit integer mutliply-add operation performance for cases like:

for (int i = 0; i < count; i++)
  a += x[i] * y[i];

Reviewers: wmi, davidxl, hfinkel, RKSimon, zvi, mkuper

Reviewed By: mkuper

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D31679

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299776 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-07 15:41:52 +00:00
Igor Breger
ea3c2beccb [GlobalISel] implement narrowing for G_CONSTANT.
Summary: [GlobalISel] implement narrowing for G_CONSTANT.

Reviewers: bogner, zvi, t.p.northover

Reviewed By: t.p.northover

Subscribers: llvm-commits, dberris, rovka, kristof.beyls

Differential Revision: https://reviews.llvm.org/D31744

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299772 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-07 14:41:59 +00:00
Gor Nishanov
2702a94ea5 [coroutines] Insert spills of PHI instructions correctly
Summary:
Fix a bug where we were inserting a spill in between the PHIs in the beginning of the block.
Consider this fragment:

```
begin:
  %phi1 = phi i32 [ 0, %entry ], [ 2, %alt ]
  %phi2 = phi i32 [ 1, %entry ], [ 3, %alt ]
  %sp1 = call i8 @llvm.coro.suspend(token none, i1 false)
  switch i8 %sp1, label %suspend [i8 0, label %resume
                                  i8 1, label %cleanup]
resume:
  call i32 @print(i32 %phi1)
```
Unless we are spilling the argument or result of the invoke, we were always inserting the spill immediately following the instruction.
The fix adds a check that if the spilled instruction is a PHI Node, select an appropriate insert point with `getFirstInsertionPt()` that
skips all the PHI Nodes and EH pads.

Reviewers: majnemer, rnk

Reviewed By: rnk

Subscribers: qcolombet, EricWF, llvm-commits

Differential Revision: https://reviews.llvm.org/D31799

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299771 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-07 14:16:49 +00:00
Matthew Simpson
ccc38cc5e7 Reapply r298620: [LV] Vectorize GEPs
This patch reapplies r298620. The original patch was reverted because of two
issues. First, the patch exposed a bug in InstCombine that caused the Chromium
builds to fail (PR32414). This issue was fixed in r299017. Second, the patch
introduced a bug in the vectorizer's scalars analysis that caused test suite
builds to fail on SystemZ. The scalars analysis was too aggressive and marked a
memory instruction scalar, even though it was going to be vectorized. This
issue has been fixed in the current patch and several new test cases for the
scalars analysis have been added.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299770 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-07 14:15:34 +00:00
Petar Jovanovic
2ad61e7749 [mips][msa] Fix generation of bm(n)zi and bins[lr]i instructions
We have two cases here, the first one being the following instruction
selection from the builtin function:
bm(n)zi builtin -> vselect node -> bins[lr]i machine instruction

In case of bm(n)zi having an immediate which has either its high or low bits
set, a bins[lr] instruction can be selected through the selectVSplatMask[LR]
function. The function counts the number of bits set, and that value is
being passed to the bins[lr]i instruction as its immediate, which in turn
copies immediate modulo the size of the element in bits plus 1 as per specs,
where we get the off-by-one-error.

The other case is:
bins[lr]i -> vselect node -> bsel.v

In this case, a bsel.v instruction gets selected with a mask having one bit
less set than required.

Patch by Stefan Maksimovic.

Differential Revision: https://reviews.llvm.org/D30579



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299768 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-07 13:31:36 +00:00
Dmitry Preobrazhensky
7bf2a5770d [AMDGPU][MC] Fix for Bug 28211 + LIT tests
- corrected DS_GWS_* opcodes (see VI_Shader_Programming#16.pdf for detailed description)
  - address operand is not used
  - several opcodes have data operand
  - all opcodes have offset modifier
- DS_AND_SRC2_B32: corrected typo in mnemo
- DS_WRAP_RTN_F32 replaced with DS_WRAP_RTN_B32
- added CI/VI opcodes:
  - DS_CONDXCHG32_RTN_B64
  - DS_GWS_SEMA_RELEASE_ALL
- added VI opcodes:
  - DS_CONSUME
  - DS_APPEND
  - DS_ORDERED_COUNT

Differential Revision: https://reviews.llvm.org/D31707

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299767 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-07 13:07:13 +00:00
Simon Dardis
dc04fc16d6 [SelectionDAG] Enable target specific vector scalarization of calls and returns
By target hookifying getRegisterType, getNumRegisters, getVectorBreakdown,
backends can request that LLVM to scalarize vector types for calls
and returns.

The MIPS vector ABI requires that vector arguments and returns are passed in
integer registers. With SelectionDAG's new hooks, the MIPS backend can now
handle LLVM-IR with vector types in calls and returns. E.g.
'call @foo(<4 x i32> %4)'.

Previously these cases would be scalarized for the MIPS O32/N32/N64 ABI for
calls and returns if vector types were not legal. If vector types were legal,
a single 128bit vector argument would be assigned to a single 32 bit / 64 bit
integer register.

By teaching the MIPS backend to inspect the original types, it can now
implement the MIPS vector ABI which requires a particular method of
scalarizing vectors.

Previously, the MIPS backend relied on clang to scalarize types such as "call
@foo(<4 x float> %a) into "call @foo(i32 inreg %1, i32 inreg %2, i32 inreg %3,
i32 inreg %4)".

This patch enables the MIPS backend to take either form for vector types.

Reviewers: zoran.jovanovic, jaydeep, vkalintiris, slthakur

Differential Revision: https://reviews.llvm.org/D27845



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299766 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-07 13:03:52 +00:00
Jonas Paulsson
c833eb7ff6 [SystemZ] Check for presence of vector support in SystemZISelLowering
A test case was found with llvm-stress that caused DAGCombiner to crash
when compiling for an older subtarget without vector support.

SystemZTargetLowering::combineTruncateExtract() should do nothing for older
subtargets.

This check was placed in canTreatAsByteVector(), which also helps in a few
other places.

Review: Ulrich Weigand

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299763 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-07 12:35:11 +00:00
Diana Picus
f51d2756c0 [ARM] GlobalISel: Test hard float properly
It turns out -float-abi=hard doesn't set the hard float calling
convention for libcalls. We need to use a hard float triple instead
(e.g. gnueabihf).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299761 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-07 12:04:24 +00:00
Sam Kolton
218a5a7e27 [AMDGPU] Move SiShrinkInstruction and SDWAPeephole to SSAOptimization passes
Summary:
Difference beetween PreRegAlloc() and MachineSSAOptimization() are that the former is run despite of -O0 optimization level. In my undestanding SiShrinkInstructions and SDWAPeephole shouldn't run when optimizations are disabled.
With this change order of passes will not change.

Reviewers: arsenm, vpykhtin, rampitec

Subscribers: qcolombet, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye

Differential Revision: https://reviews.llvm.org/D31705

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299757 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-07 10:53:12 +00:00
Diana Picus
aa39cd364d [ARM] GlobalISel: Support frem for 64-bit values
Legalize to a libcall.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299756 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-07 10:50:02 +00:00
Diana Picus
3afaea7b42 [ARM] GlobalISel: Support frem for 32-bit values
Legalize to a libcall.
On this occasion, also start allowing soft float subtargets. For the
moment G_FREM is the only legal floating point operation for them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299753 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-07 09:41:39 +00:00
Craig Topper
826edb2ba1 [InstCombine] Handle more commuted cases of ((A & B) | ~A) -> (~A | B)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299747 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-07 07:32:00 +00:00
Craig Topper
ae892fe446 [InstCombine] Add additional tests with varied commuting to show missing combines. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299746 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-07 07:31:55 +00:00
Daniel Berlin
f634bfbb16 AliasAnalysis: Be less conservative about volatile than atomic.
Summary:
getModRefInfo is meant to answer the question "what impact does this
instruction have on a given memory location" (not even another
instruction).

Long debate on this on IRC comes to the conclusion the answer should be "nothing special".

That is, a noalias volatile store does not affect a memory location
just by being volatile.  Note: DSE and GVN and memdep currently
believe this, because memdep just goes behind AA's back after it says
"modref" right now.

see line 635 of memdep. Prior to this patch we would get modref there, then check aliasing,
and if it said noalias, we would continue.

getModRefInfo *already* has this same AA check, it just wasn't being used because volatile was
lumped in with ordering.

(I am separately testing whether this code in memdep is now dead except for the invariant load case)

Reviewers: jyknight, chandlerc

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D31726

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299741 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-07 01:28:36 +00:00
Craig Topper
1096080a5d [InstCombine] Add more commuted patterns to support folding ((~A & B) | A) -> (A | B).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299737 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-07 00:29:47 +00:00
Zachary Turner
b470610091 Allow specification of what kinds of class members to dump.
Previously when dumping class definitions, there were only
two modes - on or off.  But it's useful to sometimes get a
little more fine-grained.  For example, you might only want
to see the record layout (for example to look for extraneous
padding).  This patch adds a third mode, layout mode, which
does exactly that.  Only this-relative data members are
displayed in this mode.

Differential Revision: https://reviews.llvm.org/D31794

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299733 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-06 23:43:39 +00:00
Konstantin Zhuravlyov
4d40c97796 AMDGPU/GFX9: Fix shared and private aperture queries
Differential Revision: https://reviews.llvm.org/D31786


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299727 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-06 23:02:33 +00:00
Craig Topper
42c1cc1993 [InstCombine] Add a few cases for OR we fail to optimize due to missing commuted patterns checks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299725 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-06 23:00:22 +00:00
Eli Friedman
f25acacbe6 Turn on -addr-sink-using-gep by default.
The new codepath has been in the tree for years, and there isn't any
reason to use two codepaths here.

Differential Revision: https://reviews.llvm.org/D30596



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299723 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-06 22:42:18 +00:00
Michael Kuperstein
bf82f16ca4 [X86] Revert r299387 due to AVX legalization infinite loop.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299720 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-06 22:33:25 +00:00
Matt Arsenault
c82755f01b AMDGPU: Diagnose illegal SGPR to VGPR copies
This is possible in ways that are not compiler bugs,
so stop asserting on them.

This emits an extra error when emitting objects when it
can't encode the new pseudo, but I'm not sure that matters.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299712 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-06 21:09:53 +00:00
Matt Arsenault
34d5677726 AMDGPU: Replace fp16SrcZerosHighBits with a whitelist
FCOPYSIGN is lowered to bit operations which don't clear the high
bits.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299708 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-06 20:58:30 +00:00
Keno Fischer
1f6fa0f45a [llvm-extract] Add option for recursive extraction
Summary:
Particularly, with --delete, this can be very useful for testing
new optimizations on some hotspots, without having to run it on the whole
application. E.g. as such:
```
llvm-extract app.bc --recursive --rfunc .*hotspot.* > hotspot.bc
llvm-extract app.bc --recursive --delete --rfunc .*hotspot.* > residual.bc
llc -filetype=obj residual.bc > residual.o
llc -filetype=obj hotspot.bc > hotspot.o
cc -o app residual.o hotspot.o
```

Reviewed By: davide
Differential Revision: https://reviews.llvm.org/D31722

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299706 91177308-0d34-0410-b5e6-96231b3b80d8
2017-04-06 20:51:40 +00:00