131174 Commits

Author SHA1 Message Date
Simon Pilgrim
95730ae9bd [InstCombine][AVX2] Combine VPERMD/VPERMPS intrinsics with constant masks to shufflevector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268199 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-01 16:41:22 +00:00
Simon Pilgrim
4dfb7cfee7 Fixed MSVC 'not all control paths return a value' warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268198 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-01 15:52:31 +00:00
Simon Pilgrim
84b8ada543 Document the LLVM_ENABLE_EXPENSIVE_CHECKS cmake option introduced in r268050
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268197 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-01 15:27:47 +00:00
Igor Breger
b829003e67 getelementptr instruction, support index vector of EVT.
Differential Revision: http://reviews.llvm.org/D19775

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268195 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-01 13:29:12 +00:00
Igor Breger
dcb96be9b4 Change AVX512 braodcastsd/ss patterns interaction with spilling . New implementation take a scalar register and generate a vector without COPY_TO_REGCLASS (turn it into a VR128 register ) .The issue is that during register allocation we may spill a scalar value using 128-bit loads and stores, wasting cache bandwidth.
Differential Revision: http://reviews.llvm.org/D19579

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268190 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-01 08:40:00 +00:00
Craig Topper
807ccbc3c1 [AVX512] Prefer AVX512 VPACK instructions over AVX/AVX2 instructions when VLX and BWI are supported.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268189 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-01 06:52:19 +00:00
Craig Topper
df2ac9afe2 [AVX512] Add HasVLX to the 128/256-bit versions of VPACKSSDW/USDW/SSWB/USWB and VPMADDUBSW/VPMADDWD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268188 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-01 06:24:57 +00:00
Craig Topper
105f6befe9 [AVX512] Make sure 128/256-bit DQI versions of VAND/VANDN/VOR/VXOR are also marked as requiring VLX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268186 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-01 05:57:06 +00:00
Craig Topper
4a06cf179f [X86] Add an AddedComplexity to another pattern to put it near similar in the output file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268184 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-01 05:22:15 +00:00
Craig Topper
5926b3a290 [X86] Remove a seemlingly unused pattern. The same pattern appears elsewhere with an AddedComplexity that made this unreachable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268183 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-01 05:22:13 +00:00
Craig Topper
beb596390c [X86] Add AddedComplexity to keep some similar patterns near each other in the output file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268181 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-01 04:59:49 +00:00
Craig Topper
37745446ec [X86] Remove some redundant selection patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268180 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-01 04:59:46 +00:00
Craig Topper
c473ca5cff [AVX512] Replace vector_extract with extractelt in some patterns. They mean the same thing but vector_extract is deprecated. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268179 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-01 04:59:44 +00:00
Sanjoy Das
17d8569b6e [SCEV] When printing via -analysis, dump loop disposition
There are currently some bugs in tree around SCEV caching an incorrect
loop disposition.  Printing out loop dispositions will let us write
whitebox tests as those are fixed.

The dispositions are printed as a list in "inside out" order,
i.e. innermost loop first.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268177 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-01 04:51:05 +00:00
Amaury Sechet
58e9430c5d Properly name LLVMSetIsInBounds's argument. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268176 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-01 02:23:14 +00:00
Amaury Sechet
3f89ecd798 Capitalize align argument in the C API as per convention. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268175 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-01 01:42:34 +00:00
Craig Topper
11e9c38a31 [AVX512] Add hasSideEffects/mayLoad/mayStore flags to some instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268174 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-01 01:03:56 +00:00
Lang Hames
6706c34b89 [ORC] Save AArch64 NEON state in the JIT reentry block.
The earlier version of the resolver code did not save NEON state, so it would
have broken any callees that used floating point.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268173 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-01 00:14:45 +00:00
Rui Ueyama
d5ebabfb3e [lit] Add %:[STpst] to represent paths without colons on Windows.
Summary:
We need these variables to concatenate two absolute paths to construct
a valid path. Currently, %t\%t is, for example, expanded to C:\foo\C:\foo,
which is not a valid path because ":" is not a valid path character
on Windows. With this patch, %t will be expanded to C\foo.

Differential Revision: http://reviews.llvm.org/D19757

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268168 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-30 21:32:12 +00:00
Simon Pilgrim
585ee3d03c [InstCombine][AVX2] Added VPERMD/VPERMPS shuffle combining placeholder tests.
For future support for VPERMD/VPERMPS to generic shuffles combines

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268166 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-30 20:41:52 +00:00
Saleem Abdulrasool
5ac1e61a27 CodeGen: convert to range based loops
Convert to using some range based loops, avoid unnecessary variables for
unchecked casts.  NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268165 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-30 18:15:34 +00:00
Craig Topper
9f60ac413e [X86] Reduce memory usage of MemOp2RegOp and RegOp2MemOp folding maps.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268164 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-30 17:59:49 +00:00
Rafael Espindola
a2a8d71f28 Add missing override.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268163 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-30 15:18:21 +00:00
Marcin Koscielnicki
a9a0b9a128 [ASan] Add shadow offset for SystemZ.
SystemZ on Linux currently has 53-bit address space.  In theory, the hardware
could support a full 64-bit address space, but that's not supported due to
kernel limitations (it'd require 5-level page tables), and there are no plans
for that.  The default process layout stays within first 4TB of address space
(to avoid creating 4-level page tables), so any offset >= (1 << 42) is fine.
Let's use 1 << 52 here, ie. exactly half the address space.

I've originally used 7 << 50 (uses top 1/8th of the address space), but ASan
runtime assumes there's some space after the shadow area.  While this is
fixable, it's simpler to avoid the issue entirely.

Also, I've originally wanted to have the shadow aligned to 1/8th the address
space, so that we can use OR like X86 to assemble the offset.  I no longer
think it's a good idea, since using ADD enables us to load the constant just
once and use it with register + register indexed addressing.

Differential Revision: http://reviews.llvm.org/D19650

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268161 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-30 09:57:34 +00:00
Simon Pilgrim
79d72aac7a [InstCombine][AVX] Split off VPERMILVAR tests and added additional tests for UNDEF mask elements
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268159 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-30 07:32:19 +00:00
Simon Pilgrim
99e30751ef [InstCombine][AVX] VPERMILVAR to shuffle combine to use general aggregate elements. NFCI.
Make use of Constant::getAggregateElement instead of checking constant types - first step towards adding support for UNDEF mask elements.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268158 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-30 07:23:30 +00:00
Sriraman Tallam
540bb24384 Differential Revision: http://reviews.llvm.org/D19753
Delete Target Option PositionIndependentExecutable as PIE is now part of module flags.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268155 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-30 04:18:52 +00:00
Tom Stellard
df1aa5c25d AMDGPU/SI: Remove wait state handling for SMRD in SIInsertWaits
This was supposed to be part of r268143.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268154 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-30 04:04:48 +00:00
Hal Finkel
dd0687afa4 [PowerPC/QPX] Fix the load/splat peephole with overlapping reads
If, in between the splat and the load (which does an implicit splat), there is
a read of the splat register, then that register must have another earlier
definition. In that case, we can't replace the load's destination register with
the splat's destination register.

Unfortunately, I don't have a small or non-fragile test case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268152 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-30 01:59:28 +00:00
Amjad Aboud
36e1723e54 Reverting 268054 & 268063 as they caused PR27579.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268150 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-30 01:44:07 +00:00
Sanjoy Das
793e61921c [LowerGuardIntrinsics] Keep track of !make.implicit metadata
If a guard call being lowered by LowerGuardIntrinsics has the
`!make.implicit` metadata attached, then reattach the metadata to the
branch in the resulting expanded form of the intrinsic.  This allows us
to implement null checks as guards and still get the benefit of implicit
null checks.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268148 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-30 00:55:59 +00:00
Lawrence Hu
177402482e Reroll loops with multiple IV and negative step part 3
support multiple induction variables

    This patch enable loop reroll for the following case:
        for(int i=0;  i<N; i += 2) {
           S += *a++;
           S += *a++;
        };

Differential Revision: http://reviews.llvm.org/D16550



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268147 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-30 00:51:22 +00:00
Lang Hames
1c7deb2e11 [Orc] Fix the AArch64 resolver size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268146 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-30 00:50:26 +00:00
Vedant Kumar
9759276c58 Fix a typo (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268144 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-30 00:32:54 +00:00
Tom Stellard
6ab99c7ca6 AMDGPU/SI: Enable the post-ra scheduler
Summary:
This includes a hazard recognizer implementation to replace some of
the hazard handling we had during frame index elimination.

Reviewers: arsenm

Subscribers: qcolombet, arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D18602

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268143 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-30 00:23:06 +00:00
Sanjoy Das
001d688855 [LowerGuardIntrinsics] Preserve calling conv when lowering
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268142 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-30 00:17:47 +00:00
Sanjay Patel
6ebef00895 add minimal test to show dropped metadata
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268141 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-30 00:12:54 +00:00
Sanjay Patel
9803475d93 remove the metadata added with r267827
We can demonstrate the 'select' bug and fix with a simpler test case.
The merged weight values are already tested in another test.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268139 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-30 00:02:36 +00:00
Xinliang David Li
2f3e898b66 Reapply r268107 after fixing a bug breaks debug build.
Makes the new method to set data needed by debug dump.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268130 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-29 22:59:36 +00:00
Sanjoy Das
3aa5468391 Mark guards on true as "trivially dead"
This moves some logic added to EarlyCSE in rL268120 into
`llvm::isInstructionTriviallyDead`.  Adds a test case for DCE to
demonstrate that passes other than EarlyCSE can now pick up on the new
information.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268126 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-29 22:23:16 +00:00
Chris Bieneman
ccc43fcdeb [CMake] [Xcode] Improving Xcode toolchain generation to support distribution targets
This adds a new target `install-distribution-toolchain` which will install an Xcode toolchain featuring just the LLVM components specified in LLVM_DISTRIBUTION_COMPONENTS.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268125 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-29 22:19:35 +00:00
Sanjay Patel
0ac37a4267 clean up documentation comments; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268122 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-29 22:03:27 +00:00
Haicheng Wu
0583545372 [MBP] Use Function::optForSize() instead of checking OptimizeForSize directly.
Fix a FIXME.  Disable loop alignment if compiled with -Oz now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268121 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-29 22:01:10 +00:00
Sanjoy Das
d04393828c [EarlyCSE] Simplify guard intrinsics
Summary:
This change teaches EarlyCSE some basic properties of guard intrinsics:

 - Guard intrinsics read all memory, but don't write to any memory
 - After a guard has executed, the condition it was guarding on can be
   assumed to be true
 - Guard intrinsics on a constant `true` are no-ops

Reviewers: reames, hfinkel

Subscribers: mcrosier, llvm-commits

Differential Revision: http://reviews.llvm.org/D19578

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268120 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-29 21:52:58 +00:00
Matt Arsenault
c10caa3301 AMDGPU: Fix crash with unreachable terminators.
If a block has no successors because it ends in unreachable,
this was accessing an invalid iterator.

Also stop counting instructions that don't emit any
real instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268119 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-29 21:52:13 +00:00
Xinliang David Li
05d883a443 Revert r268107 -- debug build failure
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268116 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-29 21:43:28 +00:00
Simon Pilgrim
63a5b4c179 [InstCombine][SSE] PSHUFB to shuffle combine to use general aggregate elements. NFCI.
Make use of Constant::getAggregateElement instead of checking constant types - first step towards adding support for UNDEF mask elements.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268115 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-29 21:34:54 +00:00
Lang Hames
d53ff2dcbd [Orc] Add ORC lazy-compilation support for AArch64.
The ORC compile callbacks and indirect stubs APIs will now work for AArc64,
allowing functions to be lazily compiled and/or updated.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268112 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-29 21:32:00 +00:00
Lang Hames
2534484e89 [Orc] Make sure we don't drop the internal error in OrcRemoteTargetClient when
the constructor fails, as this would lead to an 'unchecked error' crash.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268111 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-29 21:29:48 +00:00
Chris Bieneman
f8bfee254f [Docs] Refer to the CMakePrimer from CMake doc
The "Building LLVM with CMake" document should have a reference to the CMakePrimer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268109 91177308-0d34-0410-b5e6-96231b3b80d8
2016-04-29 21:23:24 +00:00