Commit Graph

138479 Commits

Author SHA1 Message Date
Matt Arsenault
982faf27a3 AMDGPU: Use i64 scalar compare instructions
VI added eq/ne for i64, so use them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281800 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-17 02:02:19 +00:00
Tom Stellard
019f4de043 AMDGPU/SI: Fix kernel argument ABI for HSA
Summary: i8, i16, and f16 values are not extended to 32-bit in the HSA kernel ABI.

Reviewers: arsenm

Subscribers: arsenm, kzhuravl, wdng, nhaehnle, llvm-commits, yaxunl

Differential Revision: https://reviews.llvm.org/D24621

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281789 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 22:20:24 +00:00
Chris Bieneman
78279ce05d [CMake] Support symlinks with the same name as the binary
This supports creating symlinks to tools in different directories than
the tool is built to. This is useful for the LLDB framework build which
I’m sending patches for shortly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281788 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 22:19:19 +00:00
Sanjay Patel
16150b3947 [InstCombine] canonicalize vector select with constant vector condition to shuffle
As discussed on llvm-dev ( http://lists.llvm.org/pipermail/llvm-dev/2016-August/104210.html ): 
turn a vector select with constant condition operand into a shuffle as a canonicalization step.
Shuffles may be easier to reason about in conjunction with other shuffles and insert/extract.

Possible known (minor?) regressions from this change are filed as:
https://llvm.org/bugs/show_bug.cgi?id=28530 
https://llvm.org/bugs/show_bug.cgi?id=28531 
https://llvm.org/bugs/show_bug.cgi?id=30371

If something terrible happens to perf after this commit, feel free to revert until a backend
fix is in place.

Differential Revision: https://reviews.llvm.org/D24279


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281787 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 22:16:18 +00:00
Matt Arsenault
8f824feb12 AMDGPU: Allow some control flow intrinsics to be CSEd
These clean up some unnecessary or instructions in
cases with complex loops.

In the original testcase I noticed this, the same
or with exec was repeated 5 or 6 times in a row. With
this only one is emitted or sometimes a copy.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281786 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 22:11:18 +00:00
Evgeniy Stepanov
df9dcaf1ee [safestack] Fix assertion failure in stack coloring.
This is a fix for PR30318.

Clang may generate IR where an alloca is already live when entering a
BB with lifetime.start. In this case, conservatively extend the
alloca lifetime all the way back to the block entry.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281784 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 22:04:10 +00:00
Quentin Colombet
005bfb8238 [RegAllocGreedy] Fix the list of NewVRegs for last chance recoloring.
When trying to recolor a register we may split live-ranges in the
process. When we create new live-ranges we will have to process them,
but when we move a register from Assign to Split, the allocation is not
changed until the whole recoloring session is successful.
Therefore, only push the live-ranges that changed from Assign to
Split when the recoloring is successful.

Same as the previous commit, I was not able to produce a test case that
reproduce the problem with in-tree targets.

Note: The bug has been here since the recoloring scheme has been added
back in r200883 (Feb 2014).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281783 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 22:00:50 +00:00
Quentin Colombet
12bac3e6a2 [RegAllocGreedy] Fix an assertion and condition when last chance recoloring is used.
When last chance recoloring is used, the list of NewVRegs may not be
empty when calling selectOrSplitImpl. Indeed, another coloring may have
taken place with splitting/spilling in the same recoloring session.

Relax an assertion to take this into account and adapt a condition to
act as if the NewVRegs were local to this selectOrSplitImpl instance.

Unfortunately I am unable to produce a test case for this, I was only
able to reproduce the conditions on an out-of-tree target.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281782 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 22:00:42 +00:00
Tom Stellard
77361ae206 AMDGPU: Refactor kernel argument lowering
Summary:
The main challenge in lowering kernel arguments for AMDGPU is determing the
memory type of the argument.  The generic calling convention code assumes
that only legal register types can be stored in memory, but this is not the
case for AMDGPU.

This consolidates all the logic AMDGPU uses for deducing memory types into a single
function.  This will make it much easier to support different ABIs in the future.

Reviewers: arsenm

Subscribers: arsenm, wdng, nhaehnle, llvm-commits, yaxunl

Differential Revision: https://reviews.llvm.org/D24614

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281781 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 21:53:00 +00:00
Matt Arsenault
3a74bac021 AMDGPU: Use SOPK compare instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281780 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 21:41:16 +00:00
Tom Stellard
1961591989 AMDGPU/SI: Add support for triples with the mesa3d operating system
Summary:
mesa3d will use the same kernel calling convention as amdhsa, but it will
handle everything else like the default 'unknown' OS type.

Reviewers: arsenm

Subscribers: arsenm, llvm-commits, kzhuravl

Differential Revision: https://reviews.llvm.org/D22783

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281779 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 21:34:26 +00:00
Sanjay Patel
59183b9175 [InstCombine] allow vector types for constant folding / computeKnownBits (PR24942)
computeKnownBits() already works for integer vectors, so allow vector types when calling that from InstCombine.

I don't think the change to use m_APInt in computeKnownBits is strictly necessary because we do check for 
ConstantVector later, but it's more efficient to handle the splat case without needing to loop on vector elements.

This should work with InstSimplify, but doesn't yet, so I made that a FIXME comment on the test for PR24942:
https://llvm.org/bugs/show_bug.cgi?id=24942

Differential Revision: https://reviews.llvm.org/D24677


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281777 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 21:20:36 +00:00
Davide Italiano
463cfe4e60 [LTO] Add ability to parse AA pipelines.
This is supposed to be a drop in replacement for what lld
provides via --lto-newpm-aa-pipeline.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281774 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 21:03:21 +00:00
Derek Schuff
740da34c34 [WebAssembly] Fix function types of CFGStackify tests
Make the function's declared type match its (lack of) return type

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281773 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 20:58:31 +00:00
Simon Pilgrim
839ecc81ef [X86][SSE] Added vector sub combine tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281769 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 20:00:51 +00:00
Simon Pilgrim
b2c2d1f82a [X86][SSE] Added vector add combine tests
Some work great and others currently demonstrate the anti-vector bias prevalent in DAGCombiner

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281768 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 19:20:41 +00:00
Derek Schuff
7add7dd73a Install libLLVM if needed with LLVM_INSTALL_TOOLCHAIN_ONLY
Summary:
When LLVM_LINK_LLVM_DYLIB is set, the libLLVM shared
library needs to be installed in the toolchain.  Without
this chanage LLVM_INSTALL_TOOLCHAIN_ONLY combined with
LLVM_LINK_LLVM_DYLIB results in a broken install.

Patch by Sam Clegg

Differential Revision: https://reviews.llvm.org/D24676

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281763 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 18:50:39 +00:00
Nirav Dave
db393b8e8f Defer asm errors to post-statement failure
Recommitting after fixing AsmParser initialization and X86 inline asm
error cleanup.

Allow errors to be deferred and emitted as part of clean up to simplify
and shorten Assembly parser code. This will allow error messages to be
emitted in helper functions and be modified by the caller which has
better context.

As part of this many minor cleanups to the Parser:

* Unify parser cleanup on error
* Add Workaround for incorrect return values in ParseDirective instances
* Tighten checks on error-signifying return values for parser functions
  and fix in-tree TargetParsers to be more consistent with the changes.
* Fix AArch64 test cases checking for spurious error messages that are
  now fixed.

These changes should be backwards compatible with current Target Parsers
so long as the error status are correctly returned in appropriate
functions.

Reviewers: rnk, majnemer

Subscribers: aemerson, jyknight, llvm-commits

Differential Revision: https://reviews.llvm.org/D24047

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281762 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 18:30:20 +00:00
Dehao Chen
47462143b2 Change extractProfMetadata and extractProfTotalWeight to const member function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281760 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 18:27:20 +00:00
Michael Kuperstein
6dc8c1ab98 Make test slightly more explicit. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281759 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 18:20:43 +00:00
Eli Friedman
0d3cd48d84 LoopDistribute should preserve GlobalsAA.
Differential Revision: https://reviews.llvm.org/D24204



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281758 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 18:01:48 +00:00
Eli Friedman
3383e2cb13 LoopLoadElimination should preserve GlobalsAA.
Avoids losing GlobalsAA in the standard pass pipeline.

Differential Revision: https://reviews.llvm.org/D24094



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281757 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 17:58:07 +00:00
Sanjay Patel
58071c976f auto-generate checks
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281756 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 17:54:52 +00:00
Sanjay Patel
9fd0ad86d4 auto-generate checks
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281755 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 17:48:16 +00:00
Mehdi Amini
f15b3afcbc Fix test after renaming -name-anon-functions pass to -name-anon-globals
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281752 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 17:18:16 +00:00
Teresa Johnson
1832d7b823 [LTO] Use llvm-nm instead of nm in new tests
The use of nm in the new tests added with r281725 caused a couple
of bot failures:
http://lab.llvm.org:8011/builders/clang-x64-ninja-win7/builds/15701
http://bb.pgr.jp/builders/ninja-clang-i686-msc19-R/builds/6939

Use llvm-nm instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281750 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 17:12:48 +00:00
Eric Christopher
d964ea8fd7 Actually remove the Mangler from the AsmPrinter and clean up the places it was "used" but not used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281749 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 17:07:23 +00:00
Eric Christopher
7bbc777d2e Fix a hidden use of grabbing the Mangler from the AsmPrinter and update
accordingly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281748 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 17:07:13 +00:00
Mehdi Amini
8dff0d8b85 Rename NameAnonFunctions to NameAnonGlobals to match what it is doing (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281745 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 16:56:30 +00:00
Mehdi Amini
4dbfcbba39 Fix NameAnonFunctions pass: for ThinLTO we need to rename global variables as well
A follow-up patch will rename this pass and the source file accordingly,
but I figured the non-NFC change will be easier to spot in isolation.

Differential Revision: https://reviews.llvm.org/D24641

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281744 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 16:56:25 +00:00
Sanjay Patel
1af818627a [InstCombine] add helper functions for visitICmpInst(); NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281743 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 16:10:22 +00:00
Davide Italiano
ad63f23c04 [IRObjectFile] Turn llvm_unreachable("foo") into something more explicative.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281742 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 16:07:19 +00:00
Davide Italiano
3284f278cd [LTO] Prevent asm references to be dropped from the output.
Differential Revision:  https://reviews.llvm.org/D24617

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281741 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 16:05:25 +00:00
Ahmed Bougacha
c49f5e8a93 [AArch64][GlobalISel] Add default regbank mapping for int<>FP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281739 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 15:12:46 +00:00
Ahmed Bougacha
d705c9fe79 [AArch64][GlobalISel] Add default regbank mapping for G_FCMP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281738 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 15:12:43 +00:00
Ahmed Bougacha
16527fa797 [AArch64][GlobalISel] Add default regbank mapping for FP ops.
These should have all their operands - even scalars - go on FPR.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281737 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 15:12:40 +00:00
Ahmed Bougacha
07ca84e98a [AArch64][GlobalISel] Test default regbank mapping for G_ICMP.
Also relax a RegisterBankInfo verifier check that's incompatible with
1-bit mappings.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281735 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 14:44:54 +00:00
Ahmed Bougacha
c3852f5056 [AArch64][GlobalISel] Add default regbank mappings for mixed-type ops.
We used to only support instructions with same-type operands.
Instead, use the per-register type information to map each
operand more accurately.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281734 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 14:44:51 +00:00
Ahmed Bougacha
ac10524760 [AArch64][GlobalISel] Add tests for default RegBank mappings. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281733 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 14:44:48 +00:00
David L Kreitzer
cd01b58518 Reapplying r278731 after fixing the problem that caused it to be reverted.
Enhance SCEV to compute the trip count for some loops with unknown stride.

Patch by Pankaj Chawla

Differential Revision: https://reviews.llvm.org/D22377


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281732 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 14:38:13 +00:00
Simon Dardis
0057769961 [mips] Fix previous revert r281726.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281729 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 14:16:23 +00:00
Keith Walker
7435b28542 Place the lowered phi instruction(s) before the DEBUG_VALUE entry
When a phi node is finally lowered to a machine instruction it is
important that the lowered "load" instruction is placed before the
associated DEBUG_VALUE entry describing the value loaded.

Renamed the existing SkipPHIsAndLabels to SkipPHIsLabelsAndDebug to
more fully describe that it also skips debug entries. Then used the
"new" function SkipPHIsAndLabels when the debug information should not
be skipped when placing the lowered "load" instructions so that it is
placed before the debug entries.

Differential Revision: https://reviews.llvm.org/D23760 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281727 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 14:07:29 +00:00
Simon Dardis
ffabbc5291 Revert "[mips] Fix aui/daui/dahi/dati for MIPSR6"
This reverts r281724. Still need dsanders to accept this.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281726 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 13:56:05 +00:00
Teresa Johnson
8ab74babf7 [LTO] Fix handling of mixed (regular and thin) mode LTO
Summary:
In runThinLTO we start the task numbering for ThinLTO backend
tasks depending on whether there was also a regular LTO object
(CombinedModule). However, the CombinedModule is moved at
the end of runRegularLTO, so we need to save this information and
pass it into runThinLTO. Otherwise the AddOutput callback to the client
will use the same task number for both the regular LTO object
and the first ThinLTO object, which in gold-plugin caused only
one to be end up in the output filename array and therefore passed
back to gold for the final native link.

Reviewers: pcc, mehdi_amini

Subscribers: mehdi_amini, kromanova

Differential Revision: https://reviews.llvm.org/D24643

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281725 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 13:54:19 +00:00
Simon Dardis
e38b67fe3b [mips] Fix aui/daui/dahi/dati for MIPSR6
For compatiblity with binutils, define these instructions to take
two registers with a 16bit unsigned immediate. Both of the registers
have to be same for dahi and dati.

Reviewers: vkalintiris, dsanders, zoran.jovanovic
 
Differential Review: https://reviews.llvm.org/D21473



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281724 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 13:50:43 +00:00
Sjoerd Meijer
ea7e0cd04b Reverting r281719, this is causing buildbot failures and timeouts again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281722 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 13:16:52 +00:00
Ahmed Bougacha
89f7a48a4a [AArch64][GlobalISel] Use the generic DefaultMapping as the default.
This lets generic logic handle the common case, instead of having to
implement applyMappingImpl for each instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281720 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 12:33:34 +00:00
Sjoerd Meijer
f9c0a77050 This is an attempt to reapply r280808: [ARM] Lower UDIV+UREM to UDIV+MLS
(and the same for SREM)

This was causing buildbot failures earlier (time outs in the LNT suite).
However, we haven't been able to reproduce this and are suspecting this
was caused by another (reverted) patch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281719 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 12:10:09 +00:00
Eric Liu
6c1574bca5 Trying to fix Mangler memory leak in TargetLoweringObjectFile.
Summary:
`TargetLoweringObjectFile` can be re-used and thus `TargetLoweringObjectFile::Initialize()`
can be called multiple times causing `Mang` pointer memory leak.

Reviewers: echristo

Subscribers: llvm-commits, mehdi_amini

Differential Revision: https://reviews.llvm.org/D24659

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281718 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 11:50:57 +00:00
Chandler Carruth
793f0085f9 [LCG] Redesign the lazy post-order iteration mechanism for the
LazyCallGraph to support repeated, stable iterations, even in the face
of graph updates.

This is particularly important to allow the CGSCC pass manager to walk
the RefSCCs (and thus everything else) in a module more than once. Lots
of unittests and other tests were hard or impossible to write because
repeated CGSCC pass managers which didn't invalidate the LazyCallGraph
would conclude the module was empty after the first one. =[ Really,
really bad.

The interesting thing is that in many ways this simplifies the code. We
can now re-use the same code for handling reference edge insertion
updates of the RefSCC graph as we use for handling call edge insertion
updates of the SCC graph. Outside of adapting to the shared logic for
this (which isn't trivial, but is *much* simpler than the DFS it
replaces!), the new code involves putting newly created RefSCCs when
deleting a reference edge into the cached list in the correct way, and
to re-formulate the iterator to be stable and effective even in the face
of these kinds of updates.

I've updated the unittests for the LazyCallGraph to re-iterate the
postorder sequence and verify that this all works. We even check for
using alternating iterators to trigger the lazy formation of RefSCCs
after mutation has occured.

It's worth noting that there are a reasonable number of likely
simplifications we can make past this. It isn't clear that we need to
keep the "LeafRefSCCs" around any more. But I've not removed that mostly
because I want this to be a more isolated change.

Differential Revision: https://reviews.llvm.org/D24219

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281716 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 10:20:17 +00:00