Commit Graph

145924 Commits

Author SHA1 Message Date
Amjad Aboud
a90eb62d9e [X86] Generate VZEROUPPER for Skylake-avx512.
VZEROUPPER should not be issued on Knights Landing (KNL), but on Skylake-avx512 it should be.

Differential Revision: https://reviews.llvm.org/D29874

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296859 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-03 09:03:24 +00:00
Sjoerd Meijer
f43aabc824 [AArch64AsmParser] rewrite of function parseSysAlias
This is a cleanup/rewrite of the parseSysAlias function. It was not using the
tablegen instruction descriptions, but was “manually” matching the mnemonics
and recreating the operands whereas all this information is already in
tablegen; all this code has been replaced with calls to lookupXYZByName
tablegen calls.

Differential Revision: https://reviews.llvm.org/D30491


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296857 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-03 08:12:47 +00:00
Igor Breger
a59e6d2210 [GlobalISel][X86] Support float/double and vector types.
Summary: [GlobalISel][X86] Add support for f32/f64 and vector types in RegisterBank and InstructionSelector.

Reviewers: delena, zvi

Reviewed By: zvi

Subscribers: dberris, rovka, llvm-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D30533

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296856 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-03 08:06:46 +00:00
Peter Collingbourne
40d79c6b9d Revert r296730, "cmake: Configure the ThinLTO cache directory when using ELF lld or gold."
Causes a build failure on the clang-with-thin-lto-ubuntu bot.
http://lab.llvm.org:8011/builders/clang-with-thin-lto-ubuntu/builds/2117/steps/build-stage3-compiler/logs/stdio

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296850 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-03 02:00:22 +00:00
Evgeniy Stepanov
1dcd685fa8 [msan] Handle x86_sse_stmxcsr and x86_sse_ldmxcsr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296848 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-03 01:12:43 +00:00
Adrian Prantl
7b7499a7a6 LiveDebugValues: Assume calls never clobber SP.
A call should never modify the stack pointer, but some backends are
not so sure about this and never list SP in the regmask. For the
purposes of LiveDebugValues we assume a call never clobbers SP. We
already have a similar workaround in DbgValueHistoryCalculator (which
we hopefully can retire soon).

This fixes the availabilty of local ASANified variables on AArch64.

rdar://problem/27757381

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296847 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-03 01:08:25 +00:00
Eugene Zelenko
f4f67a0c55 [ProfileData] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296846 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-03 01:07:34 +00:00
Kyle Butt
c160e2a10f CodeGen: BlockPlacement: Precompute layout for chains of triangles.
For chains of triangles with small join blocks that can be tail duplicated, a
simple calculation of probabilities is insufficient. Tail duplication
can be profitable in 3 different ways for these cases:

1) The post-dominators marked 50% are actually taken 56% (This shrinks with
   longer chains)
2) The chains are statically correlated. Branch probabilities have a very
   U-shaped distribution.
   [http://nrs.harvard.edu/urn-3:HUL.InstRepos:24015805]
   If the branches in a chain are likely to be from the same side of the
   distribution as their predecessor, but are independent at runtime, this
   transformation is profitable. (Because the cost of being wrong is a small
   fixed cost, unlike the standard triangle layout where the cost of being
   wrong scales with the # of triangles.)
3) The chains are dynamically correlated. If the probability that a previous
   branch was taken positively influences whether the next branch will be
   taken
We believe that 2 and 3 are common enough to justify the small margin in 1.

The code pre-scans a function's CFG to identify this pattern and marks the edges
so that the standard layout algorithm can use the computed results.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296845 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-03 01:00:22 +00:00
Evgeniy Stepanov
2543166ec1 [msan] Remove stale comments.
ClStoreCleanOrigin flag was removed back in 2014.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296844 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-03 00:25:56 +00:00
Matt Arsenault
003f1a56c5 AMDGPU: Fix missing dominator tree dependency
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296842 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-02 23:50:51 +00:00
Peter Collingbourne
d8035f7f14 ThinLTOBitcodeWriter: Do not follow operand edges of type GlobalValue when looking for virtual functions.
Such edges may otherwise result in infinite recursion if a pointer to a vtable
is reachable from the vtable itself. This can happen in practice if a TU
defines the ABI types used to implement RTTI, and is itself compiled with RTTI.

Fixes PR32121.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296839 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-02 23:10:17 +00:00
Daniel Berlin
03c7f20105 Move defClobbersUseOrDef to being a protected member of a class since we don't want anyone else using it
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296838 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-02 23:06:46 +00:00
Nikolai Bozhenov
ba60b2bba2 [BypassSlowDivision] Use ValueTracking to simplify run-time checks
ValueTracking is used for more thorough analysis of operands. Based on the
analysis, either run-time checks can be simplified (e.g. check only one operand
instead of two) or the transformation can be avoided. For example, it is quite
often the case that a divisor is promoted from a shorter type and run-time
checks for it are redundant.

With additional compile-time analysis of values, two special cases naturally
arise and are addressed by the patch:

 1) Both operands are known to be short enough. Then, the long division can be
    simply replaced with a short one without CFG modification.

 2) If a division is unsigned and the dividend is known to be short then the
    long division is not needed at all. Because if the divisor is too big for
    short division then the quotient is obviously zero (and the remainder is
    equal to the dividend). Actually, the division is not needed when
    (divisor > dividend).

Differential Revision: https://reviews.llvm.org/D29897


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296832 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-02 22:12:15 +00:00
Tom Stellard
cc946df67a CMake: Clean up VersionFromVCS.cmake
Summary:
Fix a few problems in VersionFromVCS.cmake to make it more reliable:

- Stop using git svn info to retrieve the svn revision.  I am unable to
  determine what the svn revision returned by this command means.
  During my testing this command returned a revision from a month
  ago which was not the HEAD of any of my local branches.

  Also, this revision was never actually added to the version string due
  to a typo in the script.  All it was used for was to reject the
  revision number returned by git svn find-rev HEAD when the revision
  numbers didn't match.

- Populate GIT_COMMIT even when we detect a git repo without any
  svn information.

Reviewers: mehdi_amini, beanz

Reviewed By: beanz

Subscribers: mgorny, llvm-commits

Differential Revision: https://reviews.llvm.org/D30092

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296829 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-02 22:05:13 +00:00
Nikolai Bozhenov
7c6958332a [BypassSlowDivision] Refactor fast division insertion logic (NFC)
The most important goal of the patch is to break large insertFastDiv function
into separate pieces, so that later a different fast insertion logic can be
implemented using some of these pieces.

Differential Revision: https://reviews.llvm.org/D29896


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296828 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-02 22:05:07 +00:00
Taewook Oh
15497c13fd [DAGCombiner] Fix DebugLoc propagation when folding !(x cc y) -> (x !cc y)
Summary:
Currently, when 't1: i1 = setcc t2, t3, cc' followed by 't4: i1 = xor t1, Constant:i1<-1>' is folded into 't5: i1 = setcc t2, t3 !cc', SDLoc of newly created SDValue 't5' follows SDLoc of 't4', not 't1'. However, as the opcode of newly created SDValue is 'setcc', it make more sense to take DebugLoc from 't1' than 't4'. For the code below

```
extern int bar();
extern int baz();

int foo(int x, int y) {
  if (x != y)
    return bar();
  else
    return baz();
}
```

, following is the bitcode representation of 'foo' at the end of llvm-ir level optimization:

```
define i32 @foo(i32 %x, i32 %y) !dbg !4 {
entry:
  tail call void @llvm.dbg.value(metadata i32 %x, i64 0, metadata !9, metadata !11), !dbg !12
  tail call void @llvm.dbg.value(metadata i32 %y, i64 0, metadata !10, metadata !11), !dbg !13
  %cmp = icmp ne i32 %x, %y, !dbg !14
  br i1 %cmp, label %if.then, label %if.else, !dbg !16

if.then:                                          ; preds = %entry
  %call = tail call i32 (...) @bar() #3, !dbg !17
  br label %return, !dbg !18

if.else:                                          ; preds = %entry
  %call1 = tail call i32 (...) @baz() #3, !dbg !19
  br label %return, !dbg !20

return:                                           ; preds = %if.else, %if.then
  %retval.0 = phi i32 [ %call, %if.then ], [ %call1, %if.else ]
  ret i32 %retval.0, !dbg !21
}

!14 = !DILocation(line: 5, column: 9, scope: !15)
!16 = !DILocation(line: 5, column: 7, scope: !4)

```

As you can see, in 'entry' block, 'icmp' instruction and 'br' instruction have different debug locations. However, with current implementation, there's no distinction between debug locations of these two when they are lowered to asm instructions. This is because 'icmp' and 'br' become 'setcc' 'xor' and 'brcond' in SelectionDAG, where SDLoc of 'setcc' follows the debug location of 'icmp' but SDLOC of 'xor' and 'brcond' follows the debug location of 'br' instruction, and SDLoc of 'xor' overwrites SDLoc of 'setcc' when they are folded. This patch addresses this issue.

Reviewers: atrick, bogner, andreadb, craig.topper, aprantl

Reviewed By: andreadb

Subscribers: jlebar, mkuper, jholewinski, andreadb, llvm-commits

Differential Revision: https://reviews.llvm.org/D29813

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296825 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-02 21:58:35 +00:00
Sanjay Patel
0eec3b0c78 [DAG] early exit to improve readability and formatting of visitMemCmpCall(); NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296824 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-02 21:56:43 +00:00
Krzysztof Parzyszek
06a22af389 [Hexagon] Pick the right branch opcode depending on branch probabilities
Specifically, pick the opcode with the correct branch prediction, i.e.
jump:t or jump:nt.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296821 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-02 21:49:49 +00:00
Tobias Grosser
2f35f8a7a2 Revert "AMDGPU: Re-do update for branch-relaxation test"
This commit also relied on r296812, which I just reverted. We should probably
apply it again, after the r296812 has been discussed and been reapplied in some
variant.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296820 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-02 21:47:51 +00:00
Kyle Butt
ce9b88e1ed CodeGen: MachineBlockPlacement: Remove the unused outlining heuristic.
Outlining optional branches isn't a good heuristic, and it's never been
on by default. Remove it to clean things up.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296818 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-02 21:44:24 +00:00
Eli Friedman
617c526c5c [ARM] Fix insert point for store rescheduling.
In ARMPreAllocLoadStoreOpt::RescheduleOps, LastOp should be the last
operation which we want to merge. If we break out of the loop because
an operation has the wrong offset, we shouldn't use that operation
as LastOp.

This patch fixes some cases where we would move stores to the wrong
insert point.

Re-commit with a fix to increment NumMove in the right place.

Differential Revision: https://reviews.llvm.org/D30124



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296815 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-02 21:39:39 +00:00
Tobias Grosser
da5173f8bf Revert "Fix PR 24415 (at least), by making our post-dominator tree behavior sane."
and also "clang-format GenericDomTreeConstruction.h, since the current
formatting makes it look like their is a bug in the loop indentation, and there
is not"

This reverts commit r296535.

There are still some open design questions which I would like to discuss. I
revert this for Daniel (who gave the OK), as he is on vacation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296812 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-02 21:08:37 +00:00
Guozhi Wei
e225b39cd4 [PPC] Fix code generation for bswap(int32) followed by store16
This patch fixes pr32063.

Current code in PPCTargetLowering::PerformDAGCombine can transform

bswap
store

into a single PPCISD::STBRX instruction. but it doesn't consider the case that the operand size of bswap may be larger than store size. When it occurs, we need 2 modifications,

1 For the last operand of PPCISD::STBRX, we should not use DAG.getValueType(N->getOperand(1).getValueType()), instead we should use cast<StoreSDNode>(N)->getMemoryVT().

2 Before PPCISD::STBRX, we need to shift the original operand of bswap to the right side.

Differential Revision: https://reviews.llvm.org/D30362



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296811 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-02 21:07:59 +00:00
Zachary Turner
f3491b21c5 [Support] Move Stream library from MSF -> Support.
After several smaller patches to get most of the core improvements
finished up, this patch is a straight move and header fixup of
the source.

Differential Revision: https://reviews.llvm.org/D30266

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296810 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-02 20:52:51 +00:00
Chad Rosier
e1c51407af [AArch64] Extend redundant copy elimination pass to handle non-zero stores.
This patch extends the current functionality of the AArch64 redundant copy
elimination pass to handle non-zero cases such as:

BB#0:
  cmp x0, #1
  b.eq .LBB0_1
.LBB0_1:
  orr x0, xzr, #0x1  ; <-- redundant copy; x0 known to hold #1.

Differential Revision: https://reviews.llvm.org/D29344

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296809 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-02 20:48:11 +00:00
Sanjay Patel
e5601be82e [DAG] improve documentation comments; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296808 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-02 20:48:08 +00:00
Vadzim Dambrouski
c5a81e8618 [MSP430] Add SRet support to MSP430 target
This patch adds support for struct return values to the MSP430
target backend. It also reverses the order of argument and return
registers in the calling convention to bring it into closer
alignment with the published EABI from TI.

Patch by Andrew Wygle (awygle).

Differential Revision: https://reviews.llvm.org/D29069

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296807 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-02 20:25:10 +00:00
Evgeny Stupachenko
8c81a9ed04 The patch fixes r296770
Summary:

Extend -unroll-partial-threshold to 200 for runtime-loop3.ll test
as epilogue unroll initially add 1 more IV to the loop.

From: Evgeny Stupachenko <evstupac@gmail.com>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296803 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-02 19:41:38 +00:00
Artem Belevich
5881745667 [NVPTX] Reduce amount of boilerplate code used to select load instruction opcode.
Make opcode selection code for the load instruction a bit easier
to read and maintain.

This patch also catches number of f16 load/store variants that were
not handled before.

Differential Revision: https://reviews.llvm.org/D30513

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296785 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-02 19:14:14 +00:00
Artem Belevich
78a75787a3 [NVPTX] Added missing LDU/LDG intrinsics for f16.
Differential Revision: https://reviews.llvm.org/D30512

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296784 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-02 19:14:10 +00:00
Simon Pilgrim
e6879dc1ba Fix some Wdocumentation warnings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296783 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-02 18:59:07 +00:00
Simon Pilgrim
fbaf6773a0 [X86][MMX] Fixed i32 extraction on 32-bit targets
MMX extraction often ends up as extract_i32(bitcast_v2i32(extract_i64(bitcast_v1i64(x86mmx v), 0)), 0) which fails to simplify on 32-bit targets as i64 isn't legal

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296782 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-02 18:56:06 +00:00
Vassil Vassilev
c59b65941e Cast to the right type on Windows.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296778 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-02 18:12:59 +00:00
Krzysztof Parzyszek
0110e749d0 [Hexagon] Skip blocks that define vector predicate registers in early-if
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296777 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-02 18:10:59 +00:00
Vassil Vassilev
409bc1cbe6 Remove redundant include.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296775 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-02 18:04:44 +00:00
Vassil Vassilev
3983dc252d Reland r296442 with modifications reverted in r296463.
Original commit message:

"Allow externally dlopen-ed libraries to be registered as permanent libraries.

This is also useful in cases when llvm is in a shared library. First we dlopen
the llvm shared library and then we register it as a permanent library in order
to keep the JIT and other services working.

Patch reviewed by Vedant Kumar (D29955)!"




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296774 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-02 17:56:45 +00:00
Krzysztof Parzyszek
3f339ad775 [Hexagon] Properly handle 'q' constraint in 128-byte vector mode
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296772 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-02 17:50:24 +00:00
Nemanja Ivanovic
6981f9a951 [PowerPC][ELFv2ABI] Allocate parameter area on-demand to reduce stack frame size
This patch reduces the stack frame size by not allocating the parameter area if
it is not required. In the current implementation LowerFormalArguments_64SVR4
already handles the parameter area, but LowerCall_64SVR4 does not
(when calculating the stack frame size). What this patch does is make
LowerCall_64SVR4 consistent with LowerFormalArguments_64SVR4.

Committing on behalf of Hiroshi Inoue.

Differential Revision: https://reviews.llvm.org/D29881


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296771 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-02 17:38:59 +00:00
Evgeny Stupachenko
c40a2f9b2a The patch turns on epilogue unroll for loops with constant recurency start.
Summary:

Set unroll remainder to epilog if a loop contains a phi with constant parameter:

  loop:
  pn = phi [Const, PreHeader], [pn.next, Latch]
  ...

Reviewer: hfinkel

Differential Revision: http://reviews.llvm.org/D27004

From: Evgeny Stupachenko <evstupac@gmail.com>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296770 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-02 17:38:46 +00:00
Sanjay Patel
d541a8113c [DAGCombiner] avoid assertion when folding binops with opaque constants
This bug was introduced with:
https://reviews.llvm.org/rL296699

There may be a way to loosen the restriction, but for now just bail out
on any opaque constant.

The tests show that opacity is target-specific. This goes back to cost
calculations in ConstantHoisting based on TTI->getIntImmCost().


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296768 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-02 17:18:56 +00:00
Adam Nemet
6a466e7794 New tool: opt-diff.py
This tool allows generating the different between two optimization record
files.  The result is a YAML file too that can be visualized with opt-viewer.

This is very useful to see what optimization were added and removed by a
change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296767 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-02 17:00:59 +00:00
Adam Nemet
5bf944fd37 [opt-viewer] Treat remarks with different attributes as different
We used to exclude arguments but for a diffed YAML file, it's interesting to
show these as changes.

Turns out this also affects gvn/LoadClobbered because we used to squash
multiple entries of this on the same line even if they reported clobbers
by *different* instructions.  This increases the number of unique entries now
and the share of gvn/LoadClobbered.

Total number of remarks      902287

Top 10 remarks by pass:
  inline                         43%
  gvn                            37%
  licm                           11%
  loop-vectorize                  4%
  asm-printer                     3%
  regalloc                        1%
  loop-unroll                     1%
  inline-cost                     0%
  slp-vectorizer                  0%
  loop-delete                     0%

Top 10 remarks:
  gvn/LoadClobbered              33%
  inline/Inlined                 16%
  inline/CanBeInlined            14%
  inline/NoDefinition             7%
  licm/Hoisted                    6%
  licm/LoadWithLoopInvariantAddressInvalidated  5%
  gvn/LoadElim                    3%
  asm-printer/InstructionCount    3%
  inline/TooCostly                2%
  loop-vectorize/MissedDetails    2%

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296766 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-02 17:00:56 +00:00
Adam Nemet
76f5727a33 [opt-viewer] Don't use __getattr__ for missing YAML attributes
__getattr__ does not work well with debugging.  If the attribute function has
a run-time error, a missing attribute is reported instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296765 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-02 17:00:53 +00:00
Adam Nemet
40561164f5 [opt-viewer] Sort entries with identical hotness by source line
We want entries that are close to each other in the source appear next to each
other.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296764 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-02 17:00:49 +00:00
David Bozier
05f3b7323d Allow use of spaces in Bugpoint ‘--compile-command’ argument
Bug-Point functionality needs extending due to the patch D29185 by bd1976llvm (Allow llvm's build and test systems to support paths with spaces ). It requires Bugpoint to accept the use of spaces within ‘--compile-command’ tokens.

Details
Bugpoint uses the argument ‘--compile-command’ to pass in a command line argument as a string, the string is tokenized by the ‘lexCommand’ function using spaces as a delimiter. Patch D29185 will cause the unit test compile-custom.ll to fail as spaces are now required within tokens and as a delimiter. This patch allows the use of escape characters as below:

Two consecutive '\' evaluate to a single '\'.
A space after a '\' evaluates to a space that is not interpreted as a delimiter.
Any other instances of the '\' character are removed.

Committed on behalf of Owen Reynolds

Differential revision: https://reviews.llvm.org/D29940



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296763 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-02 16:50:48 +00:00
Sanjay Patel
131b639126 fix typo in comment; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296760 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-02 16:37:24 +00:00
Geoff Berry
7bc404756c Re-apply "[GVNHoist] Move GVNHoist to function simplification part of pipeline."
This re-applies r289696, which caused TSan perf regression, which has
since been addressed in separate changes (see PR for details).

See PR31382.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296759 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-02 16:16:47 +00:00
Tim Northover
d35d48c9b0 GlobalISel: record correct stack usage for signext parameters.
The CallingConv.td rules allocate 8 bytes for these kinds of arguments
on AAPCS targets, but we were only recording the smaller amount. The
difference is theoretical on AArch64 because we don't actually store
more than the smaller amount, but it's still much better to have these
two components in agreement.

Based on Diana Picus's ARM equivalent patch (where it matters a lot
more).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296754 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-02 15:34:18 +00:00
Bjorn Pettersson
4f2d8229c1 [InstCombine] Avoid faulty combines of select-cmp-br
Summary:
When InstCombine is optimizing certain select-cmp-br patterns
it replaces the result of the select in uses outside of the
basic block containing the select. This is only legal if the
path from the select to the outside use is disjoint from all
other paths out from the originating basic block.

The problem found was that InstCombiner::replacedSelectWithOperand
did not consider the case when both edges out from the br pointed
to the same label. In that case the paths aren't disjoint and the
transformation is illegal. This patch avoids the faulty rewrites
by verifying that there is a single flow to the successor where
we want to replace uses.

Reviewers: llvm-commits, spatel, majnemer

Differential Revision: https://reviews.llvm.org/D30455

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296752 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-02 15:18:58 +00:00
Matthew Simpson
201896c9fd [ARM/AArch64] Update costs for interleaved accesses with wide types
After r296750, we're able to match interleaved accesses having types wider than
128 bits. This patch updates the associated TTI costs.

Differential Revision: https://reviews.llvm.org/D29675

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296751 91177308-0d34-0410-b5e6-96231b3b80d8
2017-03-02 15:15:35 +00:00