39947 Commits

Author SHA1 Message Date
Ahmed Bougacha
c49f5e8a93 [AArch64][GlobalISel] Add default regbank mapping for int<>FP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281739 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 15:12:46 +00:00
Ahmed Bougacha
d705c9fe79 [AArch64][GlobalISel] Add default regbank mapping for G_FCMP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281738 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 15:12:43 +00:00
Ahmed Bougacha
16527fa797 [AArch64][GlobalISel] Add default regbank mapping for FP ops.
These should have all their operands - even scalars - go on FPR.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281737 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 15:12:40 +00:00
Ahmed Bougacha
c3852f5056 [AArch64][GlobalISel] Add default regbank mappings for mixed-type ops.
We used to only support instructions with same-type operands.
Instead, use the per-register type information to map each
operand more accurately.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281734 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 14:44:51 +00:00
Simon Dardis
0057769961 [mips] Fix previous revert r281726.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281729 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 14:16:23 +00:00
Keith Walker
7435b28542 Place the lowered phi instruction(s) before the DEBUG_VALUE entry
When a phi node is finally lowered to a machine instruction it is
important that the lowered "load" instruction is placed before the
associated DEBUG_VALUE entry describing the value loaded.

Renamed the existing SkipPHIsAndLabels to SkipPHIsLabelsAndDebug to
more fully describe that it also skips debug entries. Then used the
"new" function SkipPHIsAndLabels when the debug information should not
be skipped when placing the lowered "load" instructions so that it is
placed before the debug entries.

Differential Revision: https://reviews.llvm.org/D23760 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281727 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 14:07:29 +00:00
Simon Dardis
ffabbc5291 Revert "[mips] Fix aui/daui/dahi/dati for MIPSR6"
This reverts r281724. Still need dsanders to accept this.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281726 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 13:56:05 +00:00
Simon Dardis
e38b67fe3b [mips] Fix aui/daui/dahi/dati for MIPSR6
For compatiblity with binutils, define these instructions to take
two registers with a 16bit unsigned immediate. Both of the registers
have to be same for dahi and dati.

Reviewers: vkalintiris, dsanders, zoran.jovanovic
 
Differential Review: https://reviews.llvm.org/D21473



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281724 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 13:50:43 +00:00
Sjoerd Meijer
ea7e0cd04b Reverting r281719, this is causing buildbot failures and timeouts again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281722 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 13:16:52 +00:00
Ahmed Bougacha
89f7a48a4a [AArch64][GlobalISel] Use the generic DefaultMapping as the default.
This lets generic logic handle the common case, instead of having to
implement applyMappingImpl for each instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281720 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 12:33:34 +00:00
Sjoerd Meijer
f9c0a77050 This is an attempt to reapply r280808: [ARM] Lower UDIV+UREM to UDIV+MLS
(and the same for SREM)

This was causing buildbot failures earlier (time outs in the LNT suite).
However, we haven't been able to reproduce this and are suspecting this
was caused by another (reverted) patch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281719 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 12:10:09 +00:00
Eric Liu
6c1574bca5 Trying to fix Mangler memory leak in TargetLoweringObjectFile.
Summary:
`TargetLoweringObjectFile` can be re-used and thus `TargetLoweringObjectFile::Initialize()`
can be called multiple times causing `Mang` pointer memory leak.

Reviewers: echristo

Subscribers: llvm-commits, mehdi_amini

Differential Revision: https://reviews.llvm.org/D24659

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281718 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 11:50:57 +00:00
James Molloy
d95bddac05 [ARM] Promote small global constants to constant pools
If a constant is unamed_addr and is only used within one function, we can save
on the code size and runtime cost of an indirection by changing the global's storage
to inside the constant pool. For example, instead of:

      ldr r0, .CPI0
      bl printf
      bx lr
    .CPI0: &format_string
    format_string: .asciz "hello, world!\n"

We can emit:

      adr r0, .CPI0
      bl printf
      bx lr
    .CPI0: .asciz "hello, world!\n"

This can cause significant code size savings when many small strings are used in one
function (4 bytes per string).

This recommit contains fixes for a nasty bug related to fast-isel fallback - because
fast-isel doesn't know about this optimization, if it runs and emits references to
a string that we inline (because fast-isel fell back to SDAG) we will end up
with an inlined string and also an out-of-line string, and we won't emit the
out-of-line string, causing backend failures.

It also contains fixes for emitting .text relocations which made the sanitizer
bots unhappy.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281715 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 10:17:04 +00:00
Eric Christopher
88a23b6016 Move the Mangler from the AsmPrinter down to TLOF and clean up the
TLOF API accordingly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281708 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 07:33:15 +00:00
Eric Christopher
2ce67fb75a Remove unused function getMang().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281707 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-16 07:32:58 +00:00
Evandro Menezes
a5437a6d55 [AArch64] Support for FP FMA when -ffp-contract=fast
Currently, the machine combiner can proceed matching when -ffast-math is on.
It should also match when only -ffp-contract=fast is specified as was the
case before when DAGCombiner was doing the job.

Patch by: Abderrazek Zaafrani <a.zaafrani@samsung.com>.

Differential Revision: https://reviews.llvm.org/D24366

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281649 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-15 19:55:23 +00:00
Evgeniy Stepanov
745df3296d Revert "[ARM] Promote small global constants to constant pools"
This reverts r281604, which adds text relocations to ARM binaries.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281645 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-15 19:13:32 +00:00
Simon Dardis
c2c0b27fee [mips][ias] Enable IAS by default for N64 on Debian mips64el.
Unfortunately we can't enable it for all N64 because it is not yet possible to
distinguish N32 from N64.

N64 has been confirmed to produce identical (within reason) objects to GAS
during stage 2 of compiler recursion on N64-abit Fedora. Unfortunately,
Fedora's triples do not distinguish N32 from N64 so I can't enable it by
default there. I'm currently repeating this testing for Debian mips64el but
it's very unlikely to produce a different result.

Patch by: Daniel Sanders

Reviewers: sdardis

Differential Review: https://reviews.llvm.org/D22678


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281607 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-15 13:13:01 +00:00
James Molloy
095eb00556 [ARM] Promote small global constants to constant pools
If a constant is unamed_addr and is only used within one function, we can save
on the code size and runtime cost of an indirection by changing the global's storage
to inside the constant pool. For example, instead of:

      ldr r0, .CPI0
      bl printf
      bx lr
    .CPI0: &format_string
    format_string: .asciz "hello, world!\n"

We can emit:

      adr r0, .CPI0
      bl printf
      bx lr
    .CPI0: .asciz "hello, world!\n"

This can cause significant code size savings when many small strings are used in one
function (4 bytes per string).

This recommit contains fixes for a nasty bug related to fast-isel fallback - because
fast-isel doesn't know about this optimization, if it runs and emits references to
a string that we inline (because fast-isel fell back to SDAG) we will end up
with an inlined string and also an out-of-line string, and we won't emit the
out-of-line string, causing backend failures.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281604 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-15 12:30:27 +00:00
Tim Northover
8c9a9af652 GlobalISel: legalize GEP instructions with small offsets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281602 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-15 11:02:19 +00:00
Tim Northover
3d658a6577 GlobalISel: relax type constraints on G_ICMP to allow pointers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281600 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-15 10:40:38 +00:00
Tim Northover
3d94178ab6 GlobalISel: remove "unsized" LLT
It was only really there as a sentinel when instructions had to have precisely
one type. Now that registers are typed, each register really has to have a type
that is sized.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281599 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-15 10:09:59 +00:00
Tim Northover
cdce758a72 GlobalISel: cache pointer sizes in LLT
Otherwise everything that needs to work out what size they are has to keep a
DataLayout handy, which is a bit silly and very annoying.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281597 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-15 09:20:34 +00:00
Matt Arsenault
93e6e5414d Finish renaming remaining analyzeBranch functions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281535 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-14 20:43:16 +00:00
Evgeniy Stepanov
eb967fb89e Revert "[ARM] Promote small global constants to constant pools"
Breaks Android tests by introducing text relocations to ARM binaries.

http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux/builds/25362/steps/run%20asan%20lit%20tests%20%5Barm%2Fbullhead-userdebug%2FMTC20F%5D/logs/stdio

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281526 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-14 20:02:30 +00:00
Matt Arsenault
aceeb33943 Revert "AMDGPU: Use SOPK compare instructions"
Accidentally committed

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281514 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-14 18:04:42 +00:00
Matt Arsenault
fff5113a50 AMDGPU: Use SOPK compare instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281513 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-14 18:03:53 +00:00
Matt Arsenault
b1a710d5f0 Make analyzeBranch family of instruction names consistent
analyzeBranch was renamed to use lowercase first, rename
the related set to match.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281506 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-14 17:24:15 +00:00
Matt Arsenault
ab302cda5e AArch64: Use TTI branch functions in branch relaxation
The main change is to return the code size from
InsertBranch/RemoveBranch.

Patch mostly by Tim Northover

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281505 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-14 17:23:48 +00:00
Sanjay Patel
b4dbf03541 [x86] fix formatting; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281504 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-14 17:23:18 +00:00
Simon Pilgrim
c348bc4aeb [X86][SSE] Improve recognition of i64 sitofp conversions that can be performed as i32 (PR29078)
Until AVX512DQ we only support i64/vXi64 sitofp conversion as scalars.

This patch sees if the sign bit extends far enough that we can truncate to a i32 type and then perform sitofp without loss of precision.

Differential Revision: https://reviews.llvm.org/D24345

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281502 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-14 17:15:26 +00:00
Simon Pilgrim
e65dbf0620 [X86][SSE] Don't use PSHUFD directly - lower with generic shuffle
Remove the last user of the old getTargetShuffleNode helpers

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281499 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-14 17:04:22 +00:00
Sanjay Patel
47eb9d5b63 getValueType().getScalarSizeInBits() -> getScalarValueSizeInBits(), round 2 ; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281498 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-14 16:54:10 +00:00
Sanjay Patel
c0a42ffc17 getVectorElementType().getSizeInBits() -> getScalarSizeInBits() ; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281495 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-14 16:37:15 +00:00
Sanjay Patel
a7c48ccd3f getValueType().getSizeInBits() -> getValueSizeInBits() ; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281493 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-14 16:05:51 +00:00
Matt Arsenault
0f7125844e AMDGPU: Support folding FrameIndex operands
This avoids test regressions in a future commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281491 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-14 15:51:33 +00:00
Sanjay Patel
04e0167eac getValueType().getScalarSizeInBits() -> getScalarValueSizeInBits() ; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281490 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-14 15:43:44 +00:00
Sanjay Patel
f4559b5e2c getScalarType().getSizeInBits() -> getScalarSizeInBits() ; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281489 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-14 15:21:00 +00:00
Matt Arsenault
8bc95d0a47 AMDGPU: Improve splitting 64-bit bit ops by constants
This addresses a TODO to handle operations besides and. This
also starts eliminating no-op operations with a constant that
can emerge later.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281488 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-14 15:19:03 +00:00
James Molloy
b50cea7150 [ARM] Promote small global constants to constant pools
If a constant is unamed_addr and is only used within one function, we can save
on the code size and runtime cost of an indirection by changing the global's storage
to inside the constant pool. For example, instead of:

      ldr r0, .CPI0
      bl printf
      bx lr
    .CPI0: &format_string
    format_string: .asciz "hello, world!\n"

We can emit:

      adr r0, .CPI0
      bl printf
      bx lr
    .CPI0: .asciz "hello, world!\n"

This can cause significant code size savings when many small strings are used in one
function (4 bytes per string).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281484 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-14 14:47:27 +00:00
Simon Pilgrim
3824319ab4 [X86][SSE] Removed unused getTargetShuffleNode function
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281481 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-14 14:30:00 +00:00
Nemanja Ivanovic
7328eb7558 Fix code-gen crash on Power9 for insert_vector_elt with variable index (PR30189)
This patch corresponds to review:
https://reviews.llvm.org/D24021

In the initial implementation of this instruction, I forgot to account for
variable indices. This patch fixes PR30189 and should probably be merged into
3.9.1 (I'll open a bug according to the new instructions).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281479 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-14 14:19:09 +00:00
Nemanja Ivanovic
3477191193 Adding missing directive for Power9.
There is currently no codegen for Power9 that depends on the directive
so this is NFC for now but will be important in the future. This was
missed in r268950 so I'm adding it now.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281473 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-14 14:09:39 +00:00
Simon Pilgrim
9320a1273e [X86][SSE] Don't blend vector shifts with MOVSS/MOVSD directly, lower from generic shuffle
Shuffle lowering will correctly lower to MOVSS/MOVSD/PBLEND, improving commutation opportunities

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281471 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-14 14:08:18 +00:00
James Molloy
9502e5be6f Revert "[Thumb] Teach ISel how to lower compares of AND bitmasks efficiently"
This reverts commit r281323. It caused chromium test failures and a selfhost failure.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281451 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-14 09:45:28 +00:00
Tim Northover
d40a5626fc GlobalISel: mark pointer stores as legal on AArch64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281448 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-14 08:28:54 +00:00
Sjoerd Meijer
82d457bf36 This reapplies r281304. The issue was that I had missed
to copy the new isAdd field in the tablegen data structure.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281447 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-14 08:20:03 +00:00
Elena Demikhovsky
ad1b22c748 AVX-512: Fixed a bug in kortest.z intrinsic
Lowering was wrong - X86ISD::SETCC node should return i8 type.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281446 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-14 08:06:54 +00:00
Igor Breger
3ef99c9f83 [AVX512BW] Change truncStore action (v16i16->v16i18). It can be legal only with AVX512VL.
Differential Revision: http://reviews.llvm.org/D24547

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281445 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-14 08:04:28 +00:00
Craig Topper
cb2901c00a [X86] Remove the VCVTSI2SD32 with rounding intrinsic. It's not used by clang and not needed since 32-bit integer to double is always exact.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281442 91177308-0d34-0410-b5e6-96231b3b80d8
2016-09-14 06:27:46 +00:00