Leftover from D22686; the passes can handle all the instructions
unconditionally; only isel needs to care whether to generate them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277549 91177308-0d34-0410-b5e6-96231b3b80d8
In this particular example we wouldn't want the smmls anyway (the value is
actually unused), but in general smmls does not provide the required flags
register so if that SUBE result is used we can't replace it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277541 91177308-0d34-0410-b5e6-96231b3b80d8
Fixed the last incorrect uses of llvm_unreachable() in the code
which were actually just cases of errors in the input Archives.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277540 91177308-0d34-0410-b5e6-96231b3b80d8
There were issues with simply reporting AttrUnknown on
previously-unknown values in CFLAnders. So, we now act *entirely*
conservatively for values we haven't seen before. As in the prior patch
(r277362), writing a lit test for this isn't exactly trivial. If someone
wants a test badly, I'm willing to try to write one.
Patch by Jia Chen.
Differential Revision: https://reviews.llvm.org/D23077
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277533 91177308-0d34-0410-b5e6-96231b3b80d8
Summary: We really want to move towards MemoryLocOrCall (or fix AA) everywhere, but for now, this lets us have a single instructionClobbersQuery.
Reviewers: george.burgess.iv
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D23072
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277530 91177308-0d34-0410-b5e6-96231b3b80d8
As agreed in post-commit review of r265388, I'm switching the flag to
its original value until the 90% runtime performance regression on
SingleSource/Benchmarks/Stanford/Bubblesort is addressed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277524 91177308-0d34-0410-b5e6-96231b3b80d8
We were relying on the misleadingly-names $status result to actually be the
status. Actually it's just a scratch register that may or may not be valid (and
is the inverse of the real ststus anyway). Success can be determined by
comparing the value loaded against the one we wanted to see for "cmpxchg
strong" loops like this.
Should fix PR28819.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277513 91177308-0d34-0410-b5e6-96231b3b80d8
This changes IRCE to "preserve" LCSSA and DomTree by recomputing them.
It still does not preserve LoopSimplify.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277505 91177308-0d34-0410-b5e6-96231b3b80d8
Summary:
Two types of stores are possible in pixel shaders: stores to memory that are
explicitly requested at the API level, and stores that are an implementation
detail of register spilling or lowering of arrays.
For the first kind of store, we must ensure that helper pixels have no effect
and hence WQM must be disabled. The second kind of store must always be
executed, because the written value may be loaded again in a way that is
relevant for helper pixels as well -- and there are no externally visible
effects anyway.
This is a candidate for the 3.9 release branch.
Reviewers: arsenm, tstellarAMD, mareko
Subscribers: arsenm, kzhuravl, llvm-commits
Differential Revision: https://reviews.llvm.org/D22675
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277504 91177308-0d34-0410-b5e6-96231b3b80d8
Attempt 2: Retryign after Tsan.mman test fix.
Attempt 1: Recommitting after fixing test.
When parsing assembly where the line comment syntax is not hash, the
lexer cannot distinguish between hash's that start a hash line comment
and one that is part of an assembly statement and must be distinguished
during parsing. Previously, this was incompletely handled by not checking
for EndOfStatement at the end of statements and interpreting hash
prefixed statements as comments.
Change EndOfStatement Parsing to check for Hash comments and reintroduce
Hash statement parsing to catch previously handled cases.
Reviewers: rnk, majnemer
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D23017
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277501 91177308-0d34-0410-b5e6-96231b3b80d8
Summary:
There are cases where uniform branch conditions are computed in VGPRs, and
we didn't correctly mark those as WQM.
The stray change in basic-branch.ll is because invoking the LiveIntervals
analysis leads to the detection of a dead register that would otherwise not
be seen at -O0.
This is a candidate for the 3.9 branch, as it fixes a possible hang.
Reviewers: arsenm, tstellarAMD, mareko
Subscribers: arsenm, llvm-commits, kzhuravl
Differential Revision: https://reviews.llvm.org/D22673
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277500 91177308-0d34-0410-b5e6-96231b3b80d8
Identify patterns where the address is aligned to an 8-byte boundary,
but both the base address and the constant offset are both proper
multiples of 4. In such cases, extract Base+4 into a separate instruc-
tion, and use S2_storerd_io, instead of using S4_storerd_rr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277497 91177308-0d34-0410-b5e6-96231b3b80d8
Recommitting after fixing overaggressive fastpath return in parsing.
Fix intel syntax special case identifier operands that refer to a constant
(e.g. .set <ID> n) to be interpreted as immediate not memory in parsing.
Associated commit to fix clang test commited shortly.
Reviewers: rnk
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D22585
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277489 91177308-0d34-0410-b5e6-96231b3b80d8
None of GlobalISel requires the property, but this lets us use the
verifier instead of rolling our own "all instructions selected" check.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277484 91177308-0d34-0410-b5e6-96231b3b80d8
After instruction selection, there should be no pre-isel generic
instructions remaining, nor should generic virtual registers be
used. Verify that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277483 91177308-0d34-0410-b5e6-96231b3b80d8
Selected: the InstructionSelect pass ran and all pre-isel generic
instructions have been eliminated; i.e., all instructions are now
target-specific or non-pre-isel generic instructions (e.g., COPY).
Since only pre-isel generic instructions can have generic virtual register
operands, this also means that all generic virtual registers have been
constrained to virtual registers (assigned to register classes) and that
all sizes attached to them have been eliminated.
This lets us enforce certain invariants across passes.
This property is GlobalISel-specific, but is always available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277482 91177308-0d34-0410-b5e6-96231b3b80d8
Fixes PR28670
Summary:
Rewrite the use optimizer to be less memory intensive and 50% faster.
Fixes PR28670
The new use optimizer works like a standard SSA renaming pass, storing
all possible versions a MemorySSA use could get in a stack, and just
tracking indexes into the stack.
This uses much less memory than caching N^2 alias query results.
It's also a lot faster.
The current version defers phi node walking to the normal walker.
Reviewers: george.burgess.iv
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D23032
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277480 91177308-0d34-0410-b5e6-96231b3b80d8
RegBankSelected functions shouldn't have any generic virtual
register not assigned to a bank. Verify that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277476 91177308-0d34-0410-b5e6-96231b3b80d8
RegBankSelected: the RegBankSelect pass ran and all generic virtual
registers have been assigned to a register bank.
This lets us enforce certain invariants across passes.
This property is GlobalISel-specific, but is always available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277475 91177308-0d34-0410-b5e6-96231b3b80d8
This patch enables the vectorizer to generate both scalar and vector versions
of an integer induction variable for a given loop. Previously, we only
generated a scalar induction variable if we knew all its users were going to be
scalar. Otherwise, we generated a vector induction variable. In the case of a
loop with both scalar and vector users of the induction variable, we would
generate the vector induction variable and extract scalar values from it for
the scalar users. With this patch, we now generate both versions of the
induction variable when there are both scalar and vector users and select which
version to use based on whether the user is scalar or vector.
Differential Revision: https://reviews.llvm.org/D22869
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277474 91177308-0d34-0410-b5e6-96231b3b80d8
RegBankSelect and InstructionSelect run after the legalizer and
require a Legalized function: check that all instructions are legal.
Note that this should be in the MachineVerifier, but it can't use the
MachineLegalizer as it's currently in the separate GlobalISel library.
Note that the RegBankSelect verifier checks have the same layering
problem, but we only use inline methods so end up not needing to link
against the GlobalISel library.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277472 91177308-0d34-0410-b5e6-96231b3b80d8
We currently use and test these, and select most of them. Mark them
as legal even though we don't go through the full ir->asm flow yet.
This doesn't currently have standalone tests, but the verifier will
soon learn to check that the regbankselect/select tests are legal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277471 91177308-0d34-0410-b5e6-96231b3b80d8
Legalized: The MachineLegalizer ran; all pre-isel generic instructions
have been legalized, i.e., all instructions are now one of:
- generic and always legal (e.g., COPY)
- target-specific
- legal pre-isel generic instructions.
This lets us enforce certain invariants across passes.
This property is GlobalISel-specific, but is always available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277470 91177308-0d34-0410-b5e6-96231b3b80d8
This is only used for debug prints, but the previous hardcoded ", "
caused it to be printed unnecessarily when OnlySet, and is annoying
when adding new properties.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277465 91177308-0d34-0410-b5e6-96231b3b80d8
This patch refactors the logic in collectLoopUniforms and
collectValuesToIgnore, untangling the concepts of "uniform" and "scalar". It
adds isScalarAfterVectorization along side isUniformAfterVectorization to
distinguish the two. Known scalar values include those that are uniform,
getelementptr instructions that won't be vectorized, and induction variables
and induction variable update instructions whose users are all known to be
scalar.
This patch includes the following functional changes:
- In collectLoopUniforms, we mark uniform the pointer operands of interleaved
accesses. Although non-consecutive, these pointers are treated like
consecutive pointers during vectorization.
- In collectValuesToIgnore, we insert a value into VecValuesToIgnore if it
isScalarAfterVectorization rather than isUniformAfterVectorization. This
differs from the previous functionaly in that we now add getelementptr
instructions that will not be vectorized into VecValuesToIgnore.
This patch also removes the ValuesNotWidened set used for induction variable
scalarization since, after the above changes, it is now equivalent to
isScalarAfterVectorization.
Differential Revision: https://reviews.llvm.org/D22867
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277460 91177308-0d34-0410-b5e6-96231b3b80d8
Recommitting after fixing test.
When parsing assembly where the line comment syntax is not hash, the
lexer cannot distinguish between hash's that start a hash line comment
and one that is part of an assembly statement and must be distinguished
during parsing. Previously, this was incompletely handled by not checking
for EndOfStatement at the end of statements and interpreting hash
prefixed statements as comments.
Change EndOfStatement Parsing to check for Hash comments and reintroduce
Hash statement parsing to catch previously handled cases.
Reviewers: rnk, majnemer
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D23017
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277459 91177308-0d34-0410-b5e6-96231b3b80d8
Added (sra (shl x, 16), 16) to the sext_16_node PatLeaf for ARM to
simplify some pattern matching. This has allowed several patterns
for smul* and smla* to be removed as well as making it easier to add
the matching for the corresponding instructions for Thumb2 targets.
Also added two Pat classes that are predicated on Thumb2 with the
hasDSP flag and UseMulOps flags. Updated the smul codegen test with
the wider range of patterns plus the ThumbV6 and ThumbV6T2 targets.
Differential Revision: https://reviews.llvm.org/D22908
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277450 91177308-0d34-0410-b5e6-96231b3b80d8
