37968 Commits

Author SHA1 Message Date
Kit Barton
db21c5a551 [SystemZ] Add support for additional branch extended mnemonics
Added support for extended mnemonics for the following branch instructions and
load/store-on-condition opcodes:

BR, LOCR, LOCGR, LOC, LOCG, STOC, STOCG

Phabricator: http://reviews.llvm.org/D19729

Committing on behalf of Zhan Liau

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269106 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-10 20:11:24 +00:00
Tim Northover
8189e3d887 ARM: stop emitting blx instructions for most calls on MachO.
I'm really not sure why we were in the first place, it's the linker's job to
convert between BL/BLX as necessary. Even worse, using BLX left Thumb calls
that could be locally resolved completely unencodable since all offsets to BLX
are multiples of 4.

rdar://26182344

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269101 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-10 19:17:47 +00:00
Konstantin Zhuravlyov
2147c01e5a [AMDGPU][NFC] Rename SIInsertNops -> SIDebuggerInsertNops
Differential Revision: http://reviews.llvm.org/D20117


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269098 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-10 18:33:41 +00:00
Dan Gohman
f02416f9ad [WebAssembly] Preliminary fast-isel support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269083 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-10 17:39:48 +00:00
Marcin Koscielnicki
9100579a4f [PR27599] [SystemZ] [SelectionDAG] Fix extension of atomic cmpxchg result.
Currently, SelectionDAG assumes 8/16-bit cmpxchg returns either a sign
extended result, or a zero extended result.  SystemZ takes a third
option by returning junk in the high bits (rotated contents of the other
bytes in the memory word).  In that case, don't use Assert*ext, and
zero-extend the result ourselves if a comparison is needed.

Differential Revision: http://reviews.llvm.org/D19800

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269075 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-10 16:49:04 +00:00
Daniel Sanders
32ba5cd276 [mips][ias] Make the default path unreachable in needsRelocateWithSymbol() (except for N64).
Following post-commit comments on r268900 from Rafael Espindola:
The missing relocations are now explicitly listed in the switch statement with
appropriate FIXME comments and the default path is now unreachable. The
temporary exception to this is that compound relocations for N64 still have a
default path that returns true. This is because fixing that case ought to be a
separate patch.

Also make R_MIPS_NONE return false since it has no effect on the section data.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269047 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-10 12:17:04 +00:00
Jonas Paulsson
32db7c31b2 [foldMemoryOperand()] Pass LiveIntervals to enable liveness check.
SystemZ (and probably other targets as well) can fold a memory operand
by changing the opcode into a new instruction that as a side-effect
also clobbers the CC-reg.

In order to do this, liveness of that reg must first be checked. When
LIS is passed, getRegUnit() can be called on it and the right
LiveRange is computed on demand.

Reviewed by Matthias Braun.
http://reviews.llvm.org/D19861

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269026 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-10 08:09:37 +00:00
Craig Topper
9abf0e829e [X86][AVX512] Strengthen the assertions from r269001. We need VLX to use the 128/256-bit move opcodes for extended registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269019 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-10 05:28:04 +00:00
Craig Topper
5937d7d9ab [X86] Add ZMM registers to the X86_INTR calling convention preserved mask when AVX512 is enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269018 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-10 05:28:02 +00:00
Craig Topper
7522f0e895 [X86] Update X86_INTR calling convention to save ZMM registers instead of YMM registers when AVX512 is enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269017 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-10 05:27:56 +00:00
Dan Gohman
01a542927d [WebAssembly] Move register stackification and coloring to a late phase.
Move the register stackification and coloring passes to run very late, after
PEI, tail duplication, and most other passes. This means that all code emitted
and expanded by those passes is now exposed to these passes. This also
eliminates the need for prologue/epilogue code to be manually stackified,
which significantly simplifies the code.

This does require running LiveIntervals a second time. It's useful to think
of these late passes not as late optimization passes, but as a domain-specific
compression algorithm based on knowledge of liveness information. It's used to
compress the code after all conventional optimizations are complete, which is
why it uses LiveIntervals at a phase when actual optimization passes don't
typically need it.

Differential Revision: http://reviews.llvm.org/D20075


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269012 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-10 04:24:02 +00:00
Matthias Braun
6a6190de10 CodeGen: Move TargetPassConfig from Passes.h to an own header; NFC
Many files include Passes.h but only a fraction needs to know about the
TargetPassConfig class. Move it into an own header. Also rename
Passes.cpp to TargetPassConfig.cpp while we are at it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269011 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-10 03:21:59 +00:00
Quentin Colombet
c2cb1b7b04 [X86][AVX512] Use the proper load/store for AVX512 registers.
When loading or storing AVX512 registers we were not using the AVX512
variant of the load and store for VR128 and VR256 like registers.
Thus, we ended up with the wrong encoding and actually were dropping the
high bits of the instruction. The result was that we load or store the
wrong register. The effect is visible only when we emit the object file
directly and disassemble it. Then, the output of the disassembler does
not match the assembly input.

This is related to llvm.org/PR27481.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269001 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-10 01:09:14 +00:00
Justin Lebar
9f9e951090 [NVPTX] Change begin/end inline asm comments to "begin/end inline asm".
Previously it was just "// inline asm", which made it tricky to read
code with lots of inline assembly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268994 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-10 00:31:22 +00:00
Derek Schuff
42a5196098 [WebAssembly] Disable 128-bit shift libcalls
Currently the signature of the functions
i128(i128, i32) aka void(i32, i64, i64, i32) doesn't match the signature
of the call emitted by the default lowering, void(i32, i64, i64).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268991 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-10 00:14:07 +00:00
Justin Bogner
6d523e1b0e SDAG: Stop relying on Select's return value in SystemZ's splitLargeImmediate. NFC
The call to Select on Upper here happens in an unusual order in order
to defeat the constant folding that getNode() does. Add a comment
explaining why we can't just move the Select to later to avoid a
Handle, and wrap the call to SelectCode in a handle so we don't need
its return value.

This is part of the work to have Select return void instead of an
SDNode *, which is in turn part of llvm.org/pr26808.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268990 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-09 23:54:23 +00:00
Quentin Colombet
d3fb1bcc0c [X86] Fix the AllRegs AVX calling convention.
We used to list registers that were not in the AVX space. In other
words, we were pushing registers that the ISA cannot encode
(YMM16-YMM31).

This is part of llvm.org/PR27481.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268983 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-09 22:37:05 +00:00
Quentin Colombet
efd0e153f3 [X86] Strengthen the setting of inline asm constraints for fp regclasses.
This is similar to r268953, but for floating point and vector register
classes.

Explanations:
The setting of the inline asm constraints was implicitly relying on the
order of the register classes in the file generated by tablegen.
Since, we do not have any control on that order, make sure we do not
depend on it anymore.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268973 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-09 21:24:31 +00:00
Simon Pilgrim
15a59473b3 [X86][SSE] Improve cost model for i64 vector comparisons on pre-SSE42 targets
As discussed on PR24888, until SSE42 we don't have access to PCMPGTQ for v2i64 comparisons, but the cost models don't reflect this, resulting in over-optimistic vectorizaton.

This patch adds SSE2 'base level' costs that match what a typical target is capable of and only reduces the v2i64 costs at SSE42.

Technically SSE41 provides a PCMPEQQ v2i64 equality test, but as getCmpSelInstrCost doesn't give us a way to discriminate between comparison test types we can't easily make use of this, otherwise we could split the cost of integer equality and greater-than tests to give better costings of each.

Differential Revision: http://reviews.llvm.org/D20057

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268972 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-09 21:14:38 +00:00
Quentin Colombet
b8b6ac5e09 [X86] Drop the 64-bit alignment for LOW32_ADDR_ACCESS register class.
The only 64-bit register in that register class is RIP and it will not
get spilled in the current ABIs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268963 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-09 19:50:30 +00:00
Quentin Colombet
5db7dd2a56 Reapply [X86] Add a new LOW32_ADDR_ACCESS_RBP register class.
This reapplies commit r268796, with a fix for the setting of the inline asm
constraints. I.e., "mark" LOW32_ADDR_ACCESS_RBP as a GR variant, so that the
regular processing of the GR operands (setting of the subregisters) happens.

Original commit log:
[X86] Add a new LOW32_ADDR_ACCESS_RBP register class.

ABIs like NaCl uses 32-bit addresses but have 64-bit frame.
The new register class reflects those constraints when choosing a
register class for a address access.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268955 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-09 19:01:46 +00:00
Quentin Colombet
3024e4486b [X86] Strengthen the setting of inline asm constraints.
The setting of the inline asm constraints was implicitly relying on the
order of the register classes in the file generated by tablegen.
Since, we do not have any control on that order, make sure we do not
depend on it anymore.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268953 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-09 19:01:35 +00:00
Nemanja Ivanovic
f9018a1eb7 [Power9] Add support for -mcpu=pwr9 in the back end
This patch corresponds to review:
http://reviews.llvm.org/D19683

Simply adds the bits for being able to specify -mcpu=pwr9 to the back end.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268950 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-09 18:54:58 +00:00
Krzysztof Parzyszek
13fc4ae0bf [Hexagon] Treat all conditional branches as predicted (not-taken by default)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268946 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-09 18:22:07 +00:00
Daniel Sanders
a2d03d2ed9 [mips] Fix a partially initialized member variable that was introduced in r268896.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268938 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-09 17:42:04 +00:00
Simon Pilgrim
826093255c Fixed unused but set variable warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268931 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-09 16:42:23 +00:00
Matt Arsenault
deeb131011 AMDGPU: Fold shift into cvt_f32_ubyteN
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268930 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-09 16:29:50 +00:00
Daniel Sanders
1cc844b098 [mips] Try to fix 'truncation from FindBestPredicateResult to bool' reported by MSVC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268928 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-09 15:50:15 +00:00
Daniel Sanders
8bc041ce85 [mips][ias] Attempt to fix 'not all control paths return a value' reported by MSVC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268927 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-09 15:37:52 +00:00
Daniel Sanders
43d2886cca [mips][micromips] Make getPointerRegClass() result depend on the instruction.
Summary:
Previously, it returned the GPR16MMRegClass for all instructions which was
incorrect for instructions like lwsp/lwgp and unnecesarily restricted the
permitted registers for instructions like lw32.

This fixes quite a few of the -verify-machineinstrs errors reported in PR27458.
I've only added -verify-machineinstrs to one test in this change since I
understand there is a plan to enable the verifier by default.

Reviewers: hvarga, zbuljan, zoran.jovanovic, sdardis

Subscribers: dsanders, llvm-commits, sdardis

Differential Revision: http://reviews.llvm.org/D19873

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268918 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-09 13:38:25 +00:00
Simon Pilgrim
0f420ada79 [X86][SSE] Added TODO comment to add support for AVX512 mask registers to shuffle comments
This came up in discussion on D19198

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268915 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-09 13:30:16 +00:00
Daniel Sanders
b2292f8443 [mips] Fix use after free and an unnecessary copy introduced in r268896.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268913 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-09 13:10:57 +00:00
Strahinja Petrovic
a16fdea51a [PowerPC] fix register alignment for long double type
This patch fixes register alignment for long double type in
soft float mode. Before this patch alignment was 8 and this
patch changes it to 4.
Differential Revision: http://reviews.llvm.org/D18034



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268909 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-09 12:27:39 +00:00
Chris Dewhurst
e06fb6bce7 [Sparc][LEON] Add UMAC and SMAC instruction support for Sparc LEON subtargets
This change adds SMAC (signed multiply-accumulate) and UMAC (unsigned multiply-accumulate) for LEON subtargets of the Sparc processor.

The new files LeonFeatures.td and leon-instructions.ll will both be expanded in future, so I want to leave them separate as small files for this review, to be expanded in future check-ins.

Note: The functions are provided only for inline-assembly provision. No DAG selection is provided.

Differential Revision: http://reviews.llvm.org/D19911

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268908 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-09 11:55:15 +00:00
Silviu Baranga
784cb3fef6 [AArch64] Implement lowering of the X constraint on AArch64
Summary:
This implements the lowering of the X constraint on
AArch64.

The default behaviour of the X constraint lowering is to
restrict it to "f". This is a problem because the "f"
constraint is not implemented on AArch64 and would be too
restrictive anyway. Therefore, the AArch64 hook will
lower this to "w" (if the operand is a floating point or
vector) or "r" otherwise.

The implementation is similar with the one added for
ARM (r267411).

This is the AArch64 side of the fix for http://llvm.org/PR26493

Reviewers: rengolin

Subscribers: aemerson, rengolin, llvm-commits, t.p.northover

Differential Revision: http://reviews.llvm.org/D19967

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268907 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-09 11:10:44 +00:00
Benjamin Kramer
bc38c49428 Revert "[Mips] Fix use after free."
Fixes use after free but breaks tests.

This reverts commit r268901.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268902 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-09 10:31:17 +00:00
Benjamin Kramer
04c6ebbe71 [Mips] Fix use after free.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268901 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-09 10:21:56 +00:00
Daniel Sanders
0b6e0490cf [mips][ias] R_MIPS_(GOT|HI|LO|PC)16 and R_MIPS_GPREL32 do not need symbols.
Summary:
In theory, care must be taken to ensure that pairs of R_MIPS_(GOT|HI|LO)16
make the same decision on both relocs in the reloc pair but in practice
this isn't as hard as it sounds and only limits the complexity of the
predicate used. We handle all three with the same code to ensure their
decisions always agree with each other.

Reviewers: sdardis

Subscribers: rafael, dsanders, sdardis, llvm-commits

Differential Revision: http://reviews.llvm.org/D19016


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268900 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-09 10:21:14 +00:00
Zlatko Buljan
dc02050702 [mips][microMIPS] Implement LWP and SWP instructions
Differential Revision: http://reviews.llvm.org/D10640


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268896 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-09 08:07:28 +00:00
Craig Topper
3c29a695f2 [X86] Strengthen some type contraints for floating point round and extend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268892 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-09 05:34:14 +00:00
Craig Topper
63eccc2eca [AVX512] Fix up types for arguments of int_x86_avx512_mask_cvtsd2ss_round and int_x86_avx512_mask_cvtss2sd_round. Only the argument being converted should be a different type. The other 2 argument should have the same type as the result.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268891 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-09 05:34:12 +00:00
Craig Topper
84a0ca551e [AVX512] Add non-temporal store patterns for v16i32/v32i16/v64i8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268889 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-08 23:43:17 +00:00
Craig Topper
f453dfba6f [AVX512] Add missing patterns for non-temporal stores of 128/256-bit vXi8/vXi16/vXi32 when VLX is enabled. The equivalent AVX1/2 patterns are disabled by VLX.
This caused regular stores to be emitted instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268886 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-08 23:08:45 +00:00
Craig Topper
5cb772fb8a [AVX512] Change predicates on some vXi16/vXi8 AVX store patterns so they stay enabled unless VLX and BWI instructions are supported."
Without this we could fail instruction selection if VLX was enabled, but BWI wasn't.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268885 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-08 23:08:40 +00:00
Craig Topper
dba67a4fdb [AVX512] Add VLX 128/256-bit SET0 operations that encode to 128/256-bit EVEX encoded VPXORD so all 32 registers can be used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268884 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-08 21:33:53 +00:00
Craig Topper
ba458cf29f [X86] Remove extra patterns that check for BUILD_VECTOR of all 0s. These are always canonicalized to v4i32/v8i32/v16i32 except for in SSE1 only when only v4f32 is supported.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268880 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-08 20:10:20 +00:00
David Majnemer
aa09aeb5c0 [X86] Promote several single precision FP libcalls on Windows
A number of libcalls don't exist in any particular lib but are, instead,
defined in math.h as inline functions (even in C mode!).  Don't rely on
their existence when lowering @llvm.{cos,sin,floor,..}.f32, promote them
instead.

N.B. We had logic to handle FREM but were missing out on a number of
others.  This change generalizes the FREM handling.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268875 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-08 08:15:50 +00:00
Craig Topper
82b3d2dd64 [X86] Lower 256-bit vector all-zero constants to v8i32 even with AVX1 only. Either way a 256-bit VXORPS will be used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268873 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-08 07:10:54 +00:00
Craig Topper
7e89a31db3 [X86] Add patterns for 256-bit non-temporal stores when only AVX1 is supported. While there, add a predicate to the SSE2 patterns to avoid an ordering dependency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268872 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-08 07:10:50 +00:00
Craig Topper
16942ada10 [X86] No need to avoid selecting AVX_SET0 for 256-bit integer types when only AVX1 is supported. AVX_SET0 just expands to 256-bit VXORPS which is legal in AVX1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268871 91177308-0d34-0410-b5e6-96231b3b80d8
2016-05-08 07:10:47 +00:00