Commit Graph

106371 Commits

Author SHA1 Message Date
James Molloy
ea029d5b15 Allow only disassembling of M-class MSR masks that the assembler knows how to assemble back.
Note: The current code in DecodeMSRMask() rejects the unpredictable A/R MSR mask '0000' with Fail. The code in the patch follows this style and rejects unpredictable M-class MSR masks also with Fail (instead of SoftFail). If SoftFail is preferred in this case then additional changes to ARMInstPrinter (to print non-symbolic masks) and ARMAsmParser (to parse non-symbolic masks) will be needed.

Patch by Petr Pavlu!



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214505 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-01 12:42:11 +00:00
Aaron Ballman
93b7c0b8fe Improve some const-correctness to remove a -Wcast-qual warning. No functional changes intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214503 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-01 12:34:58 +00:00
Tilmann Scheller
3b3fa38731 [ARM] Make the assembler reject unpredictable pre/post-indexed ARM LDRB/LDRSB instructions.
The ARM ARM prohibits LDRB/LDRSB instructions with writeback into the destination register. With this commit this constraint is now enforced and we stop assembling LDRH/LDRSH instructions with unpredictable behavior.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214500 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-01 12:08:04 +00:00
Tilmann Scheller
9bd0d2a6a0 [ARM] Make the assembler reject unpredictable pre/post-indexed ARM LDRH/LDRSH instructions.
The ARM ARM prohibits LDRH/LDRSH instructions with writeback into the source register. With this commit this constraint is now enforced and we stop assembling LDRH/LDRSH instructions with unpredictable behavior.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214499 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-01 11:33:47 +00:00
Tilmann Scheller
70c9be77f7 [ARM] Make the assembler reject unpredictable pre/post-indexed ARM LDR instructions.
The ARM ARM prohibits LDR instructions with writeback into the destination register. With this commit this constraint is now enforced and we stop assembling LDR instructions with unpredictable behavior.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214498 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-01 11:08:51 +00:00
Erik Eckstein
5e2214cca6 SLPVectorizer: fix build problem in Release configuration
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214496 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-01 09:47:38 +00:00
Erik Eckstein
956268f9dc SLPVectorizer: improved scheduling algorithm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214494 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-01 09:20:42 +00:00
Daniel Sanders
0a15e20ba2 [mips][PR19612] Fix va_arg for big-endian mode.
Summary:
Big-endian mode was not correctly adjusting the offset for types smaller
than an ABI slot.

Fixes PR19612

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: sstankovic, llvm-commits

Differential Revision: http://reviews.llvm.org/D4556

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214493 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-01 09:17:39 +00:00
Erik Eckstein
12f7582cf0 SLP Vectorizer: added statistics counter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214487 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-01 08:14:28 +00:00
Erik Eckstein
e47fce60e4 SLP Vectorizer: improve canonicalize tree operands of commutitive binary operands.
This reverts r214338 (except the test file) and replaces it with a more general algorithm.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214485 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-01 08:05:55 +00:00
Sylvestre Ledru
2fd13bbae0 Revert of 214418:
"Create a default symver on Linux like ELF OSes."

Fails the build under Debian with ld.gold:
/usr/bin/ld.gold: --default-symver: unknown option




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214482 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-01 06:16:03 +00:00
Hal Finkel
d2a90101cd [PowerPC] Generate unaligned vector loads using intrinsics instead of regular loads
Altivec vector loads on PowerPC have an interesting property: They always load
from an aligned address (by rounding down the address actually provided if
necessary). In order to generate an actual unaligned load, you can generate two
load instructions, one with the original address, one offset by one vector
length, and use a special permutation to extract the bytes desired.

When this was originally implemented, I generated these two loads using regular
ISD::LOAD nodes, now marked as aligned. Unfortunately, there is a problem with
this:

The alignment of a load does not contribute to its identity, and SDNodes
are uniqued. So, imagine that we have some unaligned load, L1, that is not
aligned. The routine will create two loads, L1(aligned) and (L1+16)(aligned).
Further imagine that there had already existed a load (L1+16)(unaligned) with
the same chain operand as the load L1. When (L1+16)(aligned) is created as part
of the lowering of L1, this load *is* also the (L1+16)(unaligned) node, just
now marked as aligned (because the new alignment overwrites the old). But the
original users of (L1+16)(unaligned) now get the data intended for the
permutation yielding the data for L1, and (L1+16)(unaligned) no longer exists
to get its own permutation-based expansion. This was PR19991.

A second potential problem has to do with the MMOs on these loads, which can be
used by AA during instruction scheduling to break chain-based dependencies. If
the new "aligned" loads get the MMO from the original unaligned load, this does
not represent the fact that it will load data from below the original address.
Normally, this would not matter, but this load might be combined with another
load pair for a previous vector, and then the dependency on the otherwise-
ignored lower bytes can matter.

To fix both problems, instead of generating the necessary loads using regular
ISD::LOAD instructions, ppc_altivec_lvx intrinsics are used instead. These are
provided with MMOs with a conservative address range.

Unfortunately, I no longer have a failing test case (since PR19991 was
reported, other changes in CodeGen have forced this bug back into hiding it
again). Nevertheless, this should fix the underlying problem.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214481 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-01 05:20:41 +00:00
Suyog Sarda
1952b5a4da This patch implements transform for pattern "(A & ~B) ^ (~A) -> ~(A & B)".
Differential Revision: http://reviews.llvm.org/D4653



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214479 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-01 05:07:20 +00:00
Suyog Sarda
78061f4db4 This patch implements transform for pattern "(A | B) & ((~A) ^ B) -> (A & B)".
Differential Revision: http://reviews.llvm.org/D4628



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214478 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-01 04:59:26 +00:00
Suyog Sarda
d05b6c6f2c This patch implements transform for pattern "( A & (~B)) | (A ^ B) -> (A ^ B)"
Differential Revision: http://reviews.llvm.org/D4652



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214477 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-01 04:50:31 +00:00
Suyog Sarda
87569413b0 This patch implements transform for pattern "(A & B) | ((~A) ^ B) -> (~A ^ B)".
Patch Credit to Ankit Jain !

Differential Revision: http://reviews.llvm.org/D4655



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214476 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-01 04:41:43 +00:00
Tom Stellard
de55992d54 R600/SI: Fix build warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214475 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-01 02:05:57 +00:00
Juergen Ributzka
74ac16386b [FastISel][AArch64] Fix the immediate versions of the {s|u}{add|sub}.with.overflow intrinsics.
ADDS and SUBS cannot encode negative immediates or immediates larger than 12bit.
This fix checks if the immediate version can be used under this constraints and
if we can convert ADDS to SUBS or vice versa to support negative immediates.

Also update the test cases to test the immediate versions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214470 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-01 01:25:55 +00:00
Hal Finkel
bcaf5e176a [PowerPC] Recognize consecutive memory accesses from intrinsics
When generating unaligned vector loads, we need to search for other loads or
stores nearby offset by one vector width. If we find one, then we know that we
can safely generate another aligned load at that address. Otherwise, we must
generate the next load using an offset of the vector width minus one byte (so
we don't read off the end of the allocation if the base unaligned address
happened to be aligned at runtime). We had previously done this using only
other vector loads and stores, but did not consider the PowerPC-specific vector
load/store intrinsics. Now we'll also consider vector intrinsics. By itself,
this change is a feature enhancement, but is a necessary step toward fixing the
underlying problem behind PR19991.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214469 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-01 01:02:01 +00:00
Reid Kleckner
21e23ab6f9 MS inline asm: Fix null SMLoc when 'ptr' is missing after dword & co
This improves the diagnostics from the regular assembler, but more
importantly it fixes an assertion when parsing inline assembly.  Test
landing in Clang.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214468 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-01 00:59:22 +00:00
Tom Stellard
17c8fefc9f R600/SI: Do abs/neg folding with ComplexPatterns
Abs/neg folding has moved out of foldOperands and into the instruction
selection phase using complex patterns.  As a consequence of this
change, we now prefer to select the 64-bit encoding for most
instructions and the modifier operands have been dropped from
integer VOP3 instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214467 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-01 00:32:39 +00:00
Tom Stellard
f3b62dfcb2 TableGen: Allow AddedComplexity values to be negative
This is useful for cases when stand-alone patterns are preferred to the
patterns included in the instruction definitions.  Instead of requiring
that stand-alone patterns set a larger AddedComplexity value, which
can be confusing to new developers, the allows us to reduce the
complexity of the included patterns to achieve the same result.

There will be test cases for this added to the R600 backend in a
future commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214466 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-01 00:32:36 +00:00
Tom Stellard
5494792536 R600/SI: Simplify and fix handling of VOP2 in SIInstrInfo::legalizeOperands
We were incorrectly assuming that all VOP2 instructions can read SGPRs
in Src0, but this is not true for instructions that read carry-in from
VCC.

The old logic has been replaced with new logic which checks the defined
register classes of the VOP2 instruction to determine whether or not to
legalize the operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214465 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-01 00:32:35 +00:00
Tom Stellard
635fb9fb59 R600/SI: Fold immediates when shrinking instructions
This will prevent us from using extra MOV instructions once we prefer
selecting 64-bit instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214464 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-01 00:32:33 +00:00
Tom Stellard
e5fc4208eb R600/SI: Fix incorrect commute operation in shrink instructions pass
We were commuting the instruction by still shrinking it using the
original opcode.

NOTE: This is a candidate for the 3.5 branch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214463 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-01 00:32:28 +00:00
Kevin Enderby
42deb12738 Add support for the X86 secure guard extensions instructions in assembler (SGX).
This allows assembling the two new instructions, encls and enclu for the
SKX processor model.

Note the diffs are a bigger than what might think, but to fit the new
MRM_CF and MRM_D7 in things in the right places things had to be
renumbered and shuffled down causing a bit more diffs.

rdar://16228228


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214460 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-31 23:57:38 +00:00
Reid Kleckner
0b3444cca9 X86 MC: Don't crash on empty memory operand parens
Instead, create an absolute memory operand.

Fixes PR20504.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214457 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-31 23:26:35 +00:00
Reid Kleckner
7895ae3135 X86 MC: Reject invalid segment registers before a memory operand colon
Previously we would execute unreachable during object emission.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214456 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-31 23:03:22 +00:00
Louis Gerbarg
e120a76944 White space fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214455 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-31 22:57:46 +00:00
Hal Finkel
af85a0953c Make classof in MemSDNode consistent with MemIntrinsicSDNode
If INTRINSIC_W_CHAIN and INTRINSIC_VOID are MemIntrinsicSDNodes, and a
MemIntrinsicSDNode is a MemSDNode, then INTRINSIC_W_CHAIN and INTRINSIC_VOID
must be MemSDNodes too.

Noticed by inspection.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214452 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-31 22:31:33 +00:00
Jan Vesely
22c99ee827 R600: Modernize work item intrinsics test
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Matt Arsenault <Matthew.Arsenault@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214451 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-31 22:11:03 +00:00
Louis Gerbarg
7d54c5b0f2 Make sure no loads resulting from load->switch DAGCombine are marked invariant
Currently when DAGCombine converts loads feeding a switch into a switch of
addresses feeding a load the new load inherits the isInvariant flag of the left
side. This is incorrect since invariant loads can be reordered in cases where it
is illegal to reoarder normal loads.

This patch adds an isInvariant parameter to getExtLoad() and updates all call
sites to pass in the data if they have it or false if they don't. It also
changes the DAGCombine to use that data to make the right decision when
creating the new load.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214449 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-31 21:45:05 +00:00
Tyler Nowicki
f7be7f15c1 Improve the remark generated for -Rpass-missed.
The current remark is ambiguous and makes it sounds like explicitly specifying vectorization will allow the loop to be vectorized. This is not the case. The improved remark directs the user to -Rpass-analysis=loop-vectorize to determine the cause of the pass-miss.

Reviewed by Arnold Schwaighofer`


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214445 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-31 21:22:22 +00:00
Eric Christopher
db50d8bdaf Revert "Remove MCObjectDisassembler.cpp as it is untested and unused." as it is apparently used, but the build didn't return errors weirdly.
This reverts commits 214437 and 214438.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214444 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-31 21:18:38 +00:00
Tyler Nowicki
88212074a8 Improve the remark generated when a variable that is used outside the loop is not a reduction or induction variable.
Reviewed by Arnold Schwaighofer


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214440 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-31 21:02:40 +00:00
Rafael Espindola
03c8d18ced Replaces a few pointers with references in llvm-nm.cpp.
This opens the way for a few std::uinque_ptr cleanups.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214439 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-31 21:00:10 +00:00
Aaron Ballman
c57853e192 Fixing CMake problems with MCObjectDisassembler.cpp not existing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214438 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-31 20:48:54 +00:00
Eric Christopher
e8a696fa79 Remove MCObjectDisassembler.cpp as it is untested and unused.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214437 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-31 20:44:46 +00:00
Hans Wennborg
36daac3759 msbuild integration: remove duplicated lines and BOM from 2014 integration (PR20341)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214435 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-31 20:33:22 +00:00
Rafael Espindola
fc272c3b9e DWOHolder takes ownership of the argument constructor, use std::unique_ptr.
Thanks to David Blaikie for noticing it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214434 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-31 20:26:42 +00:00
Rafael Espindola
81becb73ab Use a reference instead of a pointer.
This makes using a std::unique_ptr in the caller more convenient.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214433 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-31 20:19:36 +00:00
Eric Fiselier
156ce6cc13 Add documentation for lit's --show-unsupported flag
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214431 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-31 20:11:13 +00:00
Bill Schmidt
8d6cf4ddd3 Clarify in PowerPC release notes that 32-bit PIC support is incomplete.
As requested, changing this wording slightly.

Thanks,
Bill

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214430 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-31 20:04:51 +00:00
Will Schmidt
723bdb5e3f Disable IsSub subregister assert. pr18663.
This is a follow-up to the activity in the bug at
http://llvm.org/bugs/show_bug.cgi?id=18663 .  The underlying issue has
to do with how the KILL pseudo-instruction is handled.  I defer to
Hal/Jakob/Uli for additional details and background.

This will disable the (bad?) assert, add an associated fixme comment,
and add a pair of tests.

The code change and the pr18663-2.ll test are copied from the referenced
bug.  That test does not immediately fail in my environment, but I have
added the pr18663.ll test which does.

(Comment from Hal)
to provide everyone else with some context, this assert was not bad when
it was written. At that time, we only generated KILL pseudo instructions
around subregister copies. This logic, unfortunately, had its own problems.
In r199797, the relevant logic in MachineCopyPropagation was replaced to
generate KILLs for other kinds of copies too. This change in semantics broke
this now-problematic assumption in AggressiveAntiDepBreaker. The
AggressiveAntiDepBreaker really needs a proper cleanup to deal with the
change, but removing the assert (which just allows the function to return
false) is a safe conservative behavior, and should do for the time being.






git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214429 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-31 19:50:53 +00:00
Rafael Espindola
72c5355bbe Remove unused argument.
Thanks to Justin Bogner for noticing it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214426 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-31 19:32:04 +00:00
Rafael Espindola
1023307a7d Move MCObjectSymbolizer.h to MC/MCAnalysis.
The cpp file is already in lib/MC/MCAnalysis.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214424 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-31 19:29:23 +00:00
Hal Finkel
50c05c91f9 Fix ScalarEvolutionExpander when creating a PHI in a block with duplicate predecessors
It seems that when I fixed this, almost exactly a year ago, I did not quite do
it correctly. When we have duplicate block predecessors, we can indeed not have
different incoming values for the same block, but we *must* have duplicate
entries. So, instead of skipping the duplicates, we explicitly add the
duplicate incoming values.

Fixes PR20442.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214423 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-31 19:13:38 +00:00
Duncan P. N. Exon Smith
94f7c7aeaa verify-uselistorder: Change the default -num-shuffles=5
Change the default for `-num-shuffles` to 5 and better document the
algorithm in the header docs of `verify-uselistorder`.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214419 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-31 18:46:24 +00:00
Eric Christopher
26d83150b4 Create a default symver on Linux like ELF OSes.
Patch by Adam Jackson.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214418 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-31 18:43:43 +00:00
Duncan P. N. Exon Smith
9d65d3717c UseListOrder: Handle self-users
Correctly sort self-users (such as PHI nodes).  I added a targeted test
in `test/Bitcode/use-list-order.ll` and the final missing RUN line to
tests in `test/Assembly`.

This is part of PR5680.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214417 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-31 18:33:12 +00:00