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106 Commits

Author SHA1 Message Date
Vincent Lejeune
f3d6e32c09 R600: Add a pass that merge Vector Register 
Previously commited @183279 but tests were failing, reverted @183286
It was broken because @183336 was missing, now it's there.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183343 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-05 21:38:04 +00:00
Vincent Lejeune
512119770e R600: Schedule copy from phys register at beginning of block 
It allows regalloc pass to remove them by trivially assigning associated reg

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183336 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-05 20:27:35 +00:00
Tom Stellard
ad7ecc65b1 R600: Make sure to schedule AR register uses and defs in the same clause 
Reviewed-by: vljn at ovi.com

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183294 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-05 03:43:06 +00:00
Rafael Espindola
6afb65c2b7 Revert "R600: Add a pass that merge Vector Register" 
This reverts commit r183279. CodeGen/R600/texture-input-merge.ll was failing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183286 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-05 01:48:30 +00:00
Vincent Lejeune
bbbdba891b R600: Add a pass that merge Vector Register 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183279 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-04 23:17:26 +00:00
Vincent Lejeune
e67a4afb5d R600: Const/Neg/Abs can be folded to dot4 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183278 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-04 23:17:15 +00:00
Vincent Lejeune
98017a015b R600: Swizzle texture/export instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183229 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-04 15:04:53 +00:00
Vincent Lejeune
9328438329 R600: Add a test for r183108 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183228 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-04 15:03:35 +00:00
Tom Stellard
e5fcc0dee4 R600/SI: Add support for work item and work group intrinsics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183138 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-03 17:40:18 +00:00
Tom Stellard
e7397ee81a R600/SI: Add a calling convention for compute shaders 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183137 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-03 17:40:11 +00:00
Tom Stellard
e86f9d70ca R600/SI: Custom lower i64 sign_extend 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183136 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-03 17:40:03 +00:00
Tom Stellard
132183510f R600/SI: Add support for global loads 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183131 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-03 17:39:43 +00:00
Vincent Lejeune
96fe0be43b R600: use capital letter for PV channel 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183107 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-03 15:44:35 +00:00
Tom Stellard
d078070f6a R600: Fix R600ControlFlowFinalizer not considering VTX_READ 128 bit dst reg 
Patch by: Vincent Lejeune

https://bugs.freedesktop.org/show_bug.cgi?id=64877

NOTE: This is a candidate for the 3.3 branch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182600 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-23 18:26:42 +00:00
Tom Stellard
4f8d90df45 R600: Fix rotr.ll on non-asserts builds 
The -debug-only option is only available on asserts builds.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182291 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-20 15:28:48 +00:00
Tom Stellard
0bbfc9313c R600/SI: Add pattern for rotr 
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182286 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-20 15:02:24 +00:00
Tom Stellard
ba534c2143 R600: Swap the legality of rotl and rotr 
The hardware supports rotr and not rotl.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182285 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-20 15:02:19 +00:00
Tom Stellard
a9d5d0b346 R600/SI: Add patterns for 64-bit shift operations 
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182284 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-20 15:02:12 +00:00
Vincent Lejeune
df98ad3959 R600: Lower int_load_input to copyFromReg instead of Register node 
It solves a bug uncovered by dot4 patch where the register class of
int_load_input use was ignored.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182130 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-17 16:51:06 +00:00
Vincent Lejeune
76fc2d077f R600: Use bottom up scheduling algorithm 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182129 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-17 16:50:56 +00:00
Vincent Lejeune
21ca0b3ea4 R600: Use depth first scheduling algorithm 
It should increase PV substitution opportunities and lower gpr
usage (pending computations path are "flushed" sooner)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182128 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-17 16:50:44 +00:00
Vincent Lejeune
4ed9917147 R600: Relax some vector constraints on Dot4. 
Dot4 now uses 8 scalar operands instead of 2 vectors one which allows register
coalescer to remove some unneeded COPY.
This patch also defines some structures/functions that can be used to handle
every vector instructions (CUBE, Cayman special instructions...) in a similar
fashion.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182126 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-17 16:50:32 +00:00
Vincent Lejeune
d3293b49f9 R600: Improve texture handling 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182125 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-17 16:50:20 +00:00
Vincent Lejeune
4109bd8829 R600: Rename 128 bit registers. 
Almost all instructions that takes a 128 bits reg as input (fetch, export...)
have the abilities to swizzle their argument and output. Instead of printing
default swizzle for each 128 bits reg, rename T*.XYZW to T* and let instructions
print potentially optimized swizzles themselves.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182124 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-17 16:50:09 +00:00
Tom Stellard
0976e3c6d9 R600: Fix encoding for R600 family GPUs 
Reviewed-by: Vincent Lejeune <vljn@ovi.com>

https://bugs.freedesktop.org/show_bug.cgi?id=64193
https://bugs.freedesktop.org/show_bug.cgi?id=64257
https://bugs.freedesktop.org/show_bug.cgi?id=64320

NOTE: This is a candidate for the 3.3 branch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182113 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-17 15:23:21 +00:00
Michel Danzer
5096dc74ae R600/SI: Add lit test coverage for the remaining patterns added recently 
Reviewed-by: Christian König <christian.koenig@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181775 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-14 09:53:30 +00:00
Tom Stellard
58e87a68a8 R600: Remove AMDILPeeopholeOptimizer and replace optimizations with tablegen patterns 
The BFE optimization was the only one we were actually using, and it was
emitting an intrinsic that we don't support.

https://bugs.freedesktop.org/show_bug.cgi?id=64201

Reviewed-by: Christian König <christian.koenig@amd.com>

NOTE: This is a candidate for the 3.3 branch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181580 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-10 02:09:45 +00:00
Tom Stellard
dde6836456 R600: Expand SUB for v2i32/v4i32 
Patch by: Aaron Watry

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Aaron Watry <awatry@gmail.com>

NOTE: This is a candidate for the 3.3 branch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181579 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-10 02:09:39 +00:00
Tom Stellard
6c40d40d70 R600: Expand MUL for v4i32/v2i32 
Fixes piglit test for OpenCL builtin mul24, and allows mad24 to run.

Patch by: Aaron Watry

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Aaron Watry <awatry@gmail.com>

NOTE: This is a candidate for the 3.3 branch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181578 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-10 02:09:34 +00:00
Tom Stellard
4fca5c1440 R600: Expand SRA for v4i32/v2i32 
v2: Add v4i32 test

Patch by: Aaron Watry

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Aaron Watry <awatry@gmail.com>

NOTE: This is a candidate for the 3.3 branch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181577 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-10 02:09:29 +00:00
Tom Stellard
bdd9b1e89f R600: Expand vselect for v4i32 and v2i32 
v2: Add vselect v4i32 test

Patch by: Aaron Watry

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Aaron Watry <awatry@gmail.com>

NOTE: This is a candidate for the 3.3 branch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181576 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-10 02:09:24 +00:00
Michel Danzer
97fd27a436 R600/SI: Add lit tests for llvm.SI.imageload and llvm.SI.resinfo intrinsics 
Adapted from the llvm.SI.sample test.

Reviewed-by: Christian König <christian.koenig@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181425 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-08 13:07:29 +00:00
Tom Stellard
f07b5373d7 R600: Emit config values in register / value pairs 
Reviewed-by: Vincent Lejeune <vljn@ovi.com>
Tested-By: Aaron Watry <awatry@gmail.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181228 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-06 17:50:51 +00:00
Tom Stellard
4f3d8a6440 R600: Stop emitting the instruction type byte before each instruction 
Reviewed-by: Vincent Lejeune <vljn@ovi.com>
Tested-By: Aaron Watry <awatry@gmail.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181225 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-06 17:50:44 +00:00
Tom Stellard
58bf662c06 R600: Emit ISA for CALL_FS_* instructions 
Reviewed-by: Vincent Lejeune <vljn@ovi.com>
Tested-By: Aaron Watry <awatry@gmail.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181223 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-06 17:50:26 +00:00
Tom Stellard
19301d5d12 R600: Expand vector or, shl, srl, and xor nodes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181035 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-03 17:21:31 +00:00
Tom Stellard
83f0a5a5e8 R600: Add pattern for SHA-256 Ma function 
This can be optimized using the BFI_INT instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181033 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-03 17:21:20 +00:00
Vincent Lejeune
5ed88013e8 R600: Signed literals are 64bits wide 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180960 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-02 21:53:03 +00:00
Vincent Lejeune
152ebee8f3 R600: If previous bundle is dot4, PV valid chan is always X 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180959 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-02 21:52:55 +00:00
Vincent Lejeune
e117646f1f R600: Add a test to check that use_kill is emitted 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180958 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-02 21:52:46 +00:00
Vincent Lejeune
92f24d403f R600: Prettier asmPrint of Alu 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180956 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-02 21:52:30 +00:00
Manman Ren
2dc50d3067 TBAA: remove !tbaa from testing cases if not used. 
This will make it easier to turn on struct-path aware TBAA since the metadata
format will change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180796 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-30 17:52:57 +00:00
Vincent Lejeune
1872730c5a R600: fix loop-address.ll test 
Texture cache is now used when shader type is not specified

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180785 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-30 12:47:56 +00:00
Vincent Lejeune
2c836f84db R600: use native for alu 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180761 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-30 00:14:38 +00:00
Vincent Lejeune
631591e6f3 R600: Add FetchInst bit to instruction defs to denote vertex/tex instructions 
v2[Vincent Lejeune]: Split FetchInst into usesTextureCache/usesVertexCache

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180755 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-30 00:13:39 +00:00
Tom Stellard
d8b2da1136 R600: Use correct CF_END instruction on Northern Island GPUs 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180735 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-29 22:23:58 +00:00
Tom Stellard
015f586bc9 R600: Fix encoding of CF_END_{EG, R600} instructions 
The EOP bit was not being encoded.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180734 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-29 22:23:54 +00:00
Tom Stellard
99d8179a9b R600: Initialize AMDGPUMachineFunction::ShaderType to ShaderType::COMPUTE 
We need to intialize this to something and since clang does not set
the shader type attribute and clang is used only for compute shaders,
initializing it to COMPUTE seems like the best choice.

Reviewed-by: Christian König <christian.koenig@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180620 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-26 18:32:24 +00:00
Tom Stellard
87cba4a4c1 R600: Use SHT_PROGBITS for the .AMDGPU.config section 
The libelf implementation that is distributed here:
http://www.mr511.de/software/english.html
will not parse sections that are marked SHT_NULL.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180230 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-24 23:56:14 +00:00
Vincent Lejeune
2a74639bc7 R600: Use .AMDGPU.config section to emit stacksize 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180124 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-23 17:34:12 +00:00