llvm/test/CodeGen/AArch64/movw-shift-encoding.ll
Evandro Menezes f5697dce74 [AArch64] Generate literals by the little end
ARM seems to prefer that long literals be formed from their little end in
order to promote the fusion of the instrs pairs MOV/MOVK and MOVK/MOVK on
Cortex A57 and others (v.  "Cortex A57 Software Optimisation Guide", section
4.14).

Differential revision: https://reviews.llvm.org/D28697

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292422 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-18 18:57:08 +00:00

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LLVM

; RUN: llc -mtriple=aarch64-linux-gnu < %s -show-mc-encoding -code-model=large | FileCheck %s
@var = global i32 0
; CodeGen should ensure that the correct shift bits are set, because the linker
; isn't going to!
define i32* @get_var() {
ret i32* @var
; CHECK: movz x0, #:abs_g0_nc:var // encoding: [0bAAA00000,A,0b100AAAAA,0xd2]
; CHECK: movk x0, #:abs_g1_nc:var // encoding: [0bAAA00000,A,0b101AAAAA,0xf2]
; CHECK: movk x0, #:abs_g2_nc:var // encoding: [0bAAA00000,A,0b110AAAAA,0xf2]
; CHECK: movk x0, #:abs_g3:var // encoding: [0bAAA00000,A,0b111AAAAA,0xf2]
}