Update to bsnes v034 release.

For this release: SPC7110 emulation speed has been greatly optimized, massive improvements to HDMA timing have been implemented, Multitap support was added, and the user interface was polished a bit more. Changelog: - SPC7110 decompression code updated to latest version by neviksti and converted to a state machine; SPC7110 overhead is now identical to S-DD1 overhead (eg ~5% speed hit over standard games) - Fixed a major bug in SPC7110 data port emulation that was crashing Super Power League 4 [Jonas Quinn] - HDMA trigger point corrected to H=1104, bus sync timing corrected - All illegal DMA A-bus accesses should now be properly blocked - DMA state machine rewritten, greatly simplified - Major corrections to HDMA run timing; fixes flickering bugs in Mecarobot Golf and Super Mario Kart - Emulator now defaults to 2/1/3 SNES (CPU/PPU1/PPU2 revision numbers) - Multitap emulation added, can be attached to either or both controller ports; user interface updated to reflect this - Status messages (cartridge loaded / unloaded, UPS patch applied, etc) now appear in status bar - Added advanced configuration option, "input.analog_axis_resistance", to control gamepad analog stick sensitivity Also, the SPC7110 emulator download link below was removed: if you are looking for this, please download the bsnes v034 source code, which has the most up-to-date version in the src/chip/spc7110 folder.
Update to bsnes v033r09? release.
2026-11-08 01:08:24 -10:00 · 2008-08-11 11:33:54 +00:00 · 2008-08-08 14:22:00 +00:00 · 2008-08-07 13:39:00 +00:00 · 2008-08-05 11:58:00 +00:00 · 2008-08-04 06:35:00 +00:00
644 changed files with 36200 additions and 36058 deletions
@@ -0,0 +1,84 @@
+bsnes (TM) Reference License
+Copyright (C) 2004 - 2008 byuu
+All rights reserved
+
+1. Definitions
+
+The terms "reproduce", "reproduction", "distribute" and "distribution" have the
+same meaning here as under U.S. copyright law.
+
+"The software" means this software package as a whole, including, but not
+limited to, this license, binaries, source code, documentation, and data.
+
+"You" means the licensee of the software.
+
+"The licensor" means the copyright holder of the software, byuu.
+
+2. Grant of Rights
+
+Subject to the terms of this license, the licensor grants you a
+non-transferable, non-exclusive, worldwide, royalty-free copyright license to
+reproduce the software for non-commercial use only, provided the software
+remains unmodified, and there is no charge for the software itself, its' use,
+nor for the medium upon which the software is distributed. The reproduction of
+modified or derivative works of the software is strictly prohibited, except when
+transmitted solely to the licensor.
+
+3. Limitations
+
+This license does not grant you any rights to use the licensor's name, logo or
+trademarks.
+
+The software is provided "as is", and any express or implied warranties,
+including, but not limited to, the implied warranties of merchantability and
+fitness for a particular purpose are disclaimed. In no event shall the licensor
+be liable for any direct, indirect, incidental, special, exemplary, or
+consequential damages (including, but not limited to, procurement of substitute
+goods or services; loss of use, data, or profits; or business interruption)
+however caused and on any theory of liability, whether in contract, strict
+liability, or tort (including negligence or otherwise) arising in any way out of
+the use of the software, even if advised of the possibility of such damage.
+
+In the event that this license is determined to be invalid or unenforceable, the
+Grant of Rights will become null and void, and no rights shall be granted to the
+licensee, within the scope of U.S. copyright law.
+
+4. Exemptions
+
+The software includes the work of other copyright holders, which is licensed
+under different agreements, and exempt from this license. Below is a complete
+list of all such software, and their respective copyright holders and licenses.
+Further, respective source code files are labeled with their correct licensing
+information in the header. The lack of such a header indicates said file falls
+under the bsnes license.
+
+HQ2x filter, author: MaxST, license: LGPL
+JMA decompressor, author: NSRT Team, license: GPL*
+NTSC filter, author: blargg, license: LGPL
+zlib decompressor, license: zlib license
+
+(* bsnes has received an exemption from the copyright holder to use this work.)
+
+The software also includes works which have been released to the public domain,
+which are not bound to any licensing agreements. Below is a complete list of all
+such software.
+
+libco, author: byuu
+S-DD1 decompressor, author: Andreas Naive
+SPC7110 decompressor, author: neviksti
+
+Any software listed above as exemptions may be relicensed individually from
+bsnes under their respective terms. However, no bsnes licensed portions can be
+combined with such a derivative work.
+
+The software also includes the work of other copyright holders, which is
+licensed under the terms of the bsnes license, with permission to do so from the
+respective authors. Below is a complete list of all such software.
+
+Cx4 emu, authors: anomie, Overload, zsKnight, Nach
+DSP-1 emu, authors: Overload, John Weidman, Neviksti, Andreas Naive
+DSP-2 emu, author: Overload
+DSP-3 emu, authors: John Weidman, Kris Bleakley, Lancer, z80 gaiden
+DSP-4 emu, authors: Dreamer Nom, John Weidman, Kris Bleakley, Nach, z80 gaiden
+S-DSP emu, author: blargg
+ST-010 emu, authors: John Weidman, Matthew Kendora, Overload, Feather
@@ -0,0 +1,106 @@
+bsnes
+Version: 0.034
+Author: byuu
+
+========
+General:
+========
+
+bsnes is a Super Nintendo / Super Famicom emulator that began on
+October 14th, 2004.
+
+The latest version can be downloaded from:
+http://byuu.org/
+
+Please see license.txt for important licensing information.
+
+==============
+Configuration:
+==============
+
+bsnes has two configuration files: bsnes.cfg, for program settings; and
+locale.cfg, for localization.
+
+For each file, bsnes will start by looking inside the same folder where the
+bsnes executable is located. If said file is not found, it will then check your
+user profile folder. On Windows, this is located at "%APPDATA%/.bsnes". On all
+other operating systems, this is located at "~/.bsnes". If said file is still
+not found, it will automatically be created in your user profile folder.
+
+If you wish to use bsnes in single-user mode, be sure that both files exist
+inside the same folder as the bsnes executable. If they do not, you can simply
+create new blank files and bsnes will use them in the future.
+
+If you wish to use bsnes in multi-user mode, simply delete these two files from
+the bsnes executable directory if they exist.
+
+If you wish to have multiple configuration profiles for the same user, you will
+need to make copies of the bsnes executable, and use each one in single-user
+mode.
+
+==================
+Known Limitations:
+==================
+
+S-CPU
+- Multiply / divide register delays not implemented
+- "Glitch" when reading joypad registers during auto polling not implemented
+
+S-PPU
+- Uses scanline-based renderer. This is very inaccurate, but few (if any)
+  games rely on mid-scanline writes to function correctly
+- Does not support FirstSprite+Y priority
+- OAM / CGRAM accesses during active display not supported correctly
+- RTO flags are not calculated on frames that are skipped when frameskipping
+  is enabled. This provides a major speedup, however it will cause in issues
+  in games that test these flags, eg the SNES Test Program Electronics Test.
+  Turning frameskipping off will allow RTO flag calculation on every frame
+
+Hardware Bugs
+- S-CPU.r1 HDMA crashing bug not emulated
+- S-CPU<>S-SMP communication bus conflicts not emulated
+
+=====================
+Unsupported Hardware:
+=====================
+
+SA-1
+Coprocessor used in many popular games, including:
+- Dragon Ball Z Hyper Dimension
+- Kirby Super Star
+- Kirby's Dreamland 3
+- Marvelous
+- SD Gundam G-NEXT
+- Super Mario RPG
+
+Super FX
+Coprocessor used in many popular games, including:
+- Doom
+- Star Fox
+- Star Fox 2 (unreleased beta)
+- Super Mario World 2: Yoshi's Island
+
+ST-011
+SETA DSP used by Quick-move Shogi Match with Nidan Rank-holder Morita
+
+ST-018
+SETA RISC CPU used by Quick-move Shogi Match with Nidan Rank-holder Morita 2
+
+Super Gameboy
+Cartridge passthrough used for playing Gameboy games
+
+========================
+Unsupported Controllers:
+========================
+
+Mouse
+Super Scope
+Justifier
+
+=============
+Contributors:
+=============
+
+Andreas Naive, anomie, blargg, DMV27, FitzRoy, GIGO, Jonas Quinn, kode54, krom,
+mudlord, Nach, neviksti, Overload, RedDwarf, Richard Bannister, tetsuo55, TRAC,
+zones
@@ -0,0 +1,280 @@
+include lib/nall/Makefile.string
+prefix = /usr/local
+
+################
+### compiler ###
+################
+
+ifneq ($(findstring gcc,$(compiler)),) # GCC family
+  flags = -O3 -fomit-frame-pointer -Ilib
+  c = $(compiler) $(flags)
+  cpp = $(subst cc,++,$(compiler)) $(flags)
+  obj = o
+  rule = -c $< -o $@
+  link = -s
+  mkbin = -o$1
+  mkdef = -D$1
+  mklib = -l$1
+else ifeq ($(compiler),cl) # Visual C++
+  flags = /nologo /wd4355 /wd4996 /O2 /EHsc /Ilib
+  c = cl $(flags)
+  cpp = cl $(flags)
+  obj = obj
+  rule = /c $< /Fo$@
+  link = /link
+  mkbin = /Fe$1
+  mkdef = /D$1
+  mklib = $1.lib
+else
+  unknown_compiler: help;
+endif
+
+##########
+### os ###
+##########
+
+ifeq ($(platform),x) # X11
+  ruby = video.glx video.xv video.sdl audio.openal audio.oss audio.alsa audio.ao input.sdl input.x
+  link += `pkg-config --libs gtk+-2.0`
+  link += $(call mklib,Xtst)
+  delete = rm -f $1
+else ifeq ($(platform),win) # Windows
+  ruby = video.direct3d video.wgl video.directdraw video.gdi audio.directsound input.directinput
+  link += $(if $(findstring mingw,$(compiler)),-mwindows)
+  link += $(call mklib,uuid)
+  link += $(call mklib,kernel32)
+  link += $(call mklib,user32)
+  link += $(call mklib,gdi32)
+  link += $(call mklib,shell32)
+  link += $(call mklib,winmm)
+  link += $(call mklib,comdlg32)
+  link += $(call mklib,comctl32)
+  delete = $(if $(findstring i586-mingw-gcc,$(compiler)),rm -f $1,del $(subst /,\,$1))
+else
+  unknown_platform: help;
+endif
+
+############
+### ruby ###
+############
+
+rubyflags =
+rubyflags += $(if $(findstring .sdl,$(ruby)),`sdl-config --cflags`)
+
+link += $(if $(findstring video.direct3d,$(ruby)),$(call mklib,d3d9))
+link += $(if $(findstring video.directdraw,$(ruby)),$(call mklib,ddraw))
+link += $(if $(findstring video.glx,$(ruby)),$(call mklib,GL))
+link += $(if $(findstring video.wgl,$(ruby)),$(call mklib,opengl32))
+link += $(if $(findstring video.xv,$(ruby)),$(call mklib,Xv))
+link += $(if $(findstring audio.alsa,$(ruby)),$(call mklib,asound))
+link += $(if $(findstring audio.ao,$(ruby)),$(call mklib,ao))
+link += $(if $(findstring audio.directsound,$(ruby)),$(call mklib,dsound))
+link += $(if $(findstring audio.openal,$(ruby)),$(if $(call streq,$(platform),x),$(call mklib,openal),$(call mklib,openal32)))
+link += $(if $(findstring input.directinput,$(ruby)),$(call mklib,dinput8) $(call mklib,dxguid))
+link += $(if $(findstring input.sdl,$(ruby)),`sdl-config --libs`)
+
+####################################
+### main target and dependencies ###
+####################################
+
+objects = main libco hiro ruby libfilter string reader cart cheat \
+  memory smemory cpu scpu smp ssmp sdsp ppu bppu snes \
+  bsx srtc sdd1 spc7110 cx4 dsp1 dsp2 dsp3 dsp4 obc1 st010
+
+ifeq ($(enable_gzip),true)
+  objects += adler32 compress crc32 deflate gzio inffast inflate inftrees ioapi trees unzip zip zutil
+  flags += $(call mkdef,GZIP_SUPPORT)
+endif
+
+ifeq ($(enable_jma),true)
+  objects += jma jcrc32 lzmadec 7zlzma iiostrm inbyte lzma winout
+  flags += $(call mkdef,JMA_SUPPORT)
+endif
+
+objects := $(patsubst %,obj/%.$(obj),$(objects))
+rubydef := $(foreach c,$(subst .,_,$(call strupper,$(ruby))),$(call mkdef,$c))
+
+# Windows resource file
+ifeq ($(platform),win)
+  ifeq ($(compiler),cl)
+    objects += obj/bsnes.res
+  else ifneq ($(findstring gcc,$(compiler)),)
+    objects += obj/bsnesrc.$(obj)
+  endif
+endif
+
+################
+### implicit ###
+################
+
+compile = \
+  $(strip \
+    $(if $(filter %.c,$<), \
+      $(c) $1 $(rule), \
+      $(if $(filter %.cpp,$<), \
+        $(cpp) $1 $(rule) \
+      ) \
+    ) \
+  )
+
+%.$(obj): $<; $(call compile)
+
+all: build;
+
+############
+### main ###
+############
+
+obj/main.$(obj): ui/main.cpp ui/* ui/base/* ui/loader/* ui/settings/*
+obj/bsnes.res: ui/bsnes.rc; rc /r /foobj/bsnes.res ui/bsnes.rc
+obj/bsnesrc.$(obj): ui/bsnes.rc; windres ui/bsnes.rc obj/bsnesrc.$(obj)
+
+#################
+### libraries ###
+#################
+
+obj/ruby.$(obj): lib/ruby/ruby.cpp lib/ruby/*
+	$(call compile,$(rubydef) $(rubyflags))
+obj/hiro.$(obj): lib/hiro/hiro.cpp lib/hiro/* lib/hiro/gtk/* lib/hiro/win/*
+	$(call compile,$(if $(call streq,$(platform),x),`pkg-config --cflags gtk+-2.0`))
+obj/libco.$(obj):     lib/libco/libco.c lib/libco/*
+	$(call compile,-static)
+obj/libfilter.$(obj): lib/libfilter/libfilter.cpp lib/libfilter/*
+obj/string.$(obj):    lib/nall/string.cpp lib/nall/*
+
+#################
+### utilities ###
+#################
+
+obj/reader.$(obj): reader/reader.cpp reader/*
+obj/cart.$(obj)  : cart/cart.cpp cart/*
+obj/cheat.$(obj) : cheat/cheat.cpp cheat/*
+
+##############
+### memory ###
+##############
+
+obj/memory.$(obj) : memory/memory.cpp memory/*
+obj/smemory.$(obj): memory/smemory/smemory.cpp memory/smemory/* memory/smemory/mapper/*
+
+###########
+### cpu ###
+###########
+
+obj/cpu.$(obj) : cpu/cpu.cpp cpu/*
+obj/scpu.$(obj): cpu/scpu/scpu.cpp cpu/scpu/* cpu/scpu/core/* cpu/scpu/dma/* cpu/scpu/memory/* cpu/scpu/mmio/* cpu/scpu/timing/*
+
+###########
+### smp ###
+###########
+
+obj/smp.$(obj) : smp/smp.cpp smp/*
+obj/ssmp.$(obj): smp/ssmp/ssmp.cpp smp/ssmp/* smp/ssmp/core/* smp/ssmp/memory/* smp/ssmp/timing/*
+
+###########
+### dsp ###
+###########
+
+obj/adsp.$(obj): dsp/adsp/adsp.cpp dsp/adsp/*
+obj/bdsp.$(obj): dsp/bdsp/bdsp.cpp dsp/bdsp/*
+obj/sdsp.$(obj): dsp/sdsp/sdsp.cpp dsp/sdsp/*
+
+###########
+### ppu ###
+###########
+
+obj/ppu.$(obj) : ppu/ppu.cpp ppu/*
+obj/bppu.$(obj): ppu/bppu/bppu.cpp ppu/bppu/*
+
+############
+### snes ###
+############
+
+obj/snes.$(obj): snes/snes.cpp snes/* snes/scheduler/* snes/video/* snes/audio/* snes/input/*
+
+#####################
+### special chips ###
+#####################
+
+obj/bsx.$(obj)    : chip/bsx/bsx.cpp chip/bsx/*
+obj/srtc.$(obj)   : chip/srtc/srtc.cpp chip/srtc/*
+obj/sdd1.$(obj)   : chip/sdd1/sdd1.cpp chip/sdd1/*
+obj/spc7110.$(obj): chip/spc7110/spc7110.cpp chip/spc7110/*
+obj/cx4.$(obj)    : chip/cx4/cx4.cpp chip/cx4/*
+obj/dsp1.$(obj)   : chip/dsp1/dsp1.cpp chip/dsp1/*
+obj/dsp2.$(obj)   : chip/dsp2/dsp2.cpp chip/dsp2/*
+obj/dsp3.$(obj)   : chip/dsp3/dsp3.cpp chip/dsp3/*
+obj/dsp4.$(obj)   : chip/dsp4/dsp4.cpp chip/dsp4/*
+obj/obc1.$(obj)   : chip/obc1/obc1.cpp chip/obc1/*
+obj/st010.$(obj)  : chip/st010/st010.cpp chip/st010/*
+
+############
+### zlib ###
+############
+
+obj/adler32.$(obj) : reader/zlib/adler32.c reader/zlib/*
+obj/compress.$(obj): reader/zlib/compress.c reader/zlib/*
+obj/crc32.$(obj)   : reader/zlib/crc32.c reader/zlib/*
+obj/deflate.$(obj) : reader/zlib/deflate.c reader/zlib/*
+obj/gzio.$(obj)    : reader/zlib/gzio.c reader/zlib/*
+obj/inffast.$(obj) : reader/zlib/inffast.c reader/zlib/*
+obj/inflate.$(obj) : reader/zlib/inflate.c reader/zlib/*
+obj/inftrees.$(obj): reader/zlib/inftrees.c reader/zlib/*
+obj/ioapi.$(obj)   : reader/zlib/ioapi.c reader/zlib/*
+obj/trees.$(obj)   : reader/zlib/trees.c reader/zlib/*
+obj/unzip.$(obj)   : reader/zlib/unzip.c reader/zlib/*
+obj/zip.$(obj)     : reader/zlib/zip.c reader/zlib/*
+obj/zutil.$(obj)   : reader/zlib/zutil.c reader/zlib/*
+
+###########
+### jma ###
+###########
+
+obj/jma.$(obj)    : reader/jma/jma.cpp reader/jma/*
+obj/jcrc32.$(obj) : reader/jma/jcrc32.cpp reader/jma/*
+obj/lzmadec.$(obj): reader/jma/lzmadec.cpp reader/jma/*
+obj/7zlzma.$(obj) : reader/jma/7zlzma.cpp reader/jma/*
+obj/iiostrm.$(obj): reader/jma/iiostrm.cpp reader/jma/*
+obj/inbyte.$(obj) : reader/jma/inbyte.cpp reader/jma/*
+obj/lzma.$(obj)   : reader/jma/lzma.cpp reader/jma/*
+obj/winout.$(obj) : reader/jma/winout.cpp reader/jma/*
+
+###############
+### targets ###
+###############
+
+build: $(objects)
+	$(strip $(cpp) $(call mkbin,../bsnes) $(objects) $(link))
+
+install:
+	install -D -m 755 ../bsnes $(DESTDIR)$(prefix)/bin/bsnes
+	install -D -m 644 data/bsnes.png $(DESTDIR)$(prefix)/share/icons/bsnes.png
+
+clean:
+	-@$(call delete,obj/*.$(obj))
+	-@$(call delete,*.res)
+	-@$(call delete,*.pgd)
+	-@$(call delete,*.pgc)
+	-@$(call delete,*.ilk)
+	-@$(call delete,*.pdb)
+	-@$(call delete,*.manifest)
+
+help:
+	@echo "Usage: $(MAKE) platform=(os) compiler=(cc) [options]"
+	@echo ""
+	@echo "Supported platforms:"
+	@echo "  x   - Linux / BSD (x86, x86-64)"
+	@echo "  win - Windows (x86, x86-64)"
+	@echo ""
+	@echo "Supported compilers:"
+	@echo "  gcc              - GCC compiler"
+	@echo "  mingw32-gcc      - MinGW compiler"
+	@echo "  i586-mingw32-gcc - MinGW cross compiler"
+	@echo "  cl               - Visual C++"
+	@echo ""
+	@echo "Available options:"
+	@echo "  enable_gzip=[true|false] - Enable ZIP / GZ support (default=false)"
+	@echo "  enable_jma=[true|false]  - Enable JMA support (default=false)"
+	@echo ""
+	@echo "Example: $(MAKE) platform=x compiler=gcc enable_gzip=true"
+	@echo ""
@@ -1,71 +1,43 @@
-#define BSNES_VERSION "0.018"
-#define BSNES_TITLE   "bsnes v" BSNES_VERSION
-
-#define MEMCORE bMemBus
-#define CPUCORE sCPU
-#define SMPCORE sSMP
-#define DSPCORE bDSP
-#define PPUCORE bPPU
-
-//#define FAVOR_ACCURACY
-#define FAVOR_SPEED
-
-//game genie + pro action replay code support (~1-3% speed hit)
-#define CHEAT_SYSTEM
-
-//enable GZ, ZIP format support
-#define GZIP_SUPPORT
-
-//enable JMA support
-#define JMA_SUPPORT
-
-//snes core polymorphism
-//(allow runtime cpu/smp/dsp/ppu/bus selection, ~10% speed hit)
-//#define POLYMORPHISM
-
-#if defined(PROCESSOR_X86)
-  #define ARCH_LSB
-#elif defined(PROCESSOR_X86_64)
-  #define ARCH_LSB
-#elif defined(PROCESSOR_G5)
-  #define ARCH_MSB
-#else
-  #error "unsupported processor"
-#endif
-
-#include "lib/libbase.h"
-#include "lib/libco_x86.h"
-#include "lib/libarray.h"
-#include "lib/libvector.h"
-#include "lib/libfile.h"
-#include "lib/libups.h"
-#include "lib/libstring.h"
-#include "lib/libconfig.h"
-
-inline uint16 read16(uint8 *addr, uint pos) {
-#ifdef ARCH_LSB
-  return *((uint16*)(addr + pos));
-#else
-  return (addr[pos]) | (addr[pos + 1] << 8);
-#endif
-}
-
-//platform-specific global functions
-void alert(char *, ...);
-void dprintf(char *, ...);
-void dprintf(uint, char *, ...);
-
-namespace source {
-  enum {
-    none = 0,
-    debug,
-    cpu,
-    ppu,
-    smp,
-    dsp,
-    bus,
-  };
-};
-
-//various class interfaces
-#include "interface.h"
+#define BSNES_VERSION "0.034"
+#define BSNES_TITLE   "bsnes v" BSNES_VERSION
+
+#define BUSCORE sBus
+#define CPUCORE sCPU
+#define SMPCORE sSMP
+#define DSPCORE sDSP
+#define PPUCORE bPPU
+
+//S-DSP can be encapsulated into a state machine using #define magic
+//this avoids ~2.048m co_switch() calls per second (~5% speedup)
+#define USE_STATE_MACHINE
+
+//FAST_FRAMESKIP disables calculation of RTO during frameskip
+//frameskip offers near-zero speedup if RTO is calculated
+//accuracy is not affected by this define when frameskipping is off
+#define FAST_FRAMESKIP
+
+//game genie + pro action replay code support (~2% speed hit)
+#define CHEAT_SYSTEM
+
+#include <nall/algorithm.hpp>
+#include <nall/array.hpp>
+#include <nall/bit.hpp>
+#include <nall/config.hpp>
+#include <nall/detect.hpp>
+#include <nall/function.hpp>
+#include <nall/modulo.hpp>
+#include <nall/new.hpp>
+#include <nall/sort.hpp>
+#include <nall/stdint.hpp>
+#include <nall/string.hpp>
+#include <nall/vector.hpp>
+using namespace nall;
+
+#include <libco/libco.h>
+#include <bbase.h>
+
+//platform-specific global functions
+void alert(const char*, ...);
+void dprintf(const char*, ...);
+
+#include "interface.h"
@@ -1,418 +1,141 @@
-#include "../base.h"
-#include "database.cpp"
+#include "../base.h"
+#define CART_CPP
+
+#include <nall/crc32.hpp>
+#include <nall/ups.hpp>
+
+#include "cart_normal.cpp"
+#include "cart_bsx.cpp"
+#include "cart_bsc.cpp"
+#include "cart_st.cpp"
+
+#include "cart_file.cpp"
+#include "cart_header.cpp"
+
+namespace memory {
+  MappedRAM cartrom, cartram, cartrtc;
+  MappedRAM bscram;
+  MappedRAM stArom, stAram;
+  MappedRAM stBrom, stBram;
+};

 Cartridge cartridge;

-void Cartridge::read_dbi() {
-  info.srtc = false;
-  info.sdd1 = false;
-  info.c4   = false;
-  info.dsp1 = false;
-  info.dsp2 = false;
-  info.obc1 = false;
+Cartridge::MemoryMapper Cartridge::mapper() { return info.mapper; }
+Cartridge::Region Cartridge::region() { return info.region; }

-  info.dsp1_mapper = 0;
+bool Cartridge::loaded() { return cart.loaded; }

-  info.header_index = 0x7fc0;
-  info.mapper = PCB;
-  strcpy(info.name, dbi.name);
-  strcpy(info.pcb,  dbi.pcb);
+void Cartridge::load_begin(CartridgeType cart_type) {
+  cart.rom = cart.ram = cart.rtc = 0;
+  bs.ram   = 0;
+  stA.rom  = stA.ram  = 0;
+  stB.rom  = stB.ram  = 0;
+
+  cart.rom_size = cart.ram_size = cart.rtc_size = 0;
+  bs.ram_size   = 0;
+  stA.rom_size  = stA.ram_size  = 0;
+  stB.rom_size  = stB.ram_size  = 0;
+
+  info.type = cart_type;
+  info.patched = false;
+
+  info.bsxbase  = false;
+  info.bsxcart  = false;
+  info.bsxflash = false;
+  info.st       = false;
+
+  info.superfx    = false;
+  info.sa1        = false;
+  info.srtc       = false;
+  info.sdd1       = false;
+  info.spc7110    = false;
+  info.spc7110rtc = false;
+  info.cx4        = false;
+  info.dsp1       = false;
+  info.dsp2       = false;
+  info.dsp3       = false;
+  info.dsp4       = false;
+  info.obc1       = false;
+  info.st010      = false;
+  info.st011      = false;
+  info.st018      = false;
+
+  info.dsp1_mapper = DSP1Unmapped;
+
+  info.header_index = 0xffc0;
+  info.mapper = LoROM;
+  info.name[0] = 0;
  info.region = NTSC;
-  info.cart_mmio = false;

-  info.rom_size = dbi.rom;
-  info.ram_size = dbi.ram;
+  info.rom_size = 0;
+  info.ram_size = 0;
 }

-void Cartridge::read_header() {
-  info.srtc = false;
-  info.sdd1 = false;
-  info.c4   = false;
-  info.dsp1 = false;
-  info.dsp2 = false;
-  info.obc1 = false;
+void Cartridge::load_end() {
+  memory::cartrom.map(cart.rom, cart.rom_size);
+  memory::cartram.map(cart.ram, cart.ram_size);
+  memory::cartrtc.map(cart.rtc, cart.rtc_size);
+  memory::bscram.map(bs.ram, bs.ram_size);
+  memory::stArom.map(stA.rom, stA.rom_size);
+  memory::stAram.map(stA.ram, stA.ram_size);
+  memory::stBrom.map(stB.rom, stB.rom_size);
+  memory::stBram.map(stB.ram, stB.ram_size);

-  info.dsp1_mapper = 0;
+  memory::cartrom.write_protect(true);
+  memory::cartram.write_protect(false);
+  memory::bscram.write_protect(true);
+  memory::stArom.write_protect(true);
+  memory::stAram.write_protect(false);
+  memory::stBrom.write_protect(true);
+  memory::stBram.write_protect(false);

-  if(info.header_index == 0x7fc0 && info.rom_size >= 0x401000) {
-    info.mapper = EXLOROM;
-    strcpy(info.pcb, "UNL-EXLOROM");
-  } else if(info.header_index == 0x7fc0 && rom[info.header_index + MAPPER] == 0x32) {
-    info.mapper = EXLOROM;
-    strcpy(info.pcb, "UNL-EXLOROM");
-  } else if(info.header_index == 0x7fc0) {
-    info.mapper = LOROM;
-    strcpy(info.pcb, "UNL-LOROM");
-  } else if(info.header_index == 0xffc0) {
-    info.mapper = HIROM;
-    strcpy(info.pcb, "UNL-HIROM");
-  } else { //info.header_index == 0x40ffc0
-    info.mapper = EXHIROM;
-    strcpy(info.pcb, "UNL-EXHIROM");
+  if(fexists(get_cheat_filename(cart.fn, "cht"))) {
+    cheat.clear();
+    cheat.load(cheatfn);
  }

-uint8 mapper   = rom[info.header_index + MAPPER];
-uint8 rom_type = rom[info.header_index + ROM_TYPE];
-  if(mapper == 0x35 && rom_type == 0x55) {
-    info.srtc = true;
-  }
-
-  if(mapper == 0x32 && (rom_type == 0x43 || rom_type == 0x45)) {
-    info.sdd1 = true;
-  }
-
-  if(mapper == 0x20 && rom_type == 0xf3) {
-    info.c4 = true;
-  }
-
-  if((mapper == 0x20 || mapper == 0x21) && rom_type == 0x03) {
-    info.dsp1 = true;
-  }
-
-  if(mapper == 0x30 && rom_type == 0x05) {
-    info.dsp1 = true;
-  }
-
-  if(mapper == 0x31 && (rom_type == 0x03 || rom_type == 0x05)) {
-    info.dsp1 = true;
-  }
-
-  if(info.dsp1 == true) {
-    if((mapper & 0x2f) == 0x20 && info.rom_size <= 0x100000) {
-      info.dsp1_mapper = DSP1_LOROM_1MB;
-    } else if((mapper & 0x2f) == 0x20) {
-      info.dsp1_mapper = DSP1_LOROM_2MB;
-    } else if((mapper & 0x2f) == 0x21) {
-      info.dsp1_mapper = DSP1_HIROM;
-    }
-  }
-
-  if(mapper == 0x20 && rom_type == 0x05) {
-    info.dsp2 = true;
-  }
-
-  if(mapper == 0x30 && rom_type == 0x25) {
-    info.obc1 = true;
-  }
-
-  info.cart_mmio = info.c4 | info.dsp1 | info.dsp2 | info.obc1;
-
-  if(rom[info.header_index + SRAM_SIZE] & 7) {
-    info.ram_size = 1024 << (rom[info.header_index + SRAM_SIZE] & 7);
-  } else {
-    info.ram_size = 0;
-  }
-
-  memcpy(&info.name, &rom[info.header_index + CART_NAME], 21);
-  info.name[21] = 0;
-
-  for(int i = 0; i < 22; i++) {
-    if(info.name[i] & 0x80) {
-      info.name[i] = '?';
-    }
-  }
-}
-
-void Cartridge::find_header() {
-int32 score_lo = 0,
-      score_hi = 0,
-      score_ex = 0;
-
-  if(info.rom_size < 0x010000) {
-  //cart too small to be anything but lorom
-    info.header_index = 0x007fc0;
-    return;
-  }
-
-  if((rom[0x7fc0 + MAPPER] & ~0x10) == 0x20)score_lo++;
-  if((rom[0xffc0 + MAPPER] & ~0x10) == 0x21)score_hi++;
-
-  if(rom[0x7fc0 + ROM_TYPE] < 0x08)score_lo++;
-  if(rom[0xffc0 + ROM_TYPE] < 0x08)score_hi++;
-
-  if(rom[0x7fc0 + ROM_SIZE] < 0x10)score_lo++;
-  if(rom[0xffc0 + ROM_SIZE] < 0x10)score_hi++;
-
-  if(rom[0x7fc0 + SRAM_SIZE] < 0x08)score_lo++;
-  if(rom[0xffc0 + SRAM_SIZE] < 0x08)score_hi++;
-
-  if(rom[0x7fc0 + REGION] < 14)score_lo++;
-  if(rom[0xffc0 + REGION] < 14)score_hi++;
-
-  if(rom[0x7fc0 + LICENSE] < 3)score_lo++;
-  if(rom[0xffc0 + LICENSE] < 3)score_hi++;
-
-  if(rom[0x7fc0 + RESH] & 0x80)score_lo += 2;
-  if(rom[0xffc0 + RESH] & 0x80)score_hi += 2;
-
-uint16 cksum, icksum;
-  cksum  = rom[0x7fc0 +  CKSUM] | (rom[0x7fc0 +  CKSUM + 1] << 8);
-  icksum = rom[0x7fc0 + ICKSUM] | (rom[0x7fc0 + ICKSUM + 1] << 8);
-  if((cksum + icksum) == 0xffff && (cksum != 0) && (icksum != 0)) {
-    score_lo += 8;
-  }
-
-  cksum  = rom[0xffc0 +  CKSUM] | (rom[0xffc0 +  CKSUM + 1] << 8);
-  icksum = rom[0xffc0 + ICKSUM] | (rom[0xffc0 + ICKSUM + 1] << 8);
-  if((cksum + icksum) == 0xffff && (cksum != 0) && (icksum != 0)) {
-    score_hi += 8;
-  }
-
-  if(info.rom_size < 0x401000) {
-    score_ex = 0;
-  } else {
-    if(rom[0x7fc0 + MAPPER] == 0x32)score_lo++;
-    else score_ex += 16;
-  }
-
-  if(score_lo >= score_hi && score_lo >= score_ex) {
-    info.header_index = 0x007fc0;
-  } else if(score_hi >= score_ex) {
-    info.header_index = 0x00ffc0;
-  } else {
-    info.header_index = 0x40ffc0;
-  }
-}
-
-void Cartridge::load_sram() {
-  if(info.ram_size == 0) {
-    sram = 0;
-    return;
-  }
-
-FileReader ff(sram_fn);
-  if(!ff.ready()) {
-    sram = (uint8*)malloc(info.ram_size);
-    memset(sram, 0xff, info.ram_size);
-    return;
-  }
-
-  sram = ff.read(info.ram_size);
-}
-
-void Cartridge::save_sram() {
-  if(info.ram_size == 0)return;
-
-FileWriter ff(sram_fn);
-  if(!ff.ready())return;
-
-  ff.write(sram, info.ram_size);
-}
-
-void Cartridge::load_rom(Reader &rf) {
-uint size   = rf.size();
-bool header = ((size & 0x7fff) == 512);
-  info.rom_size = size - (header ? 512 : 0);
-  if(info.rom_size & 0x7fff) {
-    info.rom_size += 0x8000 - (info.rom_size & 0x7fff);
-  }
-
-uint8 *base_rom = rf.read(info.rom_size + (header ? 512 : 0));
-  if(header) {
-    memcpy(rom_header, base_rom, 512);
-  } else {
-    memset(rom_header, 0x00, 512);
-  }
-
-  rom = (uint8*)malloc(info.rom_size);
-  memcpy(rom, base_rom + (header ? 512 : 0), info.rom_size);
-  SafeFree(base_rom);
-
-  info.crc32 = 0xffffffff;
-  for(int32 i = 0; i < info.rom_size; i++) {
-    info.crc32 = crc32_adjust(info.crc32, rom[i]);
-  }
-  info.crc32 = ~info.crc32;
-}
-
-void Cartridge::patch_rom(Reader &rf) {
-UPS<ramfile, ramfile, ramfile> ups;
-uint   patchsize = rf.size();
-uint8 *patchdata = rf.read();
-
-  fopen(ups.original, 0, file::mode_writeread);
-  fopen(ups.modified, 0, file::mode_writeread);
-  fopen(ups.patch.fp, 0, file::mode_writeread);
-
-  fwrite(ups.original, rom, info.rom_size);
-  fwrite(ups.patch.fp, patchdata, patchsize);
-
-  if(ups.apply() == true) {
-    info.crc32    = ups.modified_crc32;
-    info.rom_size = ups.modified_filesize;
-    rom = (uint8*)realloc(rom, info.rom_size);
-    fseek(ups.modified, 0, file::seek_start);
-    fread(ups.modified, rom, info.rom_size);
-  }
-}
-
-bool Cartridge::load(const char *fn) {
-  if(cart_loaded == true)return false;
-  if(strlen(fn) < 3)return false;
-
-  dprintf("* Loading \"%s\"...", fn);
-
-  strcpy(rom_fn, fn);
-
-  switch(Reader::detect(rom_fn)) {
-
-  case Reader::RF_NORMAL: {
-  FileReader ff(rom_fn);
-    if(!ff.ready()) {
-      alert("Error loading image file (%s)!", rom_fn);
-      return false;
-    }
-    load_rom(ff);
-  } break;
-
-#ifdef GZIP_SUPPORT
-  case Reader::RF_GZ: {
-  GZReader gf(rom_fn);
-    if(!gf.ready()) {
-      alert("Error loading image file (%s)!", rom_fn);
-      return false;
-    }
-    load_rom(gf);
-  } break;
-
-  case Reader::RF_ZIP: {
-  ZipReader zf(rom_fn);
-    load_rom(zf);
-  } break;
-#endif
-
-#ifdef JMA_SUPPORT
-  case Reader::RF_JMA: {
-    try {
-    JMAReader jf(rom_fn);
-      load_rom(jf);
-    } catch(JMA::jma_errors jma_error) {
-      alert("Error loading image file (%s)!", rom_fn);
-      return false;
-    }
-  } break;
-#endif
-
-  }
-
-//remove ROM extension
-  strcpy(sram_fn, fn);
-  for(int i = strlen(fn) - 1; i >= 0; i--) {
-    if(sram_fn[i] == '.') {
-      sram_fn[i] = 0;
-      break;
-    }
-  }
-
-//add SRAM extension
-  strcat(sram_fn, ".");
-  strcat(sram_fn, config::fs.save_ext.sget());
-
-stringarray save_path;
-  strcpy(save_path, config::fs.save_path.sget());
-  replace(save_path, "\\", "/");
-  if(strlen(save_path) && !strend(save_path, "/")) { strcat(save_path, "/"); }
-
-  if(strlen(save_path) != 0) {
-  //override default path (current directory)
-  stringarray new_fn, parts;
-    strcpy(new_fn, sram_fn);
-    replace(new_fn, "\\", "/");
-    split(parts, "/", new_fn);
-
-  //add new SRAM path
-    strcpy(new_fn, save_path);
-
-  //append fs.base_path if fs.sram_path is not fully-qualified path
-    if(strbegin(new_fn, "./") == true) {
-      strltrim(new_fn, "./");
-      strcpy(new_fn[1], new_fn[0]);
-      strcpy(new_fn[0], config::fs.base_path.sget());
-      strcat(new_fn[0], new_fn[1]);
-    }
-
-  //finally, append SRAM file name
-    strcat(new_fn, parts[count(parts) - 1]);
-    strcpy(sram_fn, strptr(new_fn));
-  }
-
-//load cheat file if it exists
-  strcpy(cheat_fn, sram_fn);
-  strrtrim(cheat_fn, config::fs.save_ext.sget());
-  strrtrim(cheat_fn, ".");
-  strcat(cheat_fn, ".cht");
-
-  if(fexists(cheat_fn) == true) {
-  FileReader ff(cheat_fn);
-    cheat.load(ff);
-  }
-
-//load patch file if it exists
-  strcpy(patch_fn, sram_fn);
-  strrtrim(patch_fn, config::fs.save_ext.sget());
-  strrtrim(patch_fn, ".");
-  strcat(patch_fn, ".ups");
-
-  if(fexists(patch_fn) == true) {
-  FileReader ff(patch_fn);
-    patch_rom(ff);
-  }
-
-#ifdef GZIP_SUPPORT
-  else {
-    strrtrim(patch_fn, ".ups");
-    strcat(patch_fn, ".upz");
-    if(fexists(patch_fn) == true) {
-    ZipReader zf(patch_fn);
-      patch_rom(zf);
-    }
-  }
-#endif
-
-  if(read_database() == true) {
-    read_dbi();
-  } else {
-    find_header();
-    read_header();
-  }
-
-  load_sram();
-  cart_loaded = true;
-
-  r_mem->load_cart();
-  return true;
+  cart.loaded = true;
+  bus.load_cart();
 }

 bool Cartridge::unload() {
-  if(cart_loaded == false)return false;
+  if(cart.loaded == false) return false;

-  r_mem->unload_cart();
+  bus.unload_cart();

-  if(sram) { save_sram(); }
-  SafeFree(rom);
-  SafeFree(sram);
+  switch(info.type) {
+    case CartridgeNormal:      unload_cart_normal(); break;
+    case CartridgeBSX:         unload_cart_bsx();    break;
+    case CartridgeBSC:         unload_cart_bsc();    break;
+    case CartridgeSufamiTurbo: unload_cart_st();     break;
+  }

-  if(cheat.count() > 0 || fexists(cheat_fn)) {
-  FileWriter ff(cheat_fn);
-    cheat.save(ff);
+  if(cart.rom) { delete[] cart.rom; cart.rom = 0; }
+  if(cart.ram) { delete[] cart.ram; cart.ram = 0; }
+  if(cart.rtc) { delete[] cart.rtc; cart.rtc = 0; }
+  if(bs.ram)   { delete[] bs.ram;   bs.ram   = 0; }
+  if(stA.rom)  { delete[] stA.rom;  stA.rom  = 0; }
+  if(stA.ram)  { delete[] stA.ram;  stA.ram  = 0; }
+  if(stB.rom)  { delete[] stB.rom;  stB.rom  = 0; }
+  if(stB.ram)  { delete[] stB.ram;  stB.ram  = 0; }
+
+  char fn[PATH_MAX];
+  strcpy(fn, cart.fn);
+  modify_extension(fn, "cht");
+  if(cheat.count() > 0 || fexists(get_cheat_filename(cart.fn, "cht"))) {
+    cheat.save(cheatfn);
    cheat.clear();
  }

-  cart_loaded = false;
+  cart.loaded = false;
  return true;
 }

 Cartridge::Cartridge() {
-  load_database();
-
-  cart_loaded = false;
-
-  rom  = 0;
-  sram = 0;
+  cart.loaded = false;
 }

 Cartridge::~Cartridge() {
-  if(cart_loaded == true) {
-    unload();
-  }
+  if(cart.loaded == true) unload();
 }
@@ -1,96 +1,160 @@
 class Cartridge {
 public:
+  enum CartridgeType {
+    CartridgeNormal,
+    CartridgeBSX,
+    CartridgeBSC,
+    CartridgeSufamiTurbo,
+  };

-/*****
- * cart database
- *****/
+  enum HeaderField {
+    CART_NAME = 0x00,
+    MAPPER    = 0x15,
+    ROM_TYPE  = 0x16,
+    ROM_SIZE  = 0x17,
+    RAM_SIZE  = 0x18,
+    REGION    = 0x19,
+    COMPANY   = 0x1a,
+    VERSION   = 0x1b,
+    ICKSUM    = 0x1c,
+    CKSUM     = 0x1e,
+    RESL      = 0x3c,
+    RESH      = 0x3d,
+  };
+
+  enum Region {
+    NTSC,
+    PAL,
+  };

-#include "db/db.h"
-db_item dbi;
-  uint8 *database;
-  uint   database_size;
-  uint   database_blocksize;
-  void   load_database();
-  bool   read_database();
+  enum MemoryMapper {
+    LoROM,
+    HiROM,
+    ExLoROM,
+    ExHiROM,
+    SPC7110ROM,
+    BSXROM,
+    BSCLoROM,
+    BSCHiROM,
+    STROM,
+  };

-//
+  enum DSP1MemoryMapper {
+    DSP1Unmapped,
+    DSP1LoROM1MB,
+    DSP1LoROM2MB,
+    DSP1HiROM,
+  };

-bool cart_loaded;
-char rom_fn[4096], sram_fn[4096], cheat_fn[4096], patch_fn[4096];
+  struct {
+    bool loaded;
+    char fn[PATH_MAX];
+    uint8 *rom, *ram, *rtc;
+    uint rom_size, ram_size, rtc_size;
+  } cart;

-uint8 rom_header[512], *rom, *sram;
+  struct {
+    char fn[PATH_MAX];
+    uint8 *ram;
+    uint ram_size;
+  } bs;

-enum {
-//header fields
-  CART_NAME = 0x00,
-  MAPPER    = 0x15,
-  ROM_TYPE  = 0x16,
-  ROM_SIZE  = 0x17,
-  SRAM_SIZE = 0x18,
-  REGION    = 0x19,
-  LICENSE   = 0x1a,
-  VERSION   = 0x1b,
-  ICKSUM    = 0x1c,
-  CKSUM     = 0x1e,
-  RESL      = 0x3c,
-  RESH      = 0x3d,
+  struct {
+    char fn[PATH_MAX];
+    uint8 *rom, *ram;
+    uint rom_size, ram_size;
+  } stA, stB;

-//regions
-  NTSC = 0,
-  PAL  = 1,
+  struct {
+    CartridgeType type;

-//memory mappers
-  PCB     = 0x00,
-  LOROM   = 0x20,
-  HIROM   = 0x21,
-  EXLOROM = 0x22,
-  EXHIROM = 0x25,
+    uint32 crc32;
+    char filename[PATH_MAX * 4];
+    char name[128];
+    bool patched;

-//special chip memory mappers
-  DSP1_LOROM_1MB = 1,
-  DSP1_LOROM_2MB = 2,
-  DSP1_HIROM     = 3,
-};
+    Region region;
+    MemoryMapper mapper;
+    uint rom_size;
+    uint ram_size;

-struct {
-  uint32 crc32;
-  char   name[128];
-  char   pcb[32];
+    bool bsxbase;
+    bool bsxcart;
+    bool bsxflash;
+    bool st;
+    bool superfx;
+    bool sa1;
+    bool srtc;
+    bool sdd1;
+    bool spc7110;
+    bool spc7110rtc;
+    bool cx4;
+    bool dsp1;
+    bool dsp2;
+    bool dsp3;
+    bool dsp4;
+    bool obc1;
+    bool st010;
+    bool st011;
+    bool st018;

-  uint   region;
-  uint   mapper;
-  uint   rom_size;
-  uint   ram_size;
+    DSP1MemoryMapper dsp1_mapper;

-//set to true for games that need cart MMIO mapping (c4, dsp-n, ...),
-//for games that map outside the standard MMIO range of $2000-$5fff
-  bool   cart_mmio;
-  bool   srtc;
-  bool   sdd1;
-  bool   c4;
-  bool   dsp1;
-  bool   dsp2;
-  bool   obc1;
+    uint header_index;
+  } info;

-  uint   dsp1_mapper;
+  MemoryMapper mapper();
+  Region region();

-//HiROM / LoROM specific code
-  uint   header_index;
-} info;
+  void load_cart_normal(const char*);
+  void load_cart_bsx(const char*, const char*);
+  void load_cart_bsc(const char*, const char*);
+  void load_cart_st(const char*, const char*, const char*);
+
+  void unload_cart_normal();
+  void unload_cart_bsx();
+  void unload_cart_bsc();
+  void unload_cart_st();
+
+  bool loaded();
+  void load_begin(CartridgeType);
+  void load_end();
+  bool unload();

-  void load_rom(Reader &rf);
-  void patch_rom(Reader &rf);
-  void load_sram();
-  void save_sram();
-  void read_dbi();
  void find_header();
  void read_header();
-  bool loaded() { return cart_loaded; }
-  bool load(const char *fn);
-  bool unload();
+  void read_extended_header();
+
+  enum CompressionMode {
+    CompressionNone,    //always load without compression
+    CompressionInspect, //use file header inspection
+    CompressionAuto,    //use file extension or file header inspection (configured by user)
+  };
+  bool load_file(const char *fn, uint8 *&data, uint &size, CompressionMode compression = CompressionNone);
+  bool save_file(const char *fn, uint8 *data, uint size);
+  bool apply_patch(const uint8_t *pdata, unsigned psize, uint8_t *&data, unsigned &size);
+  char* modify_extension(char *filename, const char *extension);
+  char* get_base_filename(char *filename);
+  char* get_path_filename(char *filename, const char *path, const char *source, const char *extension);
+  char* get_patch_filename(const char *source, const char *extension);
+  char* get_save_filename(const char *source, const char *extension);
+  char* get_cheat_filename(const char *source, const char *extension);

  Cartridge();
  ~Cartridge();
+
+private:
+  char patchfn[PATH_MAX];
+  char savefn[PATH_MAX];
+  char rtcfn[PATH_MAX];
+  char cheatfn[PATH_MAX];
+};
+
+namespace memory {
+  extern MappedRAM cartrom, cartram, cartrtc;
+  extern MappedRAM bscram;
+  extern MappedRAM stArom, stAram;
+  extern MappedRAM stBrom, stBram;
 };

 extern Cartridge cartridge;
@@ -0,0 +1,65 @@
+#ifdef CART_CPP
+
+void Cartridge::load_cart_bsc(const char *base, const char *slot) {
+  if(!base || !*base) return;
+
+  strcpy(cart.fn, base);
+  strcpy(bs.fn, slot ? slot : "");
+  load_begin(CartridgeBSC);
+
+  uint8_t *data = 0;
+  unsigned size;
+  load_file(cart.fn, data, size, CompressionAuto);
+  cart.rom = data, cart.rom_size = size;
+
+  if(load_file(get_patch_filename(cart.fn, "ups"), data, size, CompressionInspect) == true) {
+    apply_patch(data, size, cart.rom, cart.rom_size);
+    delete[] data;
+  }
+
+  if(*bs.fn) {
+    if(load_file(bs.fn, data, size, CompressionAuto) == true) {
+      info.bsxflash = true;
+      bs.ram = data, bs.ram_size = size;
+      if(load_file(get_patch_filename(bs.fn, "ups"), data, size, CompressionInspect) == true) {
+        apply_patch(data, size, bs.ram, bs.ram_size);
+        delete[] data;
+      }
+    }
+  }
+
+  find_header();
+  read_header();
+
+  info.mapper = cartridge.info.header_index == 0x7fc0 ? BSCLoROM : BSCHiROM;
+  info.region = NTSC;
+
+  if(info.ram_size > 0) {
+    cart.ram = new uint8_t[cart.ram_size = info.ram_size];
+    memset(cart.ram, 0xff, cart.ram_size);
+
+    if(load_file(get_save_filename(cart.fn, "srm"), data, size, CompressionNone) == true) {
+      memcpy(cart.ram, data, min(size, cart.ram_size));
+      delete[] data;
+    }
+  }
+
+  load_end();
+
+  //set base filename
+  strcpy(info.filename, cart.fn);
+  get_base_filename(info.filename);
+  if(*bs.fn) {
+    char filenameBS[PATH_MAX];
+    strcpy(filenameBS, bs.fn);
+    get_base_filename(filenameBS);
+    strcat(info.filename, " + ");
+    strcat(info.filename, filenameBS);
+  }
+}
+
+void Cartridge::unload_cart_bsc() {
+  if(cart.ram) save_file(get_save_filename(cart.fn, "srm"), cart.ram, cart.ram_size);
+}
+
+#endif //ifdef CART_CPP
@@ -0,0 +1,61 @@
+#ifdef CART_CPP
+
+void Cartridge::load_cart_bsx(const char *base, const char *slot) {
+  if(!base || !*base) return;
+
+  strcpy(cart.fn, base);
+  strcpy(bs.fn, slot ? slot : "");
+
+  load_begin(CartridgeBSX);
+  info.bsxbase = true;
+  info.bsxcart = true;
+  info.mapper = BSXROM;
+  info.region = NTSC;
+
+  uint8_t *data = 0;
+  unsigned size;
+  load_file(cart.fn, data, size, CompressionAuto);
+  cart.rom = data, cart.rom_size = size;
+  cart.ram = 0, cart.ram_size = 0;
+
+  if(load_file(get_patch_filename(cart.fn, "ups"), data, size, CompressionInspect) == true) {
+    apply_patch(data, size, cart.rom, cart.rom_size);
+    delete[] data;
+  }
+
+  memset(bsxcart.sram.handle (), 0x00, bsxcart.sram.size ());
+  memset(bsxcart.psram.handle(), 0x00, bsxcart.psram.size());
+
+  if(load_file(get_save_filename(cart.fn, "srm"), data, size, CompressionNone) == true) {
+    memcpy(bsxcart.sram.handle (), data, min(bsxcart.sram.size (), size));
+    delete[] data;
+  }
+
+  if(load_file(get_save_filename(cart.fn, "psr"), data, size, CompressionNone) == true) {
+    memcpy(bsxcart.psram.handle(), data, min(bsxcart.psram.size(), size));
+    delete[] data;
+  }
+
+  if(*bs.fn) {
+    if(load_file(bs.fn, data, size, CompressionAuto) == true) {
+      info.bsxflash = true;
+      bs.ram = data, bs.ram_size = size;
+      if(load_file(get_patch_filename(bs.fn, "ups"), data, size, CompressionInspect) == true) {
+        apply_patch(data, size, bs.ram, bs.ram_size);
+        delete[] data;
+      }
+    }
+  }
+
+  load_end();
+
+  strcpy(info.filename, !*bs.fn ? cart.fn : bs.fn);
+  get_base_filename(info.filename);
+}
+
+void Cartridge::unload_cart_bsx() {
+  save_file(get_save_filename(cart.fn, "srm"), bsxcart.sram.handle (), bsxcart.sram.size ());
+  save_file(get_save_filename(cart.fn, "psr"), bsxcart.psram.handle(), bsxcart.psram.size());
+}
+
+#endif //ifdef CART_CPP
@@ -0,0 +1,177 @@
+#ifdef CART_CPP
+
+#include "../reader/filereader.h"
+
+#if defined(GZIP_SUPPORT)
+  #include "../reader/gzreader.h"
+  #include "../reader/zipreader.h"
+#endif
+
+#if defined(JMA_SUPPORT)
+  #include "../reader/jmareader.h"
+#endif
+
+char* Cartridge::modify_extension(char *filename, const char *extension) {
+  int i;
+  for(i = strlen(filename); i >= 0; i--) {
+    if(filename[i] == '.') break;
+    if(filename[i] == '/') break;
+    if(filename[i] == '\\') break;
+  }
+  if(i > 0 && filename[i] == '.') filename[i] = 0;
+  strcat(filename, ".");
+  strcat(filename, extension);
+  return filename;
+}
+
+//remove directory information and file extension ("/foo/bar.ext" -> "bar")
+char* Cartridge::get_base_filename(char *filename) {
+  //remove extension
+  for(int i = strlen(filename) - 1; i >= 0; i--) {
+    if(filename[i] == '.') {
+      filename[i] = 0;
+      break;
+    }
+  }
+
+  //remove directory information
+  for(int i = strlen(filename) - 1; i >= 0; i--) {
+    if(filename[i] == '/' || filename[i] == '\\') {
+      i++;
+      char *output = filename;
+      while(true) {
+        *output++ = filename[i];
+        if(!filename[i]) break;
+        i++;
+      }
+      break;
+    }
+  }
+}
+
+char* Cartridge::get_path_filename(char *filename, const char *path, const char *source, const char *extension) {
+  strcpy(filename, source);
+  for(char *p = filename; *p; p++) { if(*p == '\\') *p = '/'; }
+  modify_extension(filename, extension);
+
+  //override path with user-specified folder, if one was defined
+  if(*path) {
+    lstring part;
+    split(part, "/", filename);
+    string fn = path;
+    if(strend(fn, "/") == false) strcat(fn, "/");
+    strcat(fn, part[count(part) - 1]);
+    strcpy(filename, fn);
+
+    //resolve relative path, if found
+    if(strbegin(fn, "./") == true) {
+      ltrim(fn, "./");
+      strcpy(filename, config::path.base);
+      strcat(filename, fn);
+    }
+  }
+
+  return filename;
+}
+
+char* Cartridge::get_patch_filename(const char *source, const char *extension) {
+  return get_path_filename(patchfn, config::path.patch, source, extension);
+}
+
+char* Cartridge::get_save_filename(const char *source, const char *extension) {
+  return get_path_filename(savefn, config::path.save, source, extension);
+}
+
+char* Cartridge::get_cheat_filename(const char *source, const char *extension) {
+  return get_path_filename(cheatfn, config::path.cheat, source, extension);
+}
+
+bool Cartridge::load_file(const char *fn, uint8 *&data, uint &size, CompressionMode compression) {
+  if(fexists(fn) == false) return false;
+
+  Reader::Type filetype = Reader::Normal;
+  if(compression == CompressionInspect) filetype = Reader::detect(fn, true);
+  if(compression == CompressionAuto) filetype = Reader::detect(fn, config::file.autodetect_type);
+
+  switch(filetype) {
+    default:
+      dprintf("* Warning: filetype detected as unsupported compression type.");
+      dprintf("* Will attempt to load as uncompressed file -- may fail.");
+    case Reader::Normal: {
+      FileReader ff(fn);
+      if(!ff.ready()) {
+        alert("Error loading image file (%s)!", fn);
+        return false;
+      }
+      size = ff.size();
+      data = ff.read();
+    } break;
+
+    #ifdef GZIP_SUPPORT
+    case Reader::GZIP: {
+      GZReader gf(fn);
+      if(!gf.ready()) {
+        alert("Error loading image file (%s)!", fn);
+        return false;
+      }
+      size = gf.size();
+      data = gf.read();
+    } break;
+
+    case Reader::ZIP: {
+      ZipReader zf(fn);
+      size = zf.size();
+      data = zf.read();
+    } break;
+    #endif
+
+    #ifdef JMA_SUPPORT
+    case Reader::JMA: {
+      try {
+        JMAReader jf(fn);
+        size = jf.size();
+        data = jf.read();
+      } catch(JMA::jma_errors jma_error) {
+        alert("Error loading image file (%s)!", fn);
+        return false;
+      }
+    } break;
+    #endif
+  }
+
+  return true;
+}
+
+bool Cartridge::apply_patch(const uint8_t *pdata, const unsigned psize, uint8_t *&data, unsigned &size) {
+  uint8_t *outdata = 0;
+  unsigned outsize;
+  ups patcher;
+  ups::result result = patcher.apply(pdata, psize, data, size, outdata, outsize);
+
+  bool apply = false;
+  if(result == ups::ok) apply = true;
+  if(config::file.bypass_patch_crc32 == true) {
+    if(result == ups::input_crc32_invalid) apply = true;
+    if(result == ups::output_crc32_invalid) apply = true;
+  }
+
+  if(apply == true) {
+    delete[] data;
+    data = new uint8_t[size = outsize];
+    memcpy(data, outdata, outsize);
+  } else {
+    dprintf("* Warning: patch application failed!");
+  }
+
+  if(outdata) delete[] outdata;
+}
+
+bool Cartridge::save_file(const char *fn, uint8 *data, uint size) {
+  FILE *fp = fopen(fn, "wb");
+  if(!fp) return false;
+  fwrite(data, 1, size, fp);
+  fclose(fp);
+  return true;
+}
+
+#endif //ifdef CART_CPP
@@ -0,0 +1,197 @@
+#ifdef CART_CPP
+
+void Cartridge::read_header() {
+  uint8 *rom = cart.rom;
+  uint index = info.header_index;
+  uint8 mapper   = rom[index + MAPPER];
+  uint8 rom_type = rom[index + ROM_TYPE];
+  uint8 rom_size = rom[index + ROM_SIZE];
+  uint8 company  = rom[index + COMPANY];
+  uint8 region   = rom[index + REGION] & 0x7f;
+
+  //detect presence of BS-X flash cartridge connector (reads extended header information)
+  bool has_bsxflash = false;
+  if(rom[index - 14] == 'Z') {
+    if(rom[index - 11] == 'J') {
+      uint8 n13 = rom[index - 13];
+      if((n13 >= 'A' && n13 <= 'Z') || (n13 >= '0' && n13 <= '9')) {
+        if(company == 0x33 || (rom[index - 10] == 0x00 && rom[index - 4] == 0x00)) {
+          has_bsxflash = true;
+        }
+      }
+    }
+  }
+
+  if(has_bsxflash == true) {
+    info.mapper = index == 0x7fc0 ? BSCLoROM : BSCHiROM;
+  } else if(index == 0x7fc0 && cart.rom_size >= 0x401000) {
+    info.mapper = ExLoROM;
+  } else if(index == 0x7fc0 && mapper == 0x32) {
+    info.mapper = ExLoROM;
+  } else if(index == 0x7fc0) {
+    info.mapper = LoROM;
+  } else if(index == 0xffc0) {
+    info.mapper = HiROM;
+  } else { //index == 0x40ffc0
+    info.mapper = ExHiROM;
+  }
+
+  if(mapper == 0x20 && (rom_type == 0x13 || rom_type == 0x14 || rom_type == 0x15 || rom_type == 0x1a)) {
+    info.superfx = true;
+  }
+
+  if(mapper == 0x23 && (rom_type == 0x34 || rom_type == 0x35)) {
+    info.sa1 = true;
+  }
+
+  if(mapper == 0x35 && rom_type == 0x55) {
+    info.srtc = true;
+  }
+
+  if(mapper == 0x32 && (rom_type == 0x43 || rom_type == 0x45)) {
+    info.sdd1 = true;
+  }
+
+  if(mapper == 0x3a && (rom_type == 0xf5 || rom_type == 0xf9)) {
+    info.spc7110 = true;
+    info.spc7110rtc = (rom_type == 0xf9);
+    info.mapper = SPC7110ROM;
+  }
+
+  if(mapper == 0x20 && rom_type == 0xf3) {
+    info.cx4 = true;
+  }
+
+  if((mapper == 0x20 || mapper == 0x21) && rom_type == 0x03) {
+    info.dsp1 = true;
+  }
+
+  if(mapper == 0x30 && rom_type == 0x05 && company != 0xb2) {
+    info.dsp1 = true;
+  }
+
+  if(mapper == 0x31 && (rom_type == 0x03 || rom_type == 0x05)) {
+    info.dsp1 = true;
+  }
+
+  if(info.dsp1 == true) {
+    if((mapper & 0x2f) == 0x20 && cart.rom_size <= 0x100000) {
+      info.dsp1_mapper = DSP1LoROM1MB;
+    } else if((mapper & 0x2f) == 0x20) {
+      info.dsp1_mapper = DSP1LoROM2MB;
+    } else if((mapper & 0x2f) == 0x21) {
+      info.dsp1_mapper = DSP1HiROM;
+    }
+  }
+
+  if(mapper == 0x20 && rom_type == 0x05) {
+    info.dsp2 = true;
+  }
+
+  if(mapper == 0x30 && rom_type == 0x05 && company == 0xb2) {
+    info.dsp3 = true;
+  }
+
+  if(mapper == 0x30 && rom_type == 0x03) {
+    info.dsp4 = true;
+  }
+
+  if(mapper == 0x30 && rom_type == 0x25) {
+    info.obc1 = true;
+  }
+
+  if(mapper == 0x30 && rom_type == 0xf6 && rom_size >= 10) {
+    info.st010 = true;
+  }
+
+  if(mapper == 0x30 && rom_type == 0xf6 && rom_size < 10) {
+    info.st011 = true;
+  }
+
+  if(mapper == 0x30 && rom_type == 0xf5) {
+    info.st018 = true;
+  }
+
+  if(rom[info.header_index + RAM_SIZE] & 7) {
+    info.ram_size = 1024 << (rom[info.header_index + RAM_SIZE] & 7);
+  } else {
+    info.ram_size = 0;
+  }
+
+  //0, 1, 13 = NTSC; 2 - 12 = PAL
+  info.region = (region <= 1 || region >= 13) ? NTSC : PAL;
+
+  memcpy(&info.name, &rom[info.header_index + CART_NAME], 21);
+  info.name[21] = 0;
+  trim(info.name);
+
+  //convert undisplayable characters (half-width katakana, etc) to '?' characters
+  for(int i = 0; i < 21; i++) {
+    if(info.name[i] & 0x80) info.name[i] = '?';
+  }
+
+  //always display something
+  if(!info.name[0]) strcpy(info.name, "(untitled)");
+}
+
+void Cartridge::find_header() {
+  int32 score_lo = 0, score_hi = 0, score_ex = 0;
+  uint8_t *rom = cart.rom;
+
+  if(cart.rom_size < 0x010000) {
+    //cart too small to be anything but lorom
+    info.header_index = 0x007fc0;
+    return;
+  }
+
+  if((rom[0x7fc0 + MAPPER] & ~0x10) == 0x20) score_lo++;
+  if((rom[0xffc0 + MAPPER] & ~0x10) == 0x21) score_hi++;
+
+  if(rom[0x7fc0 + ROM_TYPE] < 0x08) score_lo++;
+  if(rom[0xffc0 + ROM_TYPE] < 0x08) score_hi++;
+
+  if(rom[0x7fc0 + ROM_SIZE] < 0x10) score_lo++;
+  if(rom[0xffc0 + ROM_SIZE] < 0x10) score_hi++;
+
+  if(rom[0x7fc0 + RAM_SIZE] < 0x08) score_lo++;
+  if(rom[0xffc0 + RAM_SIZE] < 0x08) score_hi++;
+
+  if(rom[0x7fc0 + REGION] < 14) score_lo++;
+  if(rom[0xffc0 + REGION] < 14) score_hi++;
+
+  if(rom[0x7fc0 + COMPANY] < 3) score_lo++;
+  if(rom[0xffc0 + COMPANY] < 3) score_hi++;
+
+  if(rom[0x7fc0 + RESH] & 0x80) score_lo += 2;
+  if(rom[0xffc0 + RESH] & 0x80) score_hi += 2;
+
+  uint16 cksum, icksum;
+  cksum  = rom[0x7fc0 +  CKSUM] | (rom[0x7fc0 +  CKSUM + 1] << 8);
+  icksum = rom[0x7fc0 + ICKSUM] | (rom[0x7fc0 + ICKSUM + 1] << 8);
+  if((cksum + icksum) == 0xffff && (cksum != 0) && (icksum != 0)) {
+    score_lo += 8;
+  }
+
+  cksum  = rom[0xffc0 +  CKSUM] | (rom[0xffc0 +  CKSUM + 1] << 8);
+  icksum = rom[0xffc0 + ICKSUM] | (rom[0xffc0 + ICKSUM + 1] << 8);
+  if((cksum + icksum) == 0xffff && (cksum != 0) && (icksum != 0)) {
+    score_hi += 8;
+  }
+
+  if(cart.rom_size < 0x401000) {
+    score_ex = 0;
+  } else {
+    if(rom[0x7fc0 + MAPPER] == 0x32) score_lo++;
+    else score_ex += 12;
+  }
+
+  if(score_lo >= score_hi && score_lo >= score_ex) {
+    info.header_index = 0x007fc0;
+  } else if(score_hi >= score_ex) {
+    info.header_index = 0x00ffc0;
+  } else {
+    info.header_index = 0x40ffc0;
+  }
+}
+
+#endif //ifdef CART_CPP
@@ -0,0 +1,64 @@
+#ifdef CART_CPP
+
+void Cartridge::load_cart_normal(const char *filename) {
+  if(!filename || !*filename) return;
+
+  uint8_t *data = 0;
+  unsigned size;
+  if(load_file(filename, data, size, CompressionAuto) == false) return;
+  strcpy(cart.fn, filename);
+
+  load_begin(CartridgeNormal);
+
+  //load ROM data, ignore 512-byte header if detected
+  if((size & 0x7fff) != 512) {
+    cart.rom = new uint8_t[cart.rom_size = size];
+    memcpy(cart.rom, data, size);
+  } else {
+    cart.rom = new uint8_t[cart.rom_size = size - 512];
+    memcpy(cart.rom, data + 512, size - 512);
+  }
+  delete[] data;
+
+  if(load_file(get_patch_filename(cart.fn, "ups"), data, size, CompressionInspect) == true) {
+    apply_patch(data, size, cart.rom, cart.rom_size);
+    delete[] data;
+    info.patched = true;
+  }
+
+  info.crc32 = crc32_calculate(cart.rom, cart.rom_size);
+
+  find_header();
+  read_header();
+
+  if(info.ram_size > 0) {
+    cart.ram = new uint8_t[cart.ram_size = info.ram_size];
+    memset(cart.ram, 0xff, cart.ram_size);
+
+    if(load_file(get_save_filename(cart.fn, "srm"), data, size, CompressionNone) == true) {
+      memcpy(cart.ram, data, min(size, cart.ram_size));
+      delete[] data;
+    }
+  }
+
+  if(info.srtc || info.spc7110rtc) {
+    cart.rtc = new(zeromemory) uint8_t[cart.rtc_size = 20];
+    if(load_file(get_save_filename(cart.fn, "rtc"), data, size, CompressionNone) == true) {
+      memcpy(cart.rtc, data, min(size, cart.rtc_size));
+      delete[] data;
+    }
+  }
+
+  load_end();
+
+  //set base filename
+  strcpy(info.filename, cart.fn);
+  get_base_filename(info.filename);
+}
+
+void Cartridge::unload_cart_normal() {
+  if(cart.ram) save_file(get_save_filename(cart.fn, "srm"), cart.ram, cart.ram_size);
+  if(cart.rtc) save_file(get_save_filename(cart.fn, "rtc"), cart.rtc, cart.rtc_size);
+}
+
+#endif //ifdef CART_CPP
@@ -0,0 +1,96 @@
+#ifdef CART_CPP
+
+void Cartridge::load_cart_st(const char *base, const char *slotA, const char *slotB) {
+  if(!base || !*base) return;
+
+  strcpy(cart.fn, base);
+  strcpy(stA.fn, slotA ? slotA : "");
+  strcpy(stB.fn, slotB ? slotB : "");
+
+  load_begin(CartridgeSufamiTurbo);
+  info.st = true;
+  info.mapper = STROM;
+  info.region = NTSC;
+
+  uint8_t *data = 0;
+  unsigned size;
+  if(load_file(cart.fn, data, size, CompressionAuto) == true) {
+    cart.rom = new(zeromemory) uint8_t[cart.rom_size = 0x040000];
+    memcpy(cart.rom, data, min(size, cart.rom_size));
+    delete[] data;
+    if(load_file(get_patch_filename(cart.fn, "ups"), data, size, CompressionInspect) == true) {
+      apply_patch(data, size, cart.rom, cart.rom_size);
+      delete[] data;
+    }
+  }
+
+  if(*stA.fn) {
+    if(load_file(stA.fn, data, size, CompressionAuto) == true) {
+      stA.rom = new(zeromemory) uint8_t[stA.rom_size = 0x100000];
+      memcpy(stA.rom, data, min(size, stA.rom_size));
+      delete[] data;
+      if(load_file(get_patch_filename(stA.fn, "ups"), data, size, CompressionInspect) == true) {
+        apply_patch(data, size, stA.rom, stA.rom_size);
+        delete[] data;
+      }
+
+      stA.ram = new uint8_t[stA.ram_size = 0x020000];
+      memset(stA.ram, 0xff, stA.ram_size);
+
+      if(load_file(get_save_filename(stA.fn, "srm"), data, size, CompressionNone) == true) {
+        memcpy(stA.ram, data, min(size, 0x020000U));
+        delete[] data;
+      }
+    }
+  }
+
+  if(*stB.fn) {
+    if(load_file(stB.fn, data, size, CompressionAuto) == true) {
+      stB.rom = new(zeromemory) uint8_t[stB.rom_size = 0x100000];
+      memcpy(stB.rom, data, min(size, stB.rom_size));
+      delete[] data;
+      if(load_file(get_patch_filename(stB.fn, "ups"), data, size, CompressionInspect) == true) {
+        apply_patch(data, size, stB.rom, stB.rom_size);
+        delete[] data;
+      }
+
+      stB.ram = new uint8_t[stB.ram_size = 0x020000];
+      memset(stB.ram, 0xff, stB.ram_size);
+
+      if(load_file(get_save_filename(stB.fn, "srm"), data, size, CompressionNone) == true) {
+        memcpy(stB.ram, data, min(size, 0x020000U));
+        delete[] data;
+      }
+    }
+  }
+
+  load_end();
+
+  //set base filename
+  if(!*stA.fn && !*stB.fn) {
+    strcpy(info.filename, cart.fn);
+    get_base_filename(info.filename);
+  } else if(*stA.fn && !*stB.fn) {
+    strcpy(info.filename, stA.fn);
+    get_base_filename(info.filename);
+  } else if(!*stA.fn && *stB.fn) {
+    strcpy(info.filename, stB.fn);
+    get_base_filename(info.filename);
+  } else {
+    char filenameA[PATH_MAX], filenameB[PATH_MAX];
+    strcpy(filenameA, stA.fn);
+    get_base_filename(filenameA);
+    strcpy(filenameB, stB.fn);
+    get_base_filename(filenameB);
+    strcpy(info.filename, filenameA);
+    strcat(info.filename, " + ");
+    strcat(info.filename, filenameB);
+  }
+}
+
+void Cartridge::unload_cart_st() {
+  if(stA.ram) save_file(get_save_filename(stA.fn, "srm"), stA.ram, stA.ram_size);
+  if(stB.ram) save_file(get_save_filename(stB.fn, "srm"), stB.ram, stB.ram_size);
+}
+
+#endif //ifdef CART_CPP
@@ -1,37 +0,0 @@
-void Cartridge::load_database() {
-  database      = 0;
-  database_size = 0;
-
-FILE *fp;
-  fp = fopen("cart.db", "rb");
-  if(!fp)return;
-
-uint size = fsize(fp);
-  if(size < 8) {
-    fclose(fp);
-    return;
-  }
-
-  database = (uint8*)malloc(size);
-  fread(database, 1, size, fp);
-  fclose(fp);
-
-  database_blocksize = (database[6] << 0) | (database[7] << 8);
-  database_size      = (size - 8) / database_blocksize;
-}
-
-bool Cartridge::read_database() {
-uint i, crc32;
-  for(i = 0; i < database_size; i++) {
-  uint8 *p = database + 8 + (i * database_blocksize);
-    crc32  = *(p++) <<  0;
-    crc32 |= *(p++) <<  8;
-    crc32 |= *(p++) << 16;
-    crc32 |= *(p++) << 24;
-    if(crc32 == cartridge.info.crc32)break;
-  }
-  if(i >= database_size)return false;
-
-  db_read(dbi, database + 8 + (i * database_blocksize));
-  return true;
-}
@@ -1,47 +0,0 @@
-[0x7aedd703]
-name = "Der Langrisser (Japan) [!]"
-pcb  = "SHVC-1A3M-30"
-rom  = 16mbit
-ram  = 64kbit
-
-[0x35f9eecc]
-name = "Der Langrisser (Japan) (V1.1)"
-pcb  = "SHVC-1A3M-30" ;unverified (guess)
-rom  = 16mbit
-ram  = 64kbit
-
-[0x19bdcb19]
-name = "Derby Stallion '96 (Japan) [!]"
-pcb  = "BSC-1A5M-01"
-rom  =  24mbit
-ram  = 256kbit
-
-[0x9684526d]
-name = "Romancing SaGa (Japan) (V1.1) [!]"
-pcb  = "SHVC-1A3B-12"
-rom  =  8mbit
-ram  = 64kbit
-
-[0x675b6382]
-name = "RPG Tsukuru 2 (Japan)"
-pcb  = "BSC-1A7M-01" ;unverified
-rom  =  16mbit
-ram  = 512kbit
-
-[0xa5c0045e]
-name = "Secret of Evermore (USA) [!]"
-pcb  = "SHVC-1J3M-20"
-rom  = 32mbit
-ram  = 64kbit
-
-[0x5ebf7246]
-name = "Sound Novel Tsukuru (Japan) [!]"
-pcb  = "BSC-1A7M-10"
-rom  =  24mbit
-ram  = 512kbit
-
-[0x64a91e64]
-name = "Wanderers from Ys (USA) [!]"
-pcb  = "SHVC-1A3B-12"
-rom  =  8mbit
-ram  = 64kbit
@@ -1,3 +0,0 @@
-cl /nologo /O2 dbcreate.cpp
-@pause
-@del *.obj
@@ -1 +0,0 @@
-@del *.exe
@@ -1,2 +0,0 @@
-dbcreate
-@copy cart.db ..\..\..\cart.db
@@ -1,47 +0,0 @@
-struct db_item {
-  uint32 crc32;
-  char   name[128];
-  char   pcb [32];
-  uint32 rom;
-  uint32 ram;
-};
-
-void db_write(FILE *fp, db_item &dbi) {
-  fputc(dbi.crc32 >>  0, fp);
-  fputc(dbi.crc32 >>  8, fp);
-  fputc(dbi.crc32 >> 16, fp);
-  fputc(dbi.crc32 >> 24, fp);
-
-  fwrite(dbi.name, 1, 128, fp);
-  fwrite(dbi.pcb,  1,  32, fp);
-
-  fputc(dbi.rom >>  0, fp);
-  fputc(dbi.rom >>  8, fp);
-  fputc(dbi.rom >> 16, fp);
-  fputc(dbi.rom >> 24, fp);
-
-  fputc(dbi.ram >>  0, fp);
-  fputc(dbi.ram >>  8, fp);
-  fputc(dbi.ram >> 16, fp);
-  fputc(dbi.ram >> 24, fp);
-}
-
-void db_read(db_item &dbi, uint8 *data) {
-  dbi.crc32  = (*data++) <<  0;
-  dbi.crc32 |= (*data++) <<  8;
-  dbi.crc32 |= (*data++) << 16;
-  dbi.crc32 |= (*data++) << 24;
-
-  memcpy(dbi.name, data, 128); dbi.name[127] = 0; data += 128;
-  memcpy(dbi.pcb,  data,  32); dbi.pcb [ 31] = 0; data +=  32;
-
-  dbi.rom  = (*data++) <<  0;
-  dbi.rom |= (*data++) <<  8;
-  dbi.rom |= (*data++) << 16;
-  dbi.rom |= (*data++) << 24;
-
-  dbi.ram  = (*data++) <<  0;
-  dbi.ram |= (*data++) <<  8;
-  dbi.ram |= (*data++) << 16;
-  dbi.ram |= (*data++) << 24;
-}
@@ -1,117 +0,0 @@
-#include "../../lib/libbase.h"
-#include "../../lib/libvector.h"
-#include "../../lib/libstring.h"
-
-#include "../../lib/libstring.cpp"
-
-#include "db.h"
-
-FILE *fp;
-
-uint decode_size(substring &str) {
-//hex encoding
-  if(strbegin(str, "0x")) {
-    strltrim(str, "0x");
-    return strhex(str);
-  }
-
-//mbit encoding
-  if(strend(str, "mbit")) {
-    strrtrim(str, "mbit");
-    return strdec(str) * 1024 * 1024 / 8;
-  }
-
-//kbit encoding
-  if(strend(str, "kbit")) {
-    strrtrim(str, "kbit");
-    return strdec(str) * 1024 / 8;
-  }
-
-//decimal encoding
-  return strdec(str);
-}
-
-void build_block(substring &block) {
-string line, hashpart, part;
-  split(line, "\n", block);
-
-  if(strbegin(line[0], "[") == false) {
-    printf("error: invalid block detected: '%s'\n", strptr(line[0]));
-    return;
-  }
-
-  strltrim(line[0], "[");
-  strrtrim(line[0], "]");
-  replace(line[0], "0x", "");
-  split(hashpart, ",", line[0]);
-
-db_item dbi;
-  dbi.crc32 = 0;
- *dbi.name  = 0;
- *dbi.pcb   = 0;
-  dbi.rom   = 0;
-  dbi.ram   = 0;
-
-  for(int i = 1; i < count(line); i++) {
-  uint pos;
-    if(strpos(line[i], ";", pos) == true) {
-      strset(line[i], pos, 0);
-    }
-
-    if(strmatch(line[i], ""))continue;
-
-    split(part, "=", line[i]);
-    strunquote(part[1]);
-
-    if(strmatch(part[0], "name")) {
-      strncpy(dbi.name, strptr(part[1]), 128);
-      dbi.name[128] = 0;
-    }
-
-    if(strmatch(part[0], "pcb")) {
-      strncpy(dbi.pcb, strptr(part[1]), 32);
-      dbi.pcb[31] = 0;
-    }
-
-    if(strmatch(part[0], "rom")) {
-      dbi.rom = decode_size(part[1]);
-    }
-
-    if(strmatch(part[0], "ram")) {
-      dbi.ram = decode_size(part[1]);
-    }
-  }
-
-  for(int i = 0; i < count(hashpart); i++) {
-    dbi.crc32 = strhex(hashpart[i]);
-    db_write(fp, dbi);
-  }
-}
-
-void build_database() {
-string data, block;
-  if(strfread(data, "cartdb.txt") == false)return;
-
-  fp = fopen("cart.db", "wb");
-  fprintf(fp, "SNESDB");
-
-uint blocksize = 4 + 128 + 32 + 4 + 4;
-  fputc(blocksize >> 0, fp);
-  fputc(blocksize >> 8, fp);
-
-  replace (data, "\r", "");
-  qreplace(data, " ",  "");
-  qreplace(data, "\t", "");
-  split(block, "\n\n", data);
-
-  for(int i = 0; i < count(block); i++) {
-    build_block(block[i]);
-  }
-
-  fclose(fp);
-}
-
-int main() {
-  build_database();
-  return 0;
-}
@@ -0,0 +1,3 @@
+::@make platform=win compiler=mingw32-gcc
+@make platform=win compiler=mingw32-gcc enable_gzip=true enable_jma=true
+@pause
@@ -0,0 +1,2 @@
+make platform=x compiler=gcc
+#make platform=x compiler=gcc enable_gzip=true enable_jma=true
@@ -1,4 +1,5 @@
 #include "../base.h"
+#include "../reader/filereader.h"

 Cheat cheat;

@@ -9,24 +10,24 @@ Cheat cheat;
 *****/

 bool Cheat::decode(char *str, uint32 &addr, uint8 &data, uint8 &type) {
-stringarray t, part;
+  string t, part;
  strcpy(t, str);
-  strlower(t);
-  if(strlen(t) == 8 || (strlen(t) == 9 && strptr(t)[6] == ':')) {
-    type = CT_PRO_ACTION_REPLAY;
+  strlower(t());
+  if(strlen(t) == 8 || (strlen(t) == 9 && t()[6] == ':')) {
+    type = ProActionReplay;
    replace(t, ":", "");
-  uint32 r = strhex(t);
+    uint32 r = strhex((const char*)t);
    addr = r >> 8;
    data = r & 0xff;
    return true;
-  } else if(strlen(t) == 9 && strptr(t)[4] == '-') {
-    type = CT_GAME_GENIE;
+  } else if(strlen(t) == 9 && t()[4] == '-') {
+    type = GameGenie;
    replace(t, "-", "");
    strtr(t, "df4709156bc8a23e", "0123456789abcdef");
-  uint32 r = strhex(t);
-  //8421 8421 8421 8421 8421 8421
-  //abcd efgh ijkl mnop qrst uvwx
-  //ijkl qrst opab cduv wxef ghmn
+    uint32 r = strhex((const char*)t);
+    //8421 8421 8421 8421 8421 8421
+    //abcd efgh ijkl mnop qrst uvwx
+    //ijkl qrst opab cduv wxef ghmn
    addr = (!!(r & 0x002000) << 23) | (!!(r & 0x001000) << 22) |
           (!!(r & 0x000800) << 21) | (!!(r & 0x000400) << 20) |
           (!!(r & 0x000020) << 19) | (!!(r & 0x000010) << 18) |
@@ -46,10 +47,10 @@ stringarray t, part;
 }

 bool Cheat::encode(char *str, uint32 addr, uint8 data, uint8 type) {
-  if(type == CT_PRO_ACTION_REPLAY) {
+  if(type == ProActionReplay) {
    sprintf(str, "%0.6x:%0.2x", addr, data);
    return true;
-  } else if(type == CT_GAME_GENIE) {
+  } else if(type == GameGenie) {
  uint32 r = addr;
    addr = (!!(r & 0x008000) << 23) | (!!(r & 0x004000) << 22) |
           (!!(r & 0x002000) << 21) | (!!(r & 0x001000) << 20) |
@@ -78,9 +79,9 @@ bool Cheat::encode(char *str, uint32 addr, uint8 data, uint8 type) {
 *****/

 uint Cheat::mirror_address(uint addr) {
-  if((addr & 0x40e000) != 0x0000)return addr;
-//8k WRAM mirror
-//$[00-3f|80-bf]:[0000-1fff] -> $7e:[0000-1fff]
+  if((addr & 0x40e000) != 0x0000) return addr;
+  //8k WRAM mirror
+  //$[00-3f|80-bf]:[0000-1fff] -> $7e:[0000-1fff]
  return (0x7e0000 + (addr & 0x1fff));
 }

@@ -89,8 +90,8 @@ void Cheat::set(uint32 addr) {

  mask[addr >> 3] |= 1 << (addr & 7);
  if((addr & 0xffe000) == 0x7e0000) {
-  //mirror $7e:[0000-1fff] to $[00-3f|80-bf]:[0000-1fff]
-  uint mirror;
+    //mirror $7e:[0000-1fff] to $[00-3f|80-bf]:[0000-1fff]
+    uint mirror;
    for(int x = 0; x <= 0x3f; x++) {
      mirror = ((0x00 + x) << 16) + (addr & 0x1fff);
      mask[mirror >> 3] |= 1 << (mirror & 7);
@@ -103,16 +104,16 @@ void Cheat::set(uint32 addr) {
 void Cheat::clear(uint32 addr) {
  addr = mirror_address(addr);

-//is there more than one cheat code using the same address
-//(and likely a different override value) that is enabled?
-//if so, do not clear code lookup table entry for this address.
-uint8 r;
+  //is there more than one cheat code using the same address
+  //(and likely a different override value) that is enabled?
+  //if so, do not clear code lookup table entry for this address.
+  uint8 r;
  if(read(addr, r) == true)return;

  mask[addr >> 3] &= ~(1 << (addr & 7));
  if((addr & 0xffe000) == 0x7e0000) {
-  //mirror $7e:[0000-1fff] to $[00-3f|80-bf]:[0000-1fff]
-  uint mirror;
+    //mirror $7e:[0000-1fff] to $[00-3f|80-bf]:[0000-1fff]
+    uint mirror;
    for(int x = 0; x <= 0x3f; x++) {
      mirror = ((0x00 + x) << 16) + (addr & 0x1fff);
      mask[mirror >> 3] &= ~(1 << (mirror & 7));
@@ -132,13 +133,13 @@ uint8 r;
 bool Cheat::read(uint32 addr, uint8 &data) {
  addr = mirror_address(addr);
  for(int i = 0; i < cheat_count; i++) {
-    if(enabled(i) == false)continue;
+    if(enabled(i) == false) continue;
    if(addr == mirror_address(index[i].addr)) {
      data = index[i].data;
      return true;
    }
  }
-//code not found, or code is disabled
+  //code not found, or code is disabled
  return false;
 }

@@ -146,9 +147,10 @@ bool Cheat::read(uint32 addr, uint8 &data) {
 * update_cheat_status() will scan to see if any codes are
 * enabled. if any are, make sure the cheat system is on.
 * otherwise, turn cheat system off to speed up emulation.
- *****/
+ *****/
+
 void Cheat::update_cheat_status() {
-  for(int i = 0; i < cheat_count; i++) {
+  for(unsigned i = 0; i < cheat_count; i++) {
    if(index[i].enabled) {
      cheat_enabled = true;
      return;
@@ -162,11 +164,11 @@ void Cheat::update_cheat_status() {
 *****/

 bool Cheat::add(bool enable, char *code, char *desc) {
-  if(cheat_count >= CHEAT_LIMIT)return false;
+  if(cheat_count >= CheatLimit) return false;

-uint32 addr, len;
-uint8  data, type;
-  if(decode(code, addr, data, type) == false)return false;
+  uint32 addr, len;
+  uint8  data, type;
+  if(decode(code, addr, data, type) == false) return false;

  index[cheat_count].enabled = enable;
  index[cheat_count].addr = addr;
@@ -187,17 +189,17 @@ uint8  data, type;
 }

 bool Cheat::edit(uint32 n, bool enable, char *code, char *desc) {
-  if(n >= cheat_count)return false;
+  if(n >= cheat_count) return false;

-uint32 addr, len;
-uint8  data, type;
-  if(decode(code, addr, data, type) == false)return false;
+  uint32 addr, len;
+  uint8  data, type;
+  if(decode(code, addr, data, type) == false) return false;

-//disable current code and clear from code lookup table
+  //disable current code and clear from code lookup table
  index[n].enabled = false;
  clear(index[n].addr);

-//update code and enable in code lookup table
+  //update code and enable in code lookup table
  index[n].enabled = enable;
  index[n].addr = addr;
  index[n].data = data;
@@ -216,9 +218,9 @@ uint8  data, type;
 }

 bool Cheat::remove(uint32 n) {
-  if(n >= cheat_count)return false;
+  if(n >= cheat_count) return false;

-  for(int i = n; i < cheat_count; i++) {
+  for(unsigned i = n; i < cheat_count; i++) {
    index[i].enabled = index[i + 1].enabled;
    index[i].addr    = index[i + 1].addr;
    index[i].data    = index[i + 1].data;
@@ -232,7 +234,7 @@ bool Cheat::remove(uint32 n) {
 }

 bool Cheat::get(uint32 n, bool &enable, uint32 &addr, uint8 &data, char *code, char *desc) {
-  if(n >= cheat_count)return false;
+  if(n >= cheat_count) return false;
  enable = index[n].enabled;
  addr   = index[n].addr;
  data   = index[n].data;
@@ -246,19 +248,19 @@ bool Cheat::get(uint32 n, bool &enable, uint32 &addr, uint8 &data, char *code, c
 *****/

 bool Cheat::enabled(uint32 n) {
-  if(n >= cheat_count)return false;
+  if(n >= cheat_count) return false;
  return index[n].enabled;
 }

 void Cheat::enable(uint32 n) {
-  if(n >= cheat_count)return;
+  if(n >= cheat_count) return;
  index[n].enabled = true;
  set(index[n].addr);
  update_cheat_status();
 }

 void Cheat::disable(uint32 n) {
-  if(n >= cheat_count)return;
+  if(n >= cheat_count) return;
  index[n].enabled = false;
  clear(index[n].addr);
  update_cheat_status();
@@ -268,49 +270,40 @@ void Cheat::disable(uint32 n) {
 * cheat file manipulation routines
 *****/

-bool Cheat::load(Reader &rf) {
-  if(!rf.ready())return false;
+/* file format: */
+/* nnnn-nnnn = status, "description" \r\n */
+/* ... */

-uint8 *raw_data = rf.read();
-stringarray data, line;
-  raw_data[rf.size()] = 0;
-  strcpy(data, (char*)raw_data);
-  SafeFree(raw_data);
+bool Cheat::load(const char *fn) {
+  string data;
+  if(!fread(data, fn)) return false;
  replace(data, "\r\n", "\n");
+  qreplace(data, "=", ",");
+  qreplace(data, " ", "");

+  lstring line;
  split(line, "\n", data);
-  for(int i = 0; i < ::count(line); i++) {
-  stringarray part;
-  uint8  en = *(strptr(line[i]));
-    if(en == '+') {
-      strltrim(line[i], "+");
-    } else if(en == '-') {
-      strltrim(line[i], "-");
-    } else {
-      continue;
-    }
-    qreplace(line[i], " ", "");
-    qsplit(part, ",", line[i]);
-    if(::count(part) != 2)continue;
-    strunquote(part[1]);
-    add(en == '+', strptr(part[0]), strptr(part[1]));
+  for(unsigned i = 0; i < ::count(line); i++) {
+    lstring part;
+    split(part, ",", line[i]);
+    if(::count(part) != 3) continue;
+    trim(part[2], "\"");
+    add(part[1] == "enabled", part[0](), part[2]());
  }

  return true;
 }

-bool Cheat::save(Writer &wf) {
-  if(!wf.ready())return false;
-
-string data;
-char   t[4096];
-  strcpy(data, "");
-  for(int i = 0; i < cheat_count; i++) {
-    sprintf(t, "%c%s, \"%s\"\r\n", index[i].enabled ? '+' : '-', index[i].code, index[i].desc);
-    strcat(data, t);
+bool Cheat::save(const char *fn) {
+  FILE *fp = fopen(fn, "wb");
+  if(!fp) return false;
+  for(unsigned i = 0; i < cheat_count; i++) {
+    fprintf(fp, "%9s = %8s, \"%s\"\r\n",
+      index[i].code,
+      index[i].enabled ? "enabled" : "disabled",
+      index[i].desc);
  }
-
-  wf.write((uint8*)strptr(data), strlen(data));
+  fclose(fp);
  return true;
 }

@@ -320,12 +313,12 @@ char   t[4096];

 void Cheat::clear() {
  cheat_enabled = false;
-  cheat_count   = 0;
+  cheat_count = 0;
  memset(mask, 0, 0x200000);
-  for(int i = 0; i < CHEAT_LIMIT + 1; i++) {
+  for(unsigned i = 0; i <= CheatLimit; i++) {
    index[i].enabled = false;
-    index[i].addr    = 0x000000;
-    index[i].data    = 0x00;
+    index[i].addr = 0x000000;
+    index[i].data = 0x00;
    strcpy(index[i].code, "");
    strcpy(index[i].desc, "");
  }
@@ -1,48 +1,51 @@
-#define CHEAT_LIMIT 1024
-
 class Cheat {
-public:
-enum { CT_PRO_ACTION_REPLAY, CT_GAME_GENIE };
+public:
+  enum { CheatLimit = 1024 };

-struct CheatIndex {
-  bool   enabled;
-  uint32 addr;
-  uint8  data;
-  char   code[ 16 + 1];
-  char   desc[128 + 1];
-} index[CHEAT_LIMIT + 1];
-bool   cheat_enabled;
-uint32 cheat_count;
-uint8  mask[0x200000];
+  enum Type {
+    ProActionReplay,
+    GameGenie,
+  };
+
+  struct CheatIndex {
+    bool enabled;
+    uint32 addr;
+    uint8 data;
+    char code[ 16 + 1];
+    char desc[128 + 1];
+  } index[CheatLimit + 1];
+
+  bool cheat_enabled;
+  uint32 cheat_count;
+  uint8 mask[0x200000];

  inline bool enabled() { return cheat_enabled; }
  inline uint count() { return cheat_count; }
  inline bool exists(uint32 addr) { return bool(mask[addr >> 3] & 1 << (addr & 7)); }

-  bool  decode(char *str, uint32 &addr, uint8 &data, uint8 &type);
-  bool  encode(char *str, uint32  addr, uint8  data, uint8  type);
+  bool decode(char *str, uint32 &addr, uint8 &data, uint8 &type);
+  bool encode(char *str, uint32  addr, uint8  data, uint8  type);

-private:
-  uint  mirror_address(uint addr);
-  void  set(uint32 addr);
-  void  clear(uint32 addr);
-public:
+  bool read(uint32 addr, uint8 &data);

-  bool  read(uint32 addr, uint8 &data);
+  void update_cheat_status();
+  bool add(bool enable, char *code, char *desc);
+  bool edit(uint32 n, bool enable, char *code, char *desc);
+  bool get(uint32 n, bool &enable, uint32 &addr, uint8 &data, char *code, char *desc);
+  bool remove(uint32 n);
+  bool enabled(uint32 n);
+  void enable(uint32 n);
+  void disable(uint32 n);
+  bool load(const char *fn);
+  bool save(const char *fn);
+  void clear();

-  void  update_cheat_status();
-  bool  add(bool enable, char *code, char *desc);
-  bool  edit(uint32 n, bool enable, char *code, char *desc);
-  bool  get(uint32 n, bool &enable, uint32 &addr, uint8 &data, char *code, char *desc);
-  bool  remove (uint32 n);
-  bool  enabled(uint32 n);
-  void  enable (uint32 n);
-  void  disable(uint32 n);
-  bool  load(Reader &rf);
-  bool  save(Writer &wf);
-  void  clear();
-
-  Cheat();
+  Cheat();
+
+private:
+  uint mirror_address(uint addr);
+  void set(uint32 addr);
+  void clear(uint32 addr);
 };

 extern Cheat cheat;
@@ -0,0 +1,6 @@
+#include "../../base.h"
+#define BSX_CPP
+
+#include "bsx_base.cpp"
+#include "bsx_cart.cpp"
+#include "bsx_flash.cpp"
@@ -0,0 +1,77 @@
+class BSXBase : public MMIO {
+public:
+  void init();
+  void enable();
+  void power();
+  void reset();
+
+  uint8 mmio_read(uint addr);
+  void mmio_write(uint addr, uint8 data);
+
+private:
+  struct {
+    uint8 r2188, r2189, r218a, r218b;
+    uint8 r218c, r218d, r218e, r218f;
+    uint8 r2190, r2191, r2192, r2193;
+    uint8 r2194, r2195, r2196, r2197;
+    uint8 r2198, r2199, r219a, r219b;
+    uint8 r219c, r219d, r219e, r219f;
+
+    uint8 r2192_counter;
+    uint8 r2192_hour, r2192_minute, r2192_second;
+  } regs;
+};
+
+class BSXCart : public MMIO {
+public:
+  void init();
+  void enable();
+  void power();
+  void reset();
+
+  uint8 mmio_read(uint addr);
+  void mmio_write(uint addr, uint8 data);
+
+  MappedRAM sram;
+  MappedRAM psram;
+
+  BSXCart();
+  ~BSXCart();
+
+private:
+  uint8 *sram_data;  //256kbit SRAM
+  uint8 *psram_data; //  4mbit PSRAM
+
+  struct {
+    uint8 r[16];
+  } regs;
+
+  void update_memory_map();
+};
+
+class BSXFlash : public Memory {
+public:
+  void init();
+  void enable();
+  void power();
+  void reset();
+
+  uint size();
+  uint8 read(uint addr);
+  void write(uint addr, uint8 data);
+
+private:
+  struct {
+    uint command;
+    uint8 write_old;
+    uint8 write_new;
+
+    bool flash_enable;
+    bool read_enable;
+    bool write_enable;
+  } regs;
+};
+
+extern BSXBase  bsxbase;
+extern BSXCart  bsxcart;
+extern BSXFlash bsxflash;
@@ -0,0 +1,137 @@
+#ifdef BSX_CPP
+
+void BSXBase::init() {
+}
+
+void BSXBase::enable() {
+  for(uint16 i = 0x2188; i <= 0x219f; i++) memory::mmio.map(i, *this);
+}
+
+void BSXBase::power() {
+  reset();
+}
+
+void BSXBase::reset() {
+  memset(&regs, 0x00, sizeof regs);
+}
+
+uint8 BSXBase::mmio_read(uint addr) {
+  addr &= 0xffff;
+
+  switch(addr) {
+    case 0x2188: return regs.r2188;
+    case 0x2189: return regs.r2189;
+    case 0x218a: return regs.r218a;
+    case 0x218c: return regs.r218c;
+    case 0x218e: return regs.r218e;
+    case 0x218f: return regs.r218f;
+    case 0x2190: return regs.r2190;
+
+    case 0x2192: {
+    uint counter = regs.r2192_counter++;
+      if(regs.r2192_counter >= 18) regs.r2192_counter = 0;
+
+      if(counter == 0) {
+      time_t rawtime;
+        time(&rawtime);
+      tm *t = localtime(&rawtime);
+
+        regs.r2192_hour   = t->tm_hour;
+        regs.r2192_minute = t->tm_min;
+        regs.r2192_second = t->tm_sec;
+      }
+
+      switch(counter) {
+        case  0: return 0x00; //???
+        case  1: return 0x00; //???
+        case  2: return 0x00; //???
+        case  3: return 0x00; //???
+        case  4: return 0x00; //???
+        case  5: return 0x01;
+        case  6: return 0x01;
+        case  7: return 0x00;
+        case  8: return 0x00;
+        case  9: return 0x00;
+        case 10: return regs.r2192_second;
+        case 11: return regs.r2192_minute;
+        case 12: return regs.r2192_hour;
+        case 13: return 0x00; //???
+        case 14: return 0x00; //???
+        case 15: return 0x00; //???
+        case 16: return 0x00; //???
+        case 17: return 0x00; //???
+      }
+    } break;
+
+    case 0x2193: return regs.r2193 & ~0x0c;
+    case 0x2194: return regs.r2194;
+    case 0x2196: return regs.r2196;
+    case 0x2197: return regs.r2197;
+    case 0x2199: return regs.r2199;
+  }
+
+  return cpu.regs.mdr;
+}
+
+void BSXBase::mmio_write(uint addr, uint8 data) {
+  addr &= 0xffff;
+
+  switch(addr) {
+    case 0x2188: {
+      regs.r2188 = data;
+    } break;
+
+    case 0x2189: {
+      regs.r2189 = data;
+    } break;
+
+    case 0x218a: {
+      regs.r218a = data;
+    } break;
+
+    case 0x218b: {
+      regs.r218b = data;
+    } break;
+
+    case 0x218c: {
+      regs.r218c = data;
+    } break;
+
+    case 0x218e: {
+      regs.r218e = data;
+    } break;
+
+    case 0x218f: {
+      regs.r218e >>= 1;
+      regs.r218e = regs.r218f - regs.r218e;
+      regs.r218f >>= 1;
+    } break;
+
+    case 0x2191: {
+      regs.r2191 = data;
+      regs.r2192_counter = 0;
+    } break;
+
+    case 0x2192: {
+      regs.r2190 = 0x80;
+    } break;
+
+    case 0x2193: {
+      regs.r2193 = data;
+    } break;
+
+    case 0x2194: {
+      regs.r2194 = data;
+    } break;
+
+    case 0x2197: {
+      regs.r2197 = data;
+    } break;
+
+    case 0x2199: {
+      regs.r2199 = data;
+    } break;
+  }
+}
+
+#endif //ifdef BSX_CPP
@@ -0,0 +1,99 @@
+#ifdef BSX_CPP
+
+void BSXCart::init() {
+}
+
+void BSXCart::enable() {
+  for(uint16 i = 0x5000; i <= 0x5fff; i++) memory::mmio.map(i, *this);
+}
+
+void BSXCart::power() {
+  reset();
+}
+
+void BSXCart::reset() {
+  for(uint i = 0; i < 16; i++) regs.r[i] = 0x00;
+  regs.r[0x07] = 0x80;
+  regs.r[0x08] = 0x80;
+
+  update_memory_map();
+}
+
+void BSXCart::update_memory_map() {
+  Memory &cart = (regs.r[0x01] & 0x80) == 0x00 ? (Memory&)bsxflash : (Memory&)psram;
+
+  if((regs.r[0x02] & 0x80) == 0x00) { //LoROM mapping
+    bus.map(Bus::MapLinear, 0x00, 0x7d, 0x8000, 0xffff, cart);
+    bus.map(Bus::MapLinear, 0x80, 0xff, 0x8000, 0xffff, cart);
+  } else { //HiROM mapping
+    bus.map(Bus::MapShadow, 0x00, 0x3f, 0x8000, 0xffff, cart);
+    bus.map(Bus::MapLinear, 0x40, 0x7d, 0x0000, 0xffff, cart);
+    bus.map(Bus::MapShadow, 0x80, 0xbf, 0x8000, 0xffff, cart);
+    bus.map(Bus::MapLinear, 0xc0, 0xff, 0x0000, 0xffff, cart);
+  }
+
+  if(regs.r[0x03] & 0x80) {
+    bus.map(Bus::MapLinear, 0x60, 0x6f, 0x0000, 0xffff, psram);
+  //bus.map(Bus::MapLinear, 0x70, 0x77, 0x0000, 0xffff, psram);
+  }
+
+  if((regs.r[0x05] & 0x80) == 0x00) {
+    bus.map(Bus::MapLinear, 0x40, 0x4f, 0x0000, 0xffff, psram);
+  }
+
+  if((regs.r[0x06] & 0x80) == 0x00) {
+    bus.map(Bus::MapLinear, 0x50, 0x5f, 0x0000, 0xffff, psram);
+  }
+
+  if(regs.r[0x07] & 0x80) {
+    bus.map(Bus::MapLinear, 0x00, 0x1f, 0x8000, 0xffff, memory::cartrom);
+  }
+
+  if(regs.r[0x08] & 0x80) {
+    bus.map(Bus::MapLinear, 0x80, 0x9f, 0x8000, 0xffff, memory::cartrom);
+  }
+
+  bus.map(Bus::MapShadow, 0x20, 0x3f, 0x6000, 0x7fff, psram);
+  bus.map(Bus::MapLinear, 0x70, 0x77, 0x0000, 0xffff, psram);
+}
+
+uint8 BSXCart::mmio_read(uint addr) {
+  if((addr & 0xf0ffff) == 0x005000) { //$[00-0f]:5000 MMIO
+    uint8 n = (addr >> 16) & 15;
+    return regs.r[n];
+  }
+
+  if((addr & 0xf8f000) == 0x105000) { //$[10-17]:[5000-5fff] SRAM
+    return sram.read(((addr >> 16) & 7) * 0x1000 + (addr & 0xfff));
+  }
+
+  return 0x00;
+}
+
+void BSXCart::mmio_write(uint addr, uint8 data) {
+  if((addr & 0xf0ffff) == 0x005000) { //$[00-0f]:5000 MMIO
+    uint8 n = (addr >> 16) & 15;
+    regs.r[n] = data;
+    if(n == 0x0e && data & 0x80) update_memory_map();
+    return;
+  }
+
+  if((addr & 0xf8f000) == 0x105000) { //$[10-17]:[5000-5fff] SRAM
+    return sram.write(((addr >> 16) & 7) * 0x1000 + (addr & 0xfff), data);
+  }
+}
+
+BSXCart::BSXCart() {
+  sram_data  = new uint8_t[ 32 * 1024];
+  psram_data = new uint8_t[512 * 1024];
+
+  sram.map (sram_data,   32 * 1024);
+  psram.map(psram_data, 512 * 1024);
+}
+
+BSXCart::~BSXCart() {
+  delete[] sram_data;
+  delete[] psram_data;
+}
+
+#endif //ifdef BSX_CPP
@@ -0,0 +1,113 @@
+#ifdef BSX_CPP
+
+void BSXFlash::init() {}
+void BSXFlash::enable() {}
+
+void BSXFlash::power() {
+  reset();
+}
+
+void BSXFlash::reset() {
+  regs.command   = 0;
+  regs.write_old = 0x00;
+  regs.write_new = 0x00;
+
+  regs.flash_enable = false;
+  regs.read_enable  = false;
+  regs.write_enable = false;
+}
+
+uint BSXFlash::size() {
+  return memory::bscram.size();
+}
+
+uint8 BSXFlash::read(uint addr) {
+  if(addr == 0x0002) {
+    if(regs.flash_enable) return 0x80;
+  }
+
+  if(addr == 0x5555) {
+    if(regs.flash_enable) return 0x80;
+  }
+
+  if(regs.read_enable && addr >= 0xff00 && addr <= 0xff13) {
+  //read flash cartridge vendor information
+    switch(addr - 0xff00) {
+      case 0x00: return 0x4d;
+      case 0x01: return 0x00;
+      case 0x02: return 0x50;
+      case 0x03: return 0x00;
+      case 0x04: return 0x00;
+      case 0x05: return 0x00;
+      case 0x06: return 0x2a; //0x2a = 8mbit, 0x2b = 16mbit (not known to exist, though BIOS recognizes ID)
+      case 0x07: return 0x00;
+      default:   return 0x00;
+    }
+  }
+
+  return memory::bscram.read(addr);
+}
+
+void BSXFlash::write(uint addr, uint8 data) {
+//there exist both read-only and read-write BS-X flash cartridges ...
+//unfortunately, the vendor info is not stored inside memory dumps
+//of BS-X flashcarts, so it is impossible to determine whether a
+//given flashcart is writeable.
+//however, it has been observed that LoROM-mapped BS-X carts always
+//use read-write flashcarts, and HiROM-mapped BS-X carts always use
+//read-only flashcarts.
+//below is an unfortunately necessary workaround to this problem.
+  if(cartridge.mapper() == Cartridge::BSCHiROM) return;
+
+  if((addr & 0xff0000) == 0) {
+    regs.write_old = regs.write_new;
+    regs.write_new = data;
+
+    if(regs.write_enable && regs.write_old == regs.write_new) {
+      return memory::bscram.write(addr, data);
+    }
+  } else {
+    if(regs.write_enable) {
+      return memory::bscram.write(addr, data);
+    }
+  }
+
+  if(addr == 0x0000) {
+    regs.command <<= 8;
+    regs.command  |= data;
+
+    if((regs.command & 0xffff) == 0x38d0) {
+      regs.flash_enable = true;
+      regs.read_enable  = true;
+    }
+  }
+
+  if(addr == 0x2aaa) {
+    regs.command <<= 8;
+    regs.command  |= data;
+  }
+
+  if(addr == 0x5555) {
+    regs.command <<= 8;
+    regs.command  |= data;
+
+    if((regs.command & 0xffffff) == 0xaa5570) {
+      regs.write_enable = false;
+    }
+
+    if((regs.command & 0xffffff) == 0xaa55a0) {
+      regs.write_old = 0x00;
+      regs.write_new = 0x00;
+      regs.flash_enable = true;
+      regs.write_enable = true;
+    }
+
+    if((regs.command & 0xffffff) == 0xaa55f0) {
+      regs.flash_enable = false;
+      regs.read_enable  = false;
+      regs.write_enable = false;
+    }
+  }
+}
+
+#endif //ifdef BSX_CPP
@@ -0,0 +1,11 @@
+#include "bsx/bsx.h"
+#include "srtc/srtc.h"
+#include "sdd1/sdd1.h"
+#include "spc7110/spc7110.h"
+#include "cx4/cx4.h"
+#include "dsp1/dsp1.h"
+#include "dsp2/dsp2.h"
+#include "dsp3/dsp3.h"
+#include "dsp4/dsp4.h"
+#include "obc1/obc1.h"
+#include "st010/st010.h"
@@ -5,31 +5,30 @@
  Portions (c) anomie, Overload, zsKnight, Nach, byuu
 */

-#include "../../base.h"
+#include "../../base.h"
+#define CX4_CPP

-C4 *c4;
+#include "cx4data.cpp"
+#include "cx4fn.cpp"
+#include "cx4oam.cpp"
+#include "cx4ops.cpp"

-#include "c4data.cpp"
-#include "c4fn.cpp"
-#include "c4oam.cpp"
-#include "c4ops.cpp"
+void Cx4::init() {}
+void Cx4::enable() {}

-void C4::init() {}
-void C4::enable() {}
-
-uint32 C4::ldr(uint8 r) {
+uint32 Cx4::ldr(uint8 r) {
 uint16 addr = 0x0080 + (r * 3);
  return (reg[addr]) | (reg[addr + 1] << 8) | (reg[addr + 2] << 16);
 }

-void C4::str(uint8 r, uint32 data) {
+void Cx4::str(uint8 r, uint32 data) {
 uint16 addr = 0x0080 + (r * 3);
  reg[addr    ] = (data);
  reg[addr + 1] = (data >> 8);
  reg[addr + 2] = (data >> 16);
 }

-void C4::mul(uint32 x, uint32 y, uint32 &rl, uint32 &rh) {
+void Cx4::mul(uint32 x, uint32 y, uint32 &rl, uint32 &rh) {
 int64 rx = x & 0xffffff;
 int64 ry = y & 0xffffff;
  if(rx & 0x800000)rx |= ~0x7fffff;
@@ -41,7 +40,7 @@ int64 ry = y & 0xffffff;
  rh = (rx >> 24) & 0xffffff;
 }

-uint32 C4::sin(uint32 rx) {
+uint32 Cx4::sin(uint32 rx) {
  r0 = rx & 0x1ff;
  if(r0 & 0x100)r0 ^= 0x1ff;
  if(r0 & 0x080)r0 ^= 0x0ff;
@@ -52,13 +51,13 @@ uint32 C4::sin(uint32 rx) {
  }
 }

-uint32 C4::cos(uint32 rx) {
+uint32 Cx4::cos(uint32 rx) {
  return sin(rx + 0x080);
 }

-void C4::immediate_reg(uint32 start) {
+void Cx4::immediate_reg(uint32 start) {
  r0 = ldr(0);
-  for(uint32 i=start;i<48;i++) {
+  for(uint32 i = start; i < 48; i++) {
    if((r0 & 0x0fff) < 0x0c00) {
      ram[r0 & 0x0fff] = immediate_data[i];
    }
@@ -67,7 +66,7 @@ void C4::immediate_reg(uint32 start) {
  str(0, r0);
 }

-void C4::transfer_data() {
+void Cx4::transfer_data() {
 uint32 src;
 uint16 dest, count;
  src   = (reg[0x40]) | (reg[0x41] << 8) | (reg[0x42] << 16);
@@ -75,11 +74,11 @@ uint16 dest, count;
  dest  = (reg[0x45]) | (reg[0x46] << 8);

  for(uint32 i=0;i<count;i++) {
-    write(dest++, r_mem->read(src++));
+    write(dest++, bus.read(src++));
  }
 }

-void C4::write(uint16 addr, uint8 data) {
+void Cx4::write(uint addr, uint8 data) {
  addr &= 0x1fff;

  if(addr < 0x0c00) {
@@ -111,57 +110,57 @@ void C4::write(uint16 addr, uint8 data) {
    }

    switch(data) {
-    case 0x00:op00();break;
-    case 0x01:op01();break;
-    case 0x05:op05();break;
-    case 0x0d:op0d();break;
-    case 0x10:op10();break;
-    case 0x13:op13();break;
-    case 0x15:op15();break;
-    case 0x1f:op1f();break;
-    case 0x22:op22();break;
-    case 0x25:op25();break;
-    case 0x2d:op2d();break;
-    case 0x40:op40();break;
-    case 0x54:op54();break;
-    case 0x5c:op5c();break;
-    case 0x5e:op5e();break;
-    case 0x60:op60();break;
-    case 0x62:op62();break;
-    case 0x64:op64();break;
-    case 0x66:op66();break;
-    case 0x68:op68();break;
-    case 0x6a:op6a();break;
-    case 0x6c:op6c();break;
-    case 0x6e:op6e();break;
-    case 0x70:op70();break;
-    case 0x72:op72();break;
-    case 0x74:op74();break;
-    case 0x76:op76();break;
-    case 0x78:op78();break;
-    case 0x7a:op7a();break;
-    case 0x7c:op7c();break;
-    case 0x89:op89();break;
+      case 0x00: op00(); break;
+      case 0x01: op01(); break;
+      case 0x05: op05(); break;
+      case 0x0d: op0d(); break;
+      case 0x10: op10(); break;
+      case 0x13: op13(); break;
+      case 0x15: op15(); break;
+      case 0x1f: op1f(); break;
+      case 0x22: op22(); break;
+      case 0x25: op25(); break;
+      case 0x2d: op2d(); break;
+      case 0x40: op40(); break;
+      case 0x54: op54(); break;
+      case 0x5c: op5c(); break;
+      case 0x5e: op5e(); break;
+      case 0x60: op60(); break;
+      case 0x62: op62(); break;
+      case 0x64: op64(); break;
+      case 0x66: op66(); break;
+      case 0x68: op68(); break;
+      case 0x6a: op6a(); break;
+      case 0x6c: op6c(); break;
+      case 0x6e: op6e(); break;
+      case 0x70: op70(); break;
+      case 0x72: op72(); break;
+      case 0x74: op74(); break;
+      case 0x76: op76(); break;
+      case 0x78: op78(); break;
+      case 0x7a: op7a(); break;
+      case 0x7c: op7c(); break;
+      case 0x89: op89(); break;
    }
  }
 }

-void C4::writeb(uint16 addr, uint8 data) {
+void Cx4::writeb(uint16 addr, uint8 data) {
  write(addr,     data);
 }

-void C4::writew(uint16 addr, uint16 data) {
+void Cx4::writew(uint16 addr, uint16 data) {
  write(addr,     data);
  write(addr + 1, data >> 8);
 }

-void C4::writel(uint16 addr, uint32 data) {
+void Cx4::writel(uint16 addr, uint32 data) {
  write(addr,     data);
  write(addr + 1, data >>  8);
  write(addr + 2, data >> 16);
 }

-uint8 C4::read(uint16 addr) {
+uint8 Cx4::read(uint addr) {
  addr &= 0x1fff;

  if(addr < 0x0c00) {
@@ -172,28 +171,26 @@ uint8 C4::read(uint16 addr) {
    return reg[addr & 0xff];
  }

-  return r_cpu->regs.mdr;
+  return cpu.regs.mdr;
 }

-uint8 C4::readb(uint16 addr) {
+uint8 Cx4::readb(uint16 addr) {
  return read(addr);
 }

-uint16 C4::readw(uint16 addr) {
+uint16 Cx4::readw(uint16 addr) {
  return read(addr) | (read(addr + 1) << 8);
 }

-uint32 C4::readl(uint16 addr) {
+uint32 Cx4::readl(uint16 addr) {
  return read(addr) | (read(addr + 1) << 8) + (read(addr + 2) << 16);
 }

-void C4::power() {
+void Cx4::power() {
  reset();
 }

-void C4::reset() {
+void Cx4::reset() {
  memset(ram, 0, 0x0c00);
  memset(reg, 0, 0x0100);
 }
-
-C4::C4() {}
@@ -1,29 +1,29 @@
-class C4 {
+class Cx4 : public Memory {
 private:
-uint8  ram[0x0c00];
-uint8  reg[0x0100];
-uint32 r0, r1, r2,  r3,  r4,  r5,  r6,  r7,
-       r8, r9, r10, r11, r12, r13, r14, r15;
+  uint8  ram[0x0c00];
+  uint8  reg[0x0100];
+  uint32 r0, r1, r2,  r3,  r4,  r5,  r6,  r7,
+         r8, r9, r10, r11, r12, r13, r14, r15;

-static const uint8  immediate_data[48];
-static const uint16 wave_data[40];
-static const uint32 sin_table[256];
+  static const uint8  immediate_data[48];
+  static const uint16 wave_data[40];
+  static const uint32 sin_table[256];

-static const int16 SinTable[512];
-static const int16 CosTable[512];
+  static const int16 SinTable[512];
+  static const int16 CosTable[512];

-int16 C4WFXVal, C4WFYVal, C4WFZVal, C4WFX2Val, C4WFY2Val, C4WFDist, C4WFScale;
-int16 C41FXVal, C41FYVal, C41FAngleRes, C41FDist, C41FDistVal;
+  int16 C4WFXVal, C4WFYVal, C4WFZVal, C4WFX2Val, C4WFY2Val, C4WFDist, C4WFScale;
+  int16 C41FXVal, C41FYVal, C41FAngleRes, C41FDist, C41FDistVal;

-double tanval;
-double c4x,c4y,c4z, c4x2,c4y2,c4z2;
+  double tanval;
+  double c4x,c4y,c4z, c4x2,c4y2,c4z2;

-void C4TransfWireFrame();
-void C4TransfWireFrame2();
-void C4CalcWireFrame();
-void C4DrawLine(int32 X1, int32 Y1, int16 Z1, int32 X2, int32 Y2, int16 Z2, uint8 Color);
-void C4DrawWireFrame();
-void C4DoScaleRotate(int row_padding);
+  void C4TransfWireFrame();
+  void C4TransfWireFrame2();
+  void C4CalcWireFrame();
+  void C4DrawLine(int32 X1, int32 Y1, int16 Z1, int32 X2, int32 Y2, int16 Z2, uint8 Color);
+  void C4DrawWireFrame();
+  void C4DoScaleRotate(int row_padding);

 public:
  uint32 ldr(uint8 r);
@@ -75,22 +75,23 @@ public:
  void   op7c();
  void   op89();

+  uint8  readb(uint16 addr);
+  uint16 readw(uint16 addr);
+  uint32 readl(uint16 addr);
+
+  void   writeb(uint16 addr, uint8 data);
+  void   writew(uint16 addr, uint16 data);
+  void   writel(uint16 addr, uint32 data);
+
+//
+
  void   init();
  void   enable();
  void   power();
  void   reset();

-  void   write (uint16 addr, uint8 data);
-  void   writeb(uint16 addr, uint8 data);
-  void   writew(uint16 addr, uint16 data);
-  void   writel(uint16 addr, uint32 data);
-
-  uint8  read (uint16 addr);
-  uint8  readb(uint16 addr);
-  uint16 readw(uint16 addr);
-  uint32 readl(uint16 addr);
-
-  C4();
+  uint8  read (uint addr);
+  void   write(uint addr, uint8 data);
 };

-extern C4 *c4;
+extern Cx4 cx4;
@@ -1,11 +1,13 @@
-const uint8 C4::immediate_data[48] = {
+#ifdef CX4_CPP
+
+const uint8 Cx4::immediate_data[48] = {
  0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x00, 0xff, 0x00, 0x00, 0x00, 0xff,
  0xff, 0xff, 0x00, 0x00, 0xff, 0xff, 0x00, 0x00, 0x80, 0xff, 0xff, 0x7f,
  0x00, 0x80, 0x00, 0xff, 0x7f, 0x00, 0xff, 0x7f, 0xff, 0x7f, 0xff, 0xff,
  0x00, 0x00, 0x01, 0xff, 0xff, 0xfe, 0x00, 0x01, 0x00, 0xff, 0xfe, 0x00
 };

-const uint16 C4::wave_data[40] = {
+const uint16 Cx4::wave_data[40] = {
  0x0000, 0x0002, 0x0004, 0x0006, 0x0008, 0x000a, 0x000c, 0x000e,
  0x0200, 0x0202, 0x0204, 0x0206, 0x0208, 0x020a, 0x020c, 0x020e,
  0x0400, 0x0402, 0x0404, 0x0406, 0x0408, 0x040a, 0x040c, 0x040e,
@@ -13,7 +15,7 @@ const uint16 C4::wave_data[40] = {
  0x0800, 0x0802, 0x0804, 0x0806, 0x0808, 0x080a, 0x080c, 0x080e
 };

-const uint32 C4::sin_table[256] = {
+const uint32 Cx4::sin_table[256] = {
  0x000000, 0x000324, 0x000648, 0x00096c, 0x000c8f, 0x000fb2, 0x0012d5, 0x0015f6,
  0x001917, 0x001c37, 0x001f56, 0x002273, 0x002590, 0x0028aa, 0x002bc4, 0x002edb,
  0x0031f1, 0x003505, 0x003817, 0x003b26, 0x003e33, 0x00413e, 0x004447, 0x00474d,
@@ -48,7 +50,7 @@ const uint32 C4::sin_table[256] = {
  0xff013b, 0xff00f1, 0xff00b1, 0xff007b, 0xff004e, 0xff002c, 0xff0013, 0xff0004
 };

-const int16 C4::SinTable[512] = {
+const int16 Cx4::SinTable[512] = {
       0,    402,    804,   1206,   1607,   2009,   2410,   2811,
    3211,   3611,   4011,   4409,   4808,   5205,   5602,   5997,
    6392,   6786,   7179,   7571,   7961,   8351,   8739,   9126,
@@ -115,7 +117,7 @@ const int16 C4::SinTable[512] = {
   -3211,  -2811,  -2410,  -2009,  -1607,  -1206,   -804,   -402
 };

-const int16 C4::CosTable[512] = {
+const int16 Cx4::CosTable[512] = {
   32767,  32765,  32758,  32745,  32728,  32706,  32679,  32647,
   32610,  32568,  32521,  32469,  32413,  32351,  32285,  32214,
   32138,  32057,  31971,  31881,  31785,  31685,  31581,  31471,
@@ -181,3 +183,5 @@ const int16 C4::CosTable[512] = {
   32138,  32214,  32285,  32351,  32413,  32469,  32521,  32568,
   32610,  32647,  32679,  32706,  32728,  32745,  32758,  32765
 };
+
+#endif //ifdef CX4_CPP
@@ -1,3 +1,5 @@
+#ifdef CX4_CPP
+
 #include <math.h>
 #define Tan(a) (CosTable[a] ? ((((int32)SinTable[a]) << 16) / CosTable[a]) : 0x80000000)
 #define sar(b, n) ((b) >> (n))
@@ -7,7 +9,7 @@
 #define PI 3.1415926535897932384626433832795

 //Wireframe Helpers
-void C4::C4TransfWireFrame() {
+void Cx4::C4TransfWireFrame() {
  c4x = (double)C4WFXVal;
  c4y = (double)C4WFYVal;
  c4z = (double)C4WFZVal - 0x95;
@@ -32,7 +34,7 @@ void C4::C4TransfWireFrame() {
  C4WFYVal = (int16)(c4y * C4WFScale / (0x90 * (c4z + 0x95)) * 0x95);
 }

-void C4::C4CalcWireFrame() {
+void Cx4::C4CalcWireFrame() {
  C4WFXVal = C4WFX2Val - C4WFXVal;
  C4WFYVal = C4WFY2Val - C4WFYVal;

@@ -49,7 +51,7 @@ void C4::C4CalcWireFrame() {
  }
 }

-void C4::C4TransfWireFrame2() {
+void Cx4::C4TransfWireFrame2() {
  c4x = (double)C4WFXVal;
  c4y = (double)C4WFYVal;
  c4z = (double)C4WFZVal;
@@ -74,34 +76,34 @@ void C4::C4TransfWireFrame2() {
  C4WFYVal = (int16)(c4y * C4WFScale / 0x100);
 }

-void C4::C4DrawWireFrame() {
+void Cx4::C4DrawWireFrame() {
 uint32 line = readl(0x1f80);
 uint32 point1, point2;
 int16 X1, Y1, Z1;
 int16 X2, Y2, Z2;
 uint8 Color;
  for(int32 i = ram[0x0295]; i > 0; i--, line += 5) {
-    if(r_mem->read(line) == 0xff && r_mem->read(line + 1) == 0xff) {
+    if(bus.read(line) == 0xff && bus.read(line + 1) == 0xff) {
    int32 tmp = line - 5;
-      while(r_mem->read(tmp + 2) == 0xff && r_mem->read(tmp + 3) == 0xff && (tmp + 2) >= 0) { tmp -= 5; }
-      point1 = (read(0x1f82) << 16) | (r_mem->read(tmp + 2) << 8) | r_mem->read(tmp + 3);
+      while(bus.read(tmp + 2) == 0xff && bus.read(tmp + 3) == 0xff && (tmp + 2) >= 0) { tmp -= 5; }
+      point1 = (read(0x1f82) << 16) | (bus.read(tmp + 2) << 8) | bus.read(tmp + 3);
    } else {
-      point1 = (read(0x1f82) << 16) | (r_mem->read(line) << 8) | r_mem->read(line + 1);
+      point1 = (read(0x1f82) << 16) | (bus.read(line) << 8) | bus.read(line + 1);
    }
-    point2 = (read(0x1f82) << 16) | (r_mem->read(line + 2) << 8) | r_mem->read(line + 3);
+    point2 = (read(0x1f82) << 16) | (bus.read(line + 2) << 8) | bus.read(line + 3);

-    X1=(r_mem->read(point1 + 0) << 8) | r_mem->read(point1 + 1);
-    Y1=(r_mem->read(point1 + 2) << 8) | r_mem->read(point1 + 3);
-    Z1=(r_mem->read(point1 + 4) << 8) | r_mem->read(point1 + 5);
-    X2=(r_mem->read(point2 + 0) << 8) | r_mem->read(point2 + 1);
-    Y2=(r_mem->read(point2 + 2) << 8) | r_mem->read(point2 + 3);
-    Z2=(r_mem->read(point2 + 4) << 8) | r_mem->read(point2 + 5);
-    Color = r_mem->read(line + 4);
+    X1=(bus.read(point1 + 0) << 8) | bus.read(point1 + 1);
+    Y1=(bus.read(point1 + 2) << 8) | bus.read(point1 + 3);
+    Z1=(bus.read(point1 + 4) << 8) | bus.read(point1 + 5);
+    X2=(bus.read(point2 + 0) << 8) | bus.read(point2 + 1);
+    Y2=(bus.read(point2 + 2) << 8) | bus.read(point2 + 3);
+    Z2=(bus.read(point2 + 4) << 8) | bus.read(point2 + 5);
+    Color = bus.read(line + 4);
    C4DrawLine(X1, Y1, Z1, X2, Y2, Z2, Color);
  }
 }

-void C4::C4DrawLine(int32 X1, int32 Y1, int16 Z1, int32 X2, int32 Y2, int16 Z2, uint8 Color) {
+void Cx4::C4DrawLine(int32 X1, int32 Y1, int16 Z1, int32 X2, int32 Y2, int16 Z2, uint8 Color) {
 //Transform coordinates
  C4WFXVal  = (int16)X1;
  C4WFYVal  = (int16)Y1;
@@ -145,7 +147,7 @@ void C4::C4DrawLine(int32 X1, int32 Y1, int16 Z1, int32 X2, int32 Y2, int16 Z2,
  }
 }

-void C4::C4DoScaleRotate(int row_padding) {
+void Cx4::C4DoScaleRotate(int row_padding) {
 int16 A, B, C, D;

 //Calculate matrix
@@ -240,3 +242,5 @@ uint8 bit    = 0x80;
    LineY += D;
  }
 }
+
+#endif //ifdef CX4_CPP
@@ -1,5 +1,7 @@
+#ifdef CX4_CPP
+
 //Build OAM
-void C4::op00_00() {
+void Cx4::op00_00() {
 uint32 oamptr = ram[0x626] << 2;
  for(int32 i = 0x1fd; i > oamptr && i >= 0; i -= 4) {
  //clear oam-to-be
@@ -27,28 +29,28 @@ uint32 srcptr = 0x220;
    sprattr = ram[srcptr + 4] | ram[srcptr + 6];

  uint32 spraddr = readl(srcptr + 7);
-    if(r_mem->read(spraddr)) {
+    if(bus.read(spraddr)) {
    int16 x, y;
-      for(int sprcnt = r_mem->read(spraddr++); sprcnt > 0 && sprcount > 0; sprcnt--, spraddr += 4) {
-        x = (int8)r_mem->read(spraddr + 1);
+      for(int sprcnt = bus.read(spraddr++); sprcnt > 0 && sprcount > 0; sprcnt--, spraddr += 4) {
+        x = (int8)bus.read(spraddr + 1);
        if(sprattr & 0x40) {
-          x = -x - ((r_mem->read(spraddr) & 0x20) ? 16 : 8);
+          x = -x - ((bus.read(spraddr) & 0x20) ? 16 : 8);
        }
        x += sprx;
        if(x >= -16 && x <= 272) {
-          y = (int8)r_mem->read(spraddr + 2);
+          y = (int8)bus.read(spraddr + 2);
          if(sprattr & 0x80) {
-            y = -y - ((r_mem->read(spraddr) & 0x20) ? 16 : 8);
+            y = -y - ((bus.read(spraddr) & 0x20) ? 16 : 8);
          }
          y += spry;
          if(y >= -16 && y <= 224) {
            ram[oamptr    ] = (uint8)x;
            ram[oamptr + 1] = (uint8)y;
-            ram[oamptr + 2] = sprname + r_mem->read(spraddr + 3);
-            ram[oamptr + 3] = sprattr ^ (r_mem->read(spraddr) & 0xc0);
+            ram[oamptr + 2] = sprname + bus.read(spraddr + 3);
+            ram[oamptr + 3] = sprattr ^ (bus.read(spraddr) & 0xc0);
            ram[oamptr2] &= ~(3 << offset);
            if(x & 0x100)ram[oamptr2] |= 1 << offset;
-            if(r_mem->read(spraddr) & 0x20)ram[oamptr2] |= 2 << offset;
+            if(bus.read(spraddr) & 0x20)ram[oamptr2] |= 2 << offset;
            oamptr += 4;
            sprcount--;
            offset = (offset + 2) & 6;
@@ -73,12 +75,12 @@ uint32 srcptr = 0x220;
 }

 //Scale and Rotate
-void C4::op00_03() {
+void Cx4::op00_03() {
  C4DoScaleRotate(0);
 }

 //Transform Lines
-void C4::op00_05() {
+void Cx4::op00_05() {
  C4WFX2Val = read(0x1f83);
  C4WFY2Val = read(0x1f86);
  C4WFDist  = read(0x1f89);
@@ -119,17 +121,17 @@ uint32 ptr2 = 0;
 }

 //Scale and Rotate
-void C4::op00_07() {
+void Cx4::op00_07() {
  C4DoScaleRotate(64);
 }

 //Draw Wireframe
-void C4::op00_08() {
+void Cx4::op00_08() {
  C4DrawWireFrame();
 }

 //Disintegrate
-void C4::op00_0b() {
+void Cx4::op00_0b() {
 uint8  width, height;
 uint32 startx, starty;
 uint32 srcptr;
@@ -169,7 +171,7 @@ int32  i, j;
 }

 //Bitplane Wave
-void C4::op00_0c() {
+void Cx4::op00_0c() {
 uint32 destptr = 0;
 uint32 waveptr = read(0x1f83);
 uint16 mask1   = 0xc0c0;
@@ -217,3 +219,5 @@ uint16 mask2   = 0x3f3f;
    destptr += 16;
  }
 }
+
+#endif //ifdef CX4_CPP
@@ -1,5 +1,7 @@
+#ifdef CX4_CPP
+
 //Sprite Functions
-void C4::op00() {
+void Cx4::op00() {
  switch(reg[0x4d]) {
  case 0x00:op00_00();break;
  case 0x03:op00_03();break;
@@ -12,13 +14,13 @@ void C4::op00() {
 }

 //Draw Wireframe
-void C4::op01() {
+void Cx4::op01() {
  memset(ram + 0x300, 0, 2304);
  C4DrawWireFrame();
 }

 //Propulsion
-void C4::op05() {
+void Cx4::op05() {
 int32 temp = 0x10000;
  if(readw(0x1f83)) {
    temp = sar((temp / readw(0x1f83)) * readw(0x1f81), 8);
@@ -27,7 +29,7 @@ int32 temp = 0x10000;
 }

 //Set Vector length
-void C4::op0d() {
+void Cx4::op0d() {
  C41FXVal    = readw(0x1f80);
  C41FYVal    = readw(0x1f83);
  C41FDistVal = readw(0x1f86);
@@ -40,7 +42,7 @@ void C4::op0d() {
 }

 //Triangle
-void C4::op10() {
+void Cx4::op10() {
  r0 = ldr(0);
  r1 = ldr(1);

@@ -64,7 +66,7 @@ void C4::op10() {
 }

 //Triangle
-void C4::op13() {
+void Cx4::op13() {
  r0 = ldr(0);
  r1 = ldr(1);

@@ -87,7 +89,7 @@ void C4::op13() {
 }

 //Pythagorean
-void C4::op15() {
+void Cx4::op15() {
  C41FXVal = readw(0x1f80);
  C41FYVal = readw(0x1f83);
  C41FDist = (int16)sqrt((double)C41FXVal * (double)C41FXVal + (double)C41FYVal * (double)C41FYVal);
@@ -95,7 +97,7 @@ void C4::op15() {
 }

 //Calculate distance
-void C4::op1f() {
+void Cx4::op1f() {
  C41FXVal = readw(0x1f80);
  C41FYVal = readw(0x1f83);
  if(!C41FXVal) {
@@ -113,7 +115,7 @@ void C4::op1f() {
 }

 //Trapezoid
-void C4::op22() {
+void Cx4::op22() {
 int16 angle1 = readw(0x1f8c) & 0x1ff;
 int16 angle2 = readw(0x1f8f) & 0x1ff;
 int32 tan1 = Tan(angle1);
@@ -152,7 +154,7 @@ int16 left, right;
 }

 //Multiply
-void C4::op25() {
+void Cx4::op25() {
  r0 = ldr(0);
  r1 = ldr(1);
  mul(r0, r1, r0, r1);
@@ -161,7 +163,7 @@ void C4::op25() {
 }

 //Transform Coords
-void C4::op2d() {
+void Cx4::op2d() {
  C4WFXVal  = readw(0x1f81);
  C4WFYVal  = readw(0x1f84);
  C4WFZVal  = readw(0x1f87);
@@ -175,7 +177,7 @@ void C4::op2d() {
 }

 //Sum
-void C4::op40() {
+void Cx4::op40() {
  r0 = 0;
  for(uint32 i=0;i<0x800;i++) {
    r0 += ram[i];
@@ -184,7 +186,7 @@ void C4::op40() {
 }

 //Square
-void C4::op54() {
+void Cx4::op54() {
  r0 = ldr(0);
  mul(r0, r0, r1, r2);
  str(1, r1);
@@ -192,31 +194,33 @@ void C4::op54() {
 }

 //Immediate Register
-void C4::op5c() {
+void Cx4::op5c() {
  str(0, 0x000000);
  immediate_reg(0);
 }

 //Immediate Register (Multiple)
-void C4::op5e() { immediate_reg( 0); }
-void C4::op60() { immediate_reg( 3); }
-void C4::op62() { immediate_reg( 6); }
-void C4::op64() { immediate_reg( 9); }
-void C4::op66() { immediate_reg(12); }
-void C4::op68() { immediate_reg(15); }
-void C4::op6a() { immediate_reg(18); }
-void C4::op6c() { immediate_reg(21); }
-void C4::op6e() { immediate_reg(24); }
-void C4::op70() { immediate_reg(27); }
-void C4::op72() { immediate_reg(30); }
-void C4::op74() { immediate_reg(33); }
-void C4::op76() { immediate_reg(36); }
-void C4::op78() { immediate_reg(39); }
-void C4::op7a() { immediate_reg(42); }
-void C4::op7c() { immediate_reg(45); }
+void Cx4::op5e() { immediate_reg( 0); }
+void Cx4::op60() { immediate_reg( 3); }
+void Cx4::op62() { immediate_reg( 6); }
+void Cx4::op64() { immediate_reg( 9); }
+void Cx4::op66() { immediate_reg(12); }
+void Cx4::op68() { immediate_reg(15); }
+void Cx4::op6a() { immediate_reg(18); }
+void Cx4::op6c() { immediate_reg(21); }
+void Cx4::op6e() { immediate_reg(24); }
+void Cx4::op70() { immediate_reg(27); }
+void Cx4::op72() { immediate_reg(30); }
+void Cx4::op74() { immediate_reg(33); }
+void Cx4::op76() { immediate_reg(36); }
+void Cx4::op78() { immediate_reg(39); }
+void Cx4::op7a() { immediate_reg(42); }
+void Cx4::op7c() { immediate_reg(45); }

 //Immediate ROM
-void C4::op89() {
+void Cx4::op89() {
  str(0, 0x054336);
  str(1, 0xffffff);
 }
+
+#endif //ifdef CX4_CPP
@@ -1,6 +1,5 @@
-#include "../../base.h"
-
-DSP1 *dsp1;
+#include "../../base.h"
+#define DSP1_CPP

 #include "dsp1emu.cpp"

@@ -28,29 +27,30 @@ void DSP1::reset() {
 *****/
 bool DSP1::addr_decode(uint16 addr) {
  switch(cartridge.info.dsp1_mapper) {
+    case Cartridge::DSP1LoROM1MB: {
+    //$[20-3f]:[8000-bfff] = DR, $[20-3f]:[c000-ffff] = SR
+      return (addr >= 0xc000);
+    }

-  case Cartridge::DSP1_LOROM_1MB:
-  //$[20-3f]:[8000-bfff] = DR, $[20-3f]:[c000-ffff] = SR
-    return (addr >= 0xc000);
-
-  case Cartridge::DSP1_LOROM_2MB:
-  //$[60-6f]:[0000-3fff] = DR, $[60-6f]:[4000-7fff] = SR
-    return (addr >= 0x4000);
-
-  case Cartridge::DSP1_HIROM:
-  //$[00-1f]:[6000-6fff] = DR, $[00-1f]:[7000-7fff] = SR
-    return (addr >= 0x7000);
+    case Cartridge::DSP1LoROM2MB: {
+    //$[60-6f]:[0000-3fff] = DR, $[60-6f]:[4000-7fff] = SR
+      return (addr >= 0x4000);
+    }

+    case Cartridge::DSP1HiROM: {
+    //$[00-1f]:[6000-6fff] = DR, $[00-1f]:[7000-7fff] = SR
+      return (addr >= 0x7000);
+    }
  }

  return 0;
 }

-uint8 DSP1::read(uint16 addr) {
+uint8 DSP1::read(uint addr) {
  return (addr_decode(addr) == 0) ? dsp1.getDr() : dsp1.getSr();
 }

-void DSP1::write(uint16 addr, uint8 data) {
+void DSP1::write(uint addr, uint8 data) {
  if(addr_decode(addr) == 0) {
    dsp1.setDr(data);
  }
@@ -1,18 +1,18 @@
 #include "dsp1emu.h"

-class DSP1 {
+class DSP1 : public Memory {
 private:
-Dsp1 dsp1;
+  Dsp1 dsp1;
+  bool addr_decode(uint16 addr);

 public:
-  void   init();
-  void   enable();
-  void   power();
-  void   reset();
+  void init();
+  void enable();
+  void power();
+  void reset();

-  bool   addr_decode(uint16 addr);
-  uint8  read (uint16 addr);
-  void   write(uint16 addr, uint8 data);
+  uint8 read(uint addr);
+  void write(uint addr, uint8 data);
 };

-extern DSP1 *dsp1;
+extern DSP1 dsp1;
@@ -1,3 +1,5 @@
+#ifdef DSP1_CPP
+
 // DSP-1's emulation code
 //
 // Based on research by Overload, The Dumper, Neviksti and Andreas Naive
@@ -1620,3 +1622,4 @@ const int16 Dsp1::SinTable[256] = {

 //////////////////////////////////////////////////////////////////

+#endif //ifdef DSP1_CPP
@@ -1,6 +1,5 @@
-#include "../../base.h"
-
-DSP2 *dsp2;
+#include "../../base.h"
+#define DSP2_CPP

 #include "dsp2_op.cpp"

@@ -30,7 +29,7 @@ void DSP2::reset() {
  status.op0dinlen       = 0;
 }

-uint8 DSP2::read(uint16 addr) {
+uint8 DSP2::read(uint addr) {
 uint8 r = 0xff;
  if(status.out_count) {
    r = status.output[status.out_index++];
@@ -42,7 +41,7 @@ uint8 r = 0xff;
  return r;
 }

-void DSP2::write(uint16 addr, uint8 data) {
+void DSP2::write(uint addr, uint8 data) {
  if(status.waiting_for_command) {
    status.command  = data;
    status.in_index = 0;
@@ -1,43 +1,44 @@
-class DSP2 {
+class DSP2 : public Memory {
 public:
-struct {
-  bool   waiting_for_command;
-  uint   command;
-  uint   in_count,  in_index;
-  uint   out_count, out_index;
+  struct {
+    bool   waiting_for_command;
+    uint   command;
+    uint   in_count,  in_index;
+    uint   out_count, out_index;

-  uint8  parameters[512];
-  uint8  output[512];
+    uint8  parameters[512];
+    uint8  output[512];

-  uint8  op05transparent;
-  bool   op05haslen;
-  int    op05len;
-  bool   op06haslen;
-  int    op06len;
-  uint16 op09word1;
-  uint16 op09word2;
-  bool   op0dhaslen;
-  int    op0doutlen;
-  int    op0dinlen;
-} status;
+    uint8  op05transparent;
+    bool   op05haslen;
+    int    op05len;
+    bool   op06haslen;
+    int    op06len;
+    uint16 op09word1;
+    uint16 op09word2;
+    bool   op0dhaslen;
+    int    op0doutlen;
+    int    op0dinlen;
+  } status;

-  void   init();
-  void   enable();
-  void   power();
-  void   reset();
+  void init();
+  void enable();
+  void power();
+  void reset();

-  void   op01();
-  void   op03();
-  void   op05();
-  void   op06();
-  void   op09();
-  void   op0d();
-
-  uint8  read (uint16 addr);
-  void   write(uint16 addr, uint8 data);
+  uint8 read(uint addr);
+  void write(uint addr, uint8 data);

  DSP2();
  ~DSP2();
+
+protected:
+  void op01();
+  void op03();
+  void op05();
+  void op06();
+  void op09();
+  void op0d();
 };

-extern DSP2 *dsp2;
+extern DSP2 dsp2;
@@ -1,3 +1,5 @@
+#ifdef DSP2_CPP
+
 //convert bitmap to bitplane tile
 void DSP2::op01() {
 //op01 size is always 32 bytes input and output
@@ -171,3 +173,5 @@ uint8  pixelarray[512];
    status.output[i] = (pixelarray[i << 1] << 4) | pixelarray[(i << 1) + 1];
  }
 }
+
+#endif //ifdef DSP2_CPP
@@ -0,0 +1,34 @@
+#include "../../base.h"
+#define DSP3_CPP
+
+namespace DSP3i {
+  #define bool8 uint8
+  #include "dsp3emu.c"
+  #undef bool8
+};
+
+void DSP3::init() {
+}
+
+void DSP3::enable() {
+}
+
+void DSP3::power() {
+  reset();
+}
+
+void DSP3::reset() {
+  DSP3i::DSP3_Reset();
+}
+
+uint8 DSP3::read(uint addr) {
+  DSP3i::dsp3_address = addr & 0xffff;
+  DSP3i::DSP3GetByte();
+  return DSP3i::dsp3_byte;
+}
+
+void DSP3::write(uint addr, uint8 data) {
+  DSP3i::dsp3_address = addr & 0xffff;
+  DSP3i::dsp3_byte = data;
+  DSP3i::DSP3SetByte();
+}
@@ -0,0 +1,12 @@
+class DSP3 : public Memory {
+public:
+  void init();
+  void enable();
+  void power();
+  void reset();
+
+  uint8 read (uint addr);
+  void  write(uint addr, uint8 data);
+};
+
+extern DSP3 dsp3;
@@ -0,0 +1,54 @@
+#include "../../base.h"
+#define DSP4_CPP
+
+namespace DSP4i {
+  inline uint16 READ_WORD(uint8 *addr) {
+    return (addr[0]) + (addr[1] << 8);
+  }
+
+  inline uint32 READ_DWORD(uint8 *addr) {
+    return (addr[0]) + (addr[1] << 8) + (addr[2] << 16) + (addr[3] << 24);
+  }
+
+  inline void WRITE_WORD(uint8 *addr, uint16 data) {
+    addr[0] = data;
+    addr[1] = data >> 8;
+  }
+
+  #define bool8 uint8
+  #include "dsp4emu.c"
+  #undef bool8
+};
+
+void DSP4::init() {
+}
+
+void DSP4::enable() {
+}
+
+void DSP4::power() {
+  reset();
+}
+
+void DSP4::reset() {
+  DSP4i::InitDSP4();
+}
+
+uint8 DSP4::read(uint addr) {
+  addr &= 0xffff;
+  if(addr < 0xc000) {
+    DSP4i::dsp4_address = addr;
+    DSP4i::DSP4GetByte();
+    return DSP4i::dsp4_byte;
+  }
+  return 0x80;
+}
+
+void DSP4::write(uint addr, uint8 data) {
+  addr &= 0xffff;
+  if(addr < 0xc000) {
+    DSP4i::dsp4_address = addr;
+    DSP4i::dsp4_byte = data;
+    DSP4i::DSP4SetByte();
+  }
+}
@@ -0,0 +1,12 @@
+class DSP4 : public Memory {
+public:
+  void init();
+  void enable();
+  void power();
+  void reset();
+
+  uint8 read (uint addr);
+  void  write(uint addr, uint8 data);
+};
+
+extern DSP4 dsp4;
@@ -0,0 +1,108 @@
+//DSP-4 emulator code
+//Copyright (c) 2004-2006 Dreamer Nom, John Weidman, Kris Bleakley, Nach, z80 gaiden
+
+#ifndef DSP4EMU_H
+#define DSP4EMU_H
+
+#undef TRUE
+#undef FALSE
+#define TRUE  true
+#define FALSE false
+
+struct DSP4_t
+{
+  bool8 waiting4command;
+  bool8 half_command;
+  uint16 command;
+  uint32 in_count;
+  uint32 in_index;
+  uint32 out_count;
+  uint32 out_index;
+  uint8 parameters[512];
+  uint8 output[512];
+};
+
+extern struct DSP4_t DSP4;
+
+struct DSP4_vars_t
+{
+  // op control
+  int8 DSP4_Logic;            // controls op flow
+
+
+  // projection format
+  int16 lcv;                  // loop-control variable
+  int16 distance;             // z-position into virtual world
+  int16 raster;               // current raster line
+  int16 segments;             // number of raster lines drawn
+
+  // 1.15.16 or 1.15.0 [sign, integer, fraction]
+  int32 world_x;              // line of x-projection in world
+  int32 world_y;              // line of y-projection in world
+  int32 world_dx;             // projection line x-delta
+  int32 world_dy;             // projection line y-delta
+  int16 world_ddx;            // x-delta increment
+  int16 world_ddy;            // y-delta increment
+  int32 world_xenv;           // world x-shaping factor
+  int16 world_yofs;           // world y-vertical scroll
+
+  int16 view_x1;              // current viewer-x
+  int16 view_y1;              // current viewer-y
+  int16 view_x2;              // future viewer-x
+  int16 view_y2;              // future viewer-y
+  int16 view_dx;              // view x-delta factor
+  int16 view_dy;              // view y-delta factor
+  int16 view_xofs1;           // current viewer x-vertical scroll
+  int16 view_yofs1;           // current viewer y-vertical scroll
+  int16 view_xofs2;           // future viewer x-vertical scroll
+  int16 view_yofs2;           // future viewer y-vertical scroll
+  int16 view_yofsenv;         // y-scroll shaping factor
+  int16 view_turnoff_x;       // road turnoff data
+  int16 view_turnoff_dx;      // road turnoff delta factor
+
+
+  // drawing area
+
+  int16 viewport_cx;          // x-center of viewport window
+  int16 viewport_cy;          // y-center of render window
+  int16 viewport_left;        // x-left of viewport
+  int16 viewport_right;       // x-right of viewport
+  int16 viewport_top;         // y-top of viewport
+  int16 viewport_bottom;      // y-bottom of viewport
+
+
+  // sprite structure
+
+  int16 sprite_x;             // projected x-pos of sprite
+  int16 sprite_y;             // projected y-pos of sprite
+  int16 sprite_attr;          // obj attributes
+  bool8 sprite_size;          // sprite size: 8x8 or 16x16
+  int16 sprite_clipy;         // visible line to clip pixels off
+  int16 sprite_count;
+
+  // generic projection variables designed for
+  // two solid polygons + two polygon sides
+
+  int16 poly_clipLf[2][2];    // left clip boundary
+  int16 poly_clipRt[2][2];    // right clip boundary
+  int16 poly_ptr[2][2];       // HDMA structure pointers
+  int16 poly_raster[2][2];    // current raster line below horizon
+  int16 poly_top[2][2];       // top clip boundary
+  int16 poly_bottom[2][2];    // bottom clip boundary
+  int16 poly_cx[2][2];        // center for left/right points
+  int16 poly_start[2];        // current projection points
+  int16 poly_plane[2];        // previous z-plane distance
+
+
+  // OAM
+  int16 OAM_attr[16];         // OAM (size,MSB) data
+  int16 OAM_index;            // index into OAM table
+  int16 OAM_bits;             // offset into OAM table
+
+  int16 OAM_RowMax;           // maximum number of tiles per 8 aligned pixels (row)
+  int16 OAM_Row[32];          // current number of tiles per row
+};
+
+extern struct DSP4_vars_t DSP4_vars;
+
+#endif
@@ -1,7 +1,5 @@
 #include "../../base.h"

-OBC1 *obc1;
-
 void OBC1::init() {}
 void OBC1::enable() {}

@@ -10,81 +8,82 @@ void OBC1::power() {
 }

 void OBC1::reset() {
-  memset(cartridge.sram, 0xff, 0x2000);
-  status.baseptr = (cartridge.sram[0x1ff5] & 1) ? 0x1800 : 0x1c00;
-  status.address = (cartridge.sram[0x1ff6] & 0x7f);
-  status.shift   = (cartridge.sram[0x1ff6] & 3) << 1;
+  for(uint i = 0x0000; i <= 0x1fff; i++) ram_write(i, 0xff);
+
+  status.baseptr = (ram_read(0x1ff5) & 1) ? 0x1800 : 0x1c00;
+  status.address = (ram_read(0x1ff6) & 0x7f);
+  status.shift   = (ram_read(0x1ff6) & 3) << 1;
 }

-uint8 OBC1::read(uint16 addr) {
+uint8 OBC1::read(uint addr) {
  addr &= 0x1fff;
-
-  if((addr & 0x1ff8) != 0x1ff0) {
-    return cartridge.sram[addr];
-  }
+  if((addr & 0x1ff8) != 0x1ff0) return ram_read(addr);

  switch(addr) {
  case 0x1ff0:
-    return cartridge.sram[status.baseptr + (status.address << 2) + 0];
+    return ram_read(status.baseptr + (status.address << 2) + 0);
  case 0x1ff1:
-    return cartridge.sram[status.baseptr + (status.address << 2) + 1];
+    return ram_read(status.baseptr + (status.address << 2) + 1);
  case 0x1ff2:
-    return cartridge.sram[status.baseptr + (status.address << 2) + 2];
+    return ram_read(status.baseptr + (status.address << 2) + 2);
  case 0x1ff3:
-    return cartridge.sram[status.baseptr + (status.address << 2) + 3];
+    return ram_read(status.baseptr + (status.address << 2) + 3);
  case 0x1ff4:
-    return cartridge.sram[status.baseptr + (status.address >> 2) + 0x200];
+    return ram_read(status.baseptr + (status.address >> 2) + 0x200);
  case 0x1ff5:
  case 0x1ff6:
  case 0x1ff7:
-    return cartridge.sram[addr];
+    return ram_read(addr);
  }

-//never used, blocks compiler warning
-  return 0x00;
+  return 0x00; //never used, avoids compiler warning
 }

-void OBC1::write(uint16 addr, uint8 data) {
+void OBC1::write(uint addr, uint8 data) {
  addr &= 0x1fff;
-
-  if((addr & 0x1ff8) != 0x1ff0) {
-    cartridge.sram[addr] = data;
-    return;
-  }
+  if((addr & 0x1ff8) != 0x1ff0) return ram_write(addr, data);

  switch(addr) {
  case 0x1ff0:
-    cartridge.sram[status.baseptr + (status.address << 2) + 0] = data;
+    ram_write(status.baseptr + (status.address << 2) + 0, data);
    break;
  case 0x1ff1:
-    cartridge.sram[status.baseptr + (status.address << 2) + 1] = data;
+    ram_write(status.baseptr + (status.address << 2) + 1, data);
    break;
  case 0x1ff2:
-    cartridge.sram[status.baseptr + (status.address << 2) + 2] = data;
+    ram_write(status.baseptr + (status.address << 2) + 2, data);
    break;
  case 0x1ff3:
-    cartridge.sram[status.baseptr + (status.address << 2) + 3] = data;
+    ram_write(status.baseptr + (status.address << 2) + 3, data);
    break;
  case 0x1ff4: {
  uint8 temp;
-    temp = cartridge.sram[status.baseptr + (status.address >> 2) + 0x200];
+    temp = ram_read(status.baseptr + (status.address >> 2) + 0x200);
    temp = (temp & ~(3 << status.shift)) | ((data & 3) << status.shift);
-    cartridge.sram[status.baseptr + (status.address >> 2) + 0x200] = temp;
+    ram_write(status.baseptr + (status.address >> 2) + 0x200, temp);
  } break;
  case 0x1ff5:
    status.baseptr = (data & 1) ? 0x1800 : 0x1c00;
-    cartridge.sram[addr] = data;
+    ram_write(addr, data);
    break;
  case 0x1ff6:
    status.address = (data & 0x7f);
    status.shift   = (data & 3) << 1;
-    cartridge.sram[addr] = data;
+    ram_write(addr, data);
    break;
  case 0x1ff7:
-    cartridge.sram[addr] = data;
+    ram_write(addr, data);
    break;
  }
 }

+uint8 OBC1::ram_read(uint addr) {
+  return memory::cartram.read(addr & 0x1fff);
+}
+
+void OBC1::ram_write(uint addr, uint8 data) {
+  memory::cartram.write(addr & 0x1fff, data);
+}
+
 OBC1::OBC1() {}
 OBC1::~OBC1() {}
@@ -1,20 +1,25 @@
-class OBC1 {
+class OBC1 : public Memory {
 public:
-struct {
-  uint16 address;
-  uint16 baseptr;
-  uint16 shift;
-} status;
-  void   init();
-  void   enable();
-  void   power();
-  void   reset();
+  void init();
+  void enable();
+  void power();
+  void reset();

-  uint8  read (uint16 addr);
-  void   write(uint16 addr, uint8 data);
+  uint8 read(uint addr);
+  void write(uint addr, uint8 data);

  OBC1();
  ~OBC1();
+
+private:
+  uint8 ram_read(uint addr);
+  void ram_write(uint addr, uint8 data);
+
+  struct {
+    uint16 address;
+    uint16 baseptr;
+    uint16 shift;
+  } status;
 };

-extern OBC1 *obc1;
+extern OBC1 obc1;
@@ -1,15 +1,12 @@
-#include "../../base.h"
-
-SDD1 *sdd1;
+#include "../../base.h"
+#define SDD1_CPP

 #include "sdd1emu.cpp"

 void SDD1::init() {}

 void SDD1::enable() {
-  for(int i = 0x4800; i <= 0x4807; i++) {
-    r_mem->set_mmio_mapper(i, this);
-  }
+  for(int i = 0x4800; i <= 0x4807; i++) memory::mmio.map(i, *this);
 }

 void SDD1::power() {
@@ -17,59 +14,80 @@ void SDD1::power() {
 }

 void SDD1::reset() {
-  sdd1.index[0] = 0x000000;
-  sdd1.index[1] = 0x100000;
-  sdd1.index[2] = 0x200000;
-  sdd1.index[3] = 0x300000;
-
-  for(int i=0;i<8;i++) {
-    sdd1.active[i] = false;
-  }
-
  sdd1.dma_active = false;
+
+  regs.r4800 = 0x00;
+  regs.r4801 = 0x00;
+
+  regs.r4804 = 0x00;
+  regs.r4805 = 0x01;
+  regs.r4806 = 0x02;
+  regs.r4807 = 0x03;
+
+  bus.map(Bus::MapLinear, 0xc0, 0xcf, 0x0000, 0xffff, memory::cartrom, (regs.r4804 & 7) << 20);
+  bus.map(Bus::MapLinear, 0xd0, 0xdf, 0x0000, 0xffff, memory::cartrom, (regs.r4805 & 7) << 20);
+  bus.map(Bus::MapLinear, 0xe0, 0xef, 0x0000, 0xffff, memory::cartrom, (regs.r4806 & 7) << 20);
+  bus.map(Bus::MapLinear, 0xf0, 0xff, 0x0000, 0xffff, memory::cartrom, (regs.r4807 & 7) << 20);
 }

-uint32 SDD1::offset(uint32 addr) {
-uint8 b = (addr >> 16) & 0xff;
-  if(b <= 0xbf)return 0;
-
-  b  -= 0xc0; //b = 0x00-0x3f
-  b >>= 4;    //b = 0-3
-  b  &= 3;    //bitmask
-
-  return sdd1.index[b] + (addr & 0x0fffff);
-}
-
-uint8 SDD1::mmio_read(uint16 addr) {
-  switch(addr) {
-  //>>20 == 0x100000 == 1mb
-  case 0x4804:return (sdd1.index[0] >> 20) & 7;
-  case 0x4805:return (sdd1.index[1] >> 20) & 7;
-  case 0x4806:return (sdd1.index[2] >> 20) & 7;
-  case 0x4807:return (sdd1.index[3] >> 20) & 7;
+uint8 SDD1::mmio_read(uint addr) {
+  switch(addr & 0xffff) {
+    case 0x4804: return regs.r4804;
+    case 0x4805: return regs.r4805;
+    case 0x4806: return regs.r4806;
+    case 0x4807: return regs.r4807;
  }

-  return r_cpu->regs.mdr;
+  return cpu.regs.mdr;
 }

-void SDD1::mmio_write(uint16 addr, uint8 data) {
-  switch(addr) {
-  case 0x4801:
-    for(int i = 0; i < 8; i++) {
-      sdd1.active[i] = !!(data & (1 << i));
-    }
-    break;
-  //<<20 == 0x100000 == 1mb
-  case 0x4804:sdd1.index[0] = (data & 7) << 20;break;
-  case 0x4805:sdd1.index[1] = (data & 7) << 20;break;
-  case 0x4806:sdd1.index[2] = (data & 7) << 20;break;
-  case 0x4807:sdd1.index[3] = (data & 7) << 20;break;
+void SDD1::mmio_write(uint addr, uint8 data) {
+  switch(addr & 0xffff) {
+    case 0x4800: {
+      regs.r4800 = data;
+    } break;
+
+    case 0x4801: {
+      regs.r4801 = data;
+    } break;
+
+    case 0x4804: {
+      if(regs.r4804 != data) {
+        regs.r4804 = data;
+        bus.map(Bus::MapLinear, 0xc0, 0xcf, 0x0000, 0xffff,
+          memory::cartrom, (regs.r4804 & 7) << 20);
+      }
+    } break;
+
+    case 0x4805: {
+      if(regs.r4805 != data) {
+        regs.r4805 = data;
+        bus.map(Bus::MapLinear, 0xd0, 0xdf, 0x0000, 0xffff,
+          memory::cartrom, (regs.r4805 & 7) << 20);
+      }
+    } break;
+
+    case 0x4806: {
+      if(regs.r4806 != data) {
+        regs.r4806 = data;
+        bus.map(Bus::MapLinear, 0xe0, 0xef, 0x0000, 0xffff,
+          memory::cartrom, (regs.r4806 & 7) << 20);
+      }
+    } break;
+
+    case 0x4807: {
+      if(regs.r4807 != data) {
+        regs.r4807 = data;
+        bus.map(Bus::MapLinear, 0xf0, 0xff, 0x0000, 0xffff,
+          memory::cartrom, (regs.r4807 & 7) << 20);
+      }
+    } break;
  }
 }

 void SDD1::dma_begin(uint8 channel, uint32 addr, uint16 length) {
-  if(sdd1.active[channel] == true) {
-    sdd1.active[channel] = false;
+  if(regs.r4800 & (1 << channel) && regs.r4801 & (1 << channel)) {
+    regs.r4801 &= ~(1 << channel);
    sdd1.dma_active   = true;
    sdd1.buffer_index = 0;
    sdd1.buffer_size  = length;
@@ -82,9 +100,7 @@ bool SDD1::dma_active() {
 }

 uint8 SDD1::dma_read() {
-  if(--sdd1.buffer_size == 0) {
-    sdd1.dma_active = false;
-  }
+  if(--sdd1.buffer_size == 0) sdd1.dma_active = false;

 //sdd1.buffer[] is 65536 bytes, and sdd1.buffer_index
 //is of type uint16, so no buffer overflow is possible
@@ -2,31 +2,38 @@

 class SDD1 : public MMIO {
 public:
-SDD1emu sdd1emu;
+  void init();
+  void enable();
+  void power();
+  void reset();

-struct {
-  uint32 index[4];      //memory mapping registers
-  uint8  buffer[65536]; //pointer to decompressed S-DD1 data,
-                        //max. DMA length is 65536
-  uint16 buffer_index;  //DMA read index into S-DD1 decompression buffer
-  uint16 buffer_size;
-  bool   active[8];     //true when DMA channel should pass through S-DD1
-  bool   dma_active;
-} sdd1;
-  void   init();
-  void   enable();
-  void   power();
-  void   reset();
-  uint32 offset(uint32 addr);
+  uint8 mmio_read (uint addr);
+  void  mmio_write(uint addr, uint8 data);

-  void   dma_begin(uint8 channel, uint32 addr, uint16 length);
-  bool   dma_active();
-  uint8  dma_read();
-
-  uint8  mmio_read (uint16 addr);
-  void   mmio_write(uint16 addr, uint8 data);
+  void  dma_begin(uint8 channel, uint32 addr, uint16 length);
+  bool  dma_active();
+  uint8 dma_read();

  SDD1();
+
+private:
+  SDD1emu sdd1emu;
+
+  struct {
+    uint8  buffer[65536]; //pointer to decompressed S-DD1 data, max DMA length is 65536
+    uint16 buffer_index;  //DMA read index into S-DD1 decompression buffer
+    uint16 buffer_size;
+    bool   dma_active;
+  } sdd1;
+
+  struct {
+    uint8 r4800;
+    uint8 r4801;
+    uint8 r4804;
+    uint8 r4805;
+    uint8 r4806;
+    uint8 r4807;
+  } regs;
 };

-extern SDD1 *sdd1;
+extern SDD1 sdd1;
@@ -1,3 +1,5 @@
+#ifdef SDD1_CPP
+
 /************************************************************************

 S-DD1'algorithm emulation code
@@ -28,7 +30,7 @@ understood.

 ************************************************************************/

-#define SDD1_read(__addr) (r_mem->read(__addr))
+#define SDD1_read(__addr) (bus.read(__addr))

 ////////////////////////////////////////////////////

@@ -445,3 +447,5 @@ SDD1emu::SDD1emu() :
 }

 ///////////////////////////////////////////////////////////
+
+#endif //ifdef SDD1_CPP
@@ -28,6 +28,7 @@ understood.

 ************************************************************************/

+typedef uint8_t bool8;

 class SDD1_IM {  //Input Manager

@@ -0,0 +1,511 @@
+#ifdef SPC7110_CPP
+
+uint8 SPC7110Decomp::read() {
+  if(decomp_buffer_length == 0) {
+    //decompress at least (decomp_buffer_size / 2) bytes to the buffer
+    switch(decomp_mode) {
+      case 0: mode0(false); break;
+      case 1: mode1(false); break;
+      case 2: mode2(false); break;
+      default: return 0x00;
+    }
+  }
+
+  uint8 data = decomp_buffer[decomp_buffer_rdoffset++];
+  decomp_buffer_rdoffset &= decomp_buffer_size - 1;
+  decomp_buffer_length--;
+  return data;
+}
+
+void SPC7110Decomp::write(uint8 data) {
+  decomp_buffer[decomp_buffer_wroffset++] = data;
+  decomp_buffer_wroffset &= decomp_buffer_size - 1;
+  decomp_buffer_length++;
+}
+
+uint8 SPC7110Decomp::dataread() {
+  unsigned size = memory::cartrom.size() - 0x100000;
+  while(decomp_offset >= size) decomp_offset -= size;
+  return memory::cartrom.read(0x100000 + decomp_offset++);
+}
+
+void SPC7110Decomp::init(unsigned mode, unsigned offset, unsigned index) {
+  decomp_mode = mode;
+  decomp_offset = offset;
+
+  decomp_buffer_rdoffset = 0;
+  decomp_buffer_wroffset = 0;
+  decomp_buffer_length   = 0;
+
+  //reset context states
+  for(unsigned i = 0; i < 32; i++) {
+    context[i].index  = 0;
+    context[i].invert = 0;
+  }
+
+  switch(decomp_mode) {
+    case 0: mode0(true); break;
+    case 1: mode1(true); break;
+    case 2: mode2(true); break;
+  }
+
+  //decompress up to requested output data index
+  while(index--) read();
+}
+
+//
+
+void SPC7110Decomp::mode0(bool init) {
+  static uint8 val, in, span;
+  static int out, inverts, lps, in_count;
+
+  if(init == true) {
+    out = inverts = lps = 0;
+    span = 0xff;
+    val = dataread();
+    in = dataread();
+    in_count = 8;
+    return;
+  }
+
+  while(decomp_buffer_length < (decomp_buffer_size >> 1)) {
+    for(unsigned bit = 0; bit < 8; bit++) {
+      //get context
+      uint8 mask = (1 << (bit & 3)) - 1;
+      uint8 con = mask + ((inverts & mask) ^ (lps & mask));
+      if(bit > 3) con += 15;
+
+      //get prob and mps
+      unsigned prob = probability(con);
+      unsigned mps = (((out >> 15) & 1) ^ context[con].invert);
+
+      //get bit
+      unsigned flag_lps;
+      if(val <= span - prob) { //mps
+        span = span - prob;
+        out = (out << 1) + mps;
+        flag_lps = 0;
+      } else { //lps
+        val = val - (span - (prob - 1));
+        span = prob - 1;
+        out = (out << 1) + 1 - mps;
+        flag_lps = 1;
+      }
+
+      //renormalize
+      unsigned shift = 0;
+      while(span < 0x7f) {
+        shift++;
+
+        span = (span << 1) + 1;
+        val = (val << 1) + (in >> 7);
+
+        in <<= 1;
+        if(--in_count == 0) {
+          in = dataread();
+          in_count = 8;
+        }
+      }
+
+      //update processing info
+      lps = (lps << 1) + flag_lps;
+      inverts = (inverts << 1) + context[con].invert;
+
+      //update context state
+      if(flag_lps & toggle_invert(con)) context[con].invert ^= 1;
+      if(flag_lps) context[con].index = next_lps(con);
+      else if(shift) context[con].index = next_mps(con);
+    }
+
+    //save byte
+    write(out);
+  }
+}
+
+void SPC7110Decomp::mode1(bool init) {
+  static int pixelorder[4], realorder[4];
+  static uint8 in, val, span;
+  static int out, inverts, lps, in_count;
+
+  if(init == true) {
+    for(unsigned i = 0; i < 4; i++) pixelorder[i] = i;
+    out = inverts = lps = 0;
+    span = 0xff;
+    val = dataread();
+    in = dataread();
+    in_count = 8;
+    return;
+  }
+
+  while(decomp_buffer_length < (decomp_buffer_size >> 1)) {
+    for(unsigned pixel = 0; pixel < 8; pixel++) {
+      //get first symbol context
+      unsigned a = ((out >> (1 * 2)) & 3);
+      unsigned b = ((out >> (7 * 2)) & 3);
+      unsigned c = ((out >> (8 * 2)) & 3);
+      unsigned con = (a == b) ? (b != c) : (b == c) ? 2 : 4 - (a == c);
+
+      //update pixel order
+      unsigned m, n;
+      for(m = 0; m < 4; m++) if(pixelorder[m] == a) break;
+      for(n = m; n > 0; n--) pixelorder[n] = pixelorder[n - 1];
+      pixelorder[0] = a;
+
+      //calculate the real pixel order
+      for(m = 0; m < 4; m++) realorder[m] = pixelorder[m];
+
+      //rotate reference pixel c value to top
+      for(m = 0; m < 4; m++) if(realorder[m] == c) break;
+      for(n = m; n > 0; n--) realorder[n] = realorder[n - 1];
+      realorder[0] = c;
+
+      //rotate reference pixel b value to top
+      for(m = 0; m < 4; m++) if(realorder[m] == b) break;
+      for(n = m; n > 0; n--) realorder[n] = realorder[n - 1];
+      realorder[0] = b;
+
+      //rotate reference pixel a value to top
+      for(m = 0; m < 4; m++) if(realorder[m] == a) break;
+      for(n = m; n > 0; n--) realorder[n] = realorder[n - 1];
+      realorder[0] = a;
+
+      //get 2 symbols
+      for(unsigned bit = 0; bit < 2; bit++) {
+        //get prob
+        unsigned prob = probability(con);
+
+        //get symbol
+        unsigned flag_lps;
+        if(val <= span - prob) { //mps
+          span = span - prob;
+          flag_lps = 0;
+        } else { //lps
+          val = val - (span - (prob - 1));
+          span = prob - 1;
+          flag_lps = 1;
+        }
+
+        //renormalize
+        unsigned shift = 0;
+        while(span < 0x7f) {
+          shift++;
+
+          span = (span << 1) + 1;
+          val = (val << 1) + (in >> 7);
+
+          in <<= 1;
+          if(--in_count == 0) {
+            in = dataread();
+            in_count = 8;
+          }
+        }
+
+        //update processing info
+        lps = (lps << 1) + flag_lps;
+        inverts = (inverts << 1) + context[con].invert;
+
+        //update context state
+        if(flag_lps & toggle_invert(con)) context[con].invert ^= 1;
+        if(flag_lps) context[con].index = next_lps(con);
+        else if(shift) context[con].index = next_mps(con);
+
+        //get next context
+        con = 5 + (con << 1) + ((lps ^ inverts) & 1);
+      }
+
+      //get pixel
+      b = realorder[(lps ^ inverts) & 3];
+      out = (out << 2) + b;
+    }
+
+    //turn pixel data into bitplanes
+    unsigned data = morton_2x8(out);
+    write(data >> 8);
+    write(data >> 0);
+  }
+}
+
+void SPC7110Decomp::mode2(bool init) {
+  static int pixelorder[16], realorder[16];
+  static uint8 bitplanebuffer[16], buffer_index;
+  static uint8 in, val, span;
+  static int out0, out1, inverts, lps, in_count;
+
+  if(init == true) {
+    for(unsigned i = 0; i < 16; i++) pixelorder[i] = i;
+    buffer_index = 0;
+    out0 = out1 = inverts = lps = 0;
+    span = 0xff;
+    val = dataread();
+    in = dataread();
+    in_count = 8;
+    return;
+  }
+
+  while(decomp_buffer_length < (decomp_buffer_size >> 1)) {
+    for(unsigned pixel = 0; pixel < 8; pixel++) {
+      //get first symbol context
+      unsigned a = ((out0 >> (0 * 4)) & 15);
+      unsigned b = ((out0 >> (7 * 4)) & 15);
+      unsigned c = ((out1 >> (0 * 4)) & 15);
+      unsigned con = 0;
+      unsigned refcon = (a == b) ? (b != c) : (b == c) ? 2 : 4 - (a == c);
+
+      //update pixel order
+      unsigned m, n;
+      for(m = 0; m < 16; m++) if(pixelorder[m] == a) break;
+      for(n = m; n >  0; n--) pixelorder[n] = pixelorder[n - 1];
+      pixelorder[0] = a;
+
+      //calculate the real pixel order
+      for(m = 0; m < 16; m++) realorder[m] = pixelorder[m];
+
+      //rotate reference pixel c value to top
+      for(m = 0; m < 16; m++) if(realorder[m] == c) break;
+      for(n = m; n >  0; n--) realorder[n] = realorder[n - 1];
+      realorder[0] = c;
+
+      //rotate reference pixel b value to top
+      for(m = 0; m < 16; m++) if(realorder[m] == b) break;
+      for(n = m; n >  0; n--) realorder[n] = realorder[n - 1];
+      realorder[0] = b;
+
+      //rotate reference pixel a value to top
+      for(m = 0; m < 16; m++) if(realorder[m] == a) break;
+      for(n = m; n >  0; n--) realorder[n] = realorder[n - 1];
+      realorder[0] = a;
+
+      //get 4 symbols
+      for(unsigned bit = 0; bit < 4; bit++) {
+        //get prob
+        unsigned prob = probability(con);
+
+        //get symbol
+        unsigned flag_lps;
+        if(val <= span - prob) { //mps
+          span = span - prob;
+          flag_lps = 0;
+        } else { //lps
+          val = val - (span - (prob - 1));
+          span = prob - 1;
+          flag_lps = 1;
+        }
+
+        //renormalize
+        unsigned shift = 0;
+        while(span < 0x7f) {
+          shift++;
+
+          span = (span << 1) + 1;
+          val = (val << 1) + (in >> 7);
+
+          in <<= 1;
+          if(--in_count == 0) {
+            in = dataread();
+            in_count = 8;
+          }
+        }
+
+        //update processing info
+        lps = (lps << 1) + flag_lps;
+        unsigned invertbit = context[con].invert;
+        inverts = (inverts << 1) + invertbit;
+
+        //update context state
+        if(flag_lps & toggle_invert(con)) context[con].invert ^= 1;
+        if(flag_lps) context[con].index = next_lps(con);
+        else if(shift) context[con].index = next_mps(con);
+
+        //get next context
+        con = mode2_context_table[con][flag_lps ^ invertbit] + (con == 1 ? refcon : 0);
+      }
+
+      //get pixel
+      b = realorder[(lps ^ inverts) & 0x0f];
+      out1 = (out1 << 4) + ((out0 >> 28) & 0x0f);
+      out0 = (out0 << 4) + b;
+    }
+
+    //convert pixel data into bitplanes
+    unsigned data = morton_4x8(out0);
+    write(data >> 24);
+    write(data >> 16);
+    bitplanebuffer[buffer_index++] = data >> 8;
+    bitplanebuffer[buffer_index++] = data >> 0;
+
+    if(buffer_index == 16) {
+      for(unsigned i = 0; i < 16; i++) write(bitplanebuffer[i]);
+      buffer_index = 0;
+    }
+  }
+}
+
+//
+
+const uint8 SPC7110Decomp::evolution_table[53][4] = {
+//{ prob, nextlps, nextmps, toggle invert },
+
+  { 0x5a,  1,  1, 1 },
+  { 0x25,  6,  2, 0 },
+  { 0x11,  8,  3, 0 },
+  { 0x08, 10,  4, 0 },
+  { 0x03, 12,  5, 0 },
+  { 0x01, 15,  5, 0 },
+
+  { 0x5a,  7,  7, 1 },
+  { 0x3f, 19,  8, 0 },
+  { 0x2c, 21,  9, 0 },
+  { 0x20, 22, 10, 0 },
+  { 0x17, 23, 11, 0 },
+  { 0x11, 25, 12, 0 },
+  { 0x0c, 26, 13, 0 },
+  { 0x09, 28, 14, 0 },
+  { 0x07, 29, 15, 0 },
+  { 0x05, 31, 16, 0 },
+  { 0x04, 32, 17, 0 },
+  { 0x03, 34, 18, 0 },
+  { 0x02, 35,  5, 0 },
+
+  { 0x5a, 20, 20, 1 },
+  { 0x48, 39, 21, 0 },
+  { 0x3a, 40, 22, 0 },
+  { 0x2e, 42, 23, 0 },
+  { 0x26, 44, 24, 0 },
+  { 0x1f, 45, 25, 0 },
+  { 0x19, 46, 26, 0 },
+  { 0x15, 25, 27, 0 },
+  { 0x11, 26, 28, 0 },
+  { 0x0e, 26, 29, 0 },
+  { 0x0b, 27, 30, 0 },
+  { 0x09, 28, 31, 0 },
+  { 0x08, 29, 32, 0 },
+  { 0x07, 30, 33, 0 },
+  { 0x05, 31, 34, 0 },
+  { 0x04, 33, 35, 0 },
+  { 0x04, 33, 36, 0 },
+  { 0x03, 34, 37, 0 },
+  { 0x02, 35, 38, 0 },
+  { 0x02, 36,  5, 0 },
+
+  { 0x58, 39, 40, 1 },
+  { 0x4d, 47, 41, 0 },
+  { 0x43, 48, 42, 0 },
+  { 0x3b, 49, 43, 0 },
+  { 0x34, 50, 44, 0 },
+  { 0x2e, 51, 45, 0 },
+  { 0x29, 44, 46, 0 },
+  { 0x25, 45, 24, 0 },
+
+  { 0x56, 47, 48, 1 },
+  { 0x4f, 47, 49, 0 },
+  { 0x47, 48, 50, 0 },
+  { 0x41, 49, 51, 0 },
+  { 0x3c, 50, 52, 0 },
+  { 0x37, 51, 43, 0 },
+};
+
+const uint8 SPC7110Decomp::mode2_context_table[32][2] = {
+//{ next 0, next 1 },
+
+  {  1,  2 },
+
+  {  3,  8 },
+  { 13, 14 },
+
+  { 15, 16 },
+  { 17, 18 },
+  { 19, 20 },
+  { 21, 22 },
+  { 23, 24 },
+  { 25, 26 },
+  { 25, 26 },
+  { 25, 26 },
+  { 25, 26 },
+  { 25, 26 },
+  { 27, 28 },
+  { 29, 30 },
+
+  { 31, 31 },
+  { 31, 31 },
+  { 31, 31 },
+  { 31, 31 },
+  { 31, 31 },
+  { 31, 31 },
+  { 31, 31 },
+  { 31, 31 },
+  { 31, 31 },
+  { 31, 31 },
+  { 31, 31 },
+  { 31, 31 },
+  { 31, 31 },
+  { 31, 31 },
+  { 31, 31 },
+  { 31, 31 },
+
+  { 31, 31 },
+};
+
+uint8 SPC7110Decomp::probability  (unsigned n) { return evolution_table[context[n].index][0]; }
+uint8 SPC7110Decomp::next_lps     (unsigned n) { return evolution_table[context[n].index][1]; }
+uint8 SPC7110Decomp::next_mps     (unsigned n) { return evolution_table[context[n].index][2]; }
+bool  SPC7110Decomp::toggle_invert(unsigned n) { return evolution_table[context[n].index][3]; }
+
+unsigned SPC7110Decomp::morton_2x8(unsigned data) {
+  //reverse morton lookup: de-interleave two 8-bit values
+  //15, 13, 11,  9,  7,  5,  3,  1 -> 15- 8
+  //14, 12, 10,  8,  6,  4,  2,  0 ->  7- 0
+  return morton16[0][(data >>  0) & 255] + morton16[1][(data >>  8) & 255];
+}
+
+unsigned SPC7110Decomp::morton_4x8(unsigned data) {
+  //reverse morton lookup: de-interleave four 8-bit values
+  //31, 27, 23, 19, 15, 11,  7,  3 -> 31-24
+  //30, 26, 22, 18, 14, 10,  6,  2 -> 23-16
+  //29, 25, 21, 17, 13,  9,  5,  1 -> 15- 8
+  //28, 24, 20, 16, 12,  8,  4,  0 ->  7- 0
+  return morton32[0][(data >>  0) & 255] + morton32[1][(data >>  8) & 255]
+       + morton32[2][(data >> 16) & 255] + morton32[3][(data >> 24) & 255];
+}
+
+//
+
+void SPC7110Decomp::reset() {
+  //mode 3 is invalid; this is treated as a special case to always return 0x00
+  //set to mode 3 so that reading decomp port before starting first decomp will return 0x00
+  decomp_mode = 3;
+
+  decomp_buffer_rdoffset = 0;
+  decomp_buffer_wroffset = 0;
+  decomp_buffer_length   = 0;
+}
+
+SPC7110Decomp::SPC7110Decomp() {
+  decomp_buffer = new uint8_t[decomp_buffer_size];
+  reset();
+
+  //initialize reverse morton lookup tables
+  for(unsigned i = 0; i < 256; i++) {
+    #define map(x, y) (((i >> x) & 1) << y)
+    //2x8-bit
+    morton16[1][i] = map(7, 15) + map(6,  7) + map(5, 14) + map(4,  6)
+                   + map(3, 13) + map(2,  5) + map(1, 12) + map(0,  4);
+    morton16[0][i] = map(7, 11) + map(6,  3) + map(5, 10) + map(4,  2)
+                   + map(3,  9) + map(2,  1) + map(1,  8) + map(0,  0);
+    //4x8-bit
+    morton32[3][i] = map(7, 31) + map(6, 23) + map(5, 15) + map(4,  7)
+                   + map(3, 30) + map(2, 22) + map(1, 14) + map(0,  6);
+    morton32[2][i] = map(7, 29) + map(6, 21) + map(5, 13) + map(4,  5)
+                   + map(3, 28) + map(2, 20) + map(1, 12) + map(0,  4);
+    morton32[1][i] = map(7, 27) + map(6, 19) + map(5, 11) + map(4,  3)
+                   + map(3, 26) + map(2, 18) + map(1, 10) + map(0,  2);
+    morton32[0][i] = map(7, 25) + map(6, 17) + map(5,  9) + map(4,  1)
+                   + map(3, 24) + map(2, 16) + map(1,  8) + map(0,  0);
+    #undef map
+  }
+}
+
+SPC7110Decomp::~SPC7110Decomp() {
+  delete[] decomp_buffer;
+}
+
+#endif
@@ -0,0 +1,45 @@
+class SPC7110Decomp {
+public:
+  uint8 read();
+  void init(unsigned mode, unsigned offset, unsigned index);
+  void reset();
+
+  SPC7110Decomp();
+  ~SPC7110Decomp();
+
+private:
+  unsigned decomp_mode;
+  unsigned decomp_offset;
+
+  //read() will spool chunks half the size of decomp_buffer_size
+  enum { decomp_buffer_size = 64 }; //must be >= 64, and must be a power of two
+  uint8 *decomp_buffer;
+  unsigned decomp_buffer_rdoffset;
+  unsigned decomp_buffer_wroffset;
+  unsigned decomp_buffer_length;
+
+  void write(uint8 data);
+  uint8 dataread();
+
+  void mode0(bool init);
+  void mode1(bool init);
+  void mode2(bool init);
+
+  static const uint8 evolution_table[53][4];
+  static const uint8 mode2_context_table[32][2];
+
+  struct ContextState {
+    uint8 index;
+    uint8 invert;
+  } context[32];
+
+  uint8 probability(unsigned n);
+  uint8 next_lps(unsigned n);
+  uint8 next_mps(unsigned n);
+  bool toggle_invert(unsigned n);
+
+  unsigned morton16[2][256];
+  unsigned morton32[4][256];
+  unsigned morton_2x8(unsigned data);
+  unsigned morton_4x8(unsigned data);
+};
@@ -0,0 +1,658 @@
+#include "../../base.h"
+#define SPC7110_CPP
+
+#include "decomp.cpp"
+
+const unsigned SPC7110::months[12] = { 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 };
+
+void SPC7110::init() {}
+
+void SPC7110::enable() {
+  uint16_t limit = (cartridge.info.spc7110rtc ? 0x4842 : 0x483f);
+  for(uint16_t i = 0x4800; i <= limit; i++) memory::mmio.map(i, *this);
+}
+
+void SPC7110::power() {
+  reset();
+}
+
+void SPC7110::reset() {
+  r4801 = 0x00;
+  r4802 = 0x00;
+  r4803 = 0x00;
+  r4804 = 0x00;
+  r4805 = 0x00;
+  r4806 = 0x00;
+  r4807 = 0x00;
+  r4808 = 0x00;
+  r4809 = 0x00;
+  r480a = 0x00;
+  r480b = 0x00;
+  r480c = 0x00;
+
+  decomp.reset();
+
+  r4811 = 0x00;
+  r4812 = 0x00;
+  r4813 = 0x00;
+  r4814 = 0x00;
+  r4815 = 0x00;
+  r4816 = 0x00;
+  r4817 = 0x00;
+  r4818 = 0x00;
+
+  r481x = 0x00;
+  r4814_latch = false;
+  r4815_latch = false;
+
+  r4820 = 0x00;
+  r4821 = 0x00;
+  r4822 = 0x00;
+  r4823 = 0x00;
+  r4824 = 0x00;
+  r4825 = 0x00;
+  r4826 = 0x00;
+  r4827 = 0x00;
+  r4828 = 0x00;
+  r4829 = 0x00;
+  r482a = 0x00;
+  r482b = 0x00;
+  r482c = 0x00;
+  r482d = 0x00;
+  r482e = 0x00;
+  r482f = 0x00;
+
+  r4830 = 0x00;
+  mmio_write(0x4831, 0);
+  mmio_write(0x4832, 1);
+  mmio_write(0x4833, 2);
+  r4834 = 0x00;
+
+  r4840 = 0x00;
+  r4841 = 0x00;
+  r4842 = 0x00;
+
+  if(cartridge.info.spc7110rtc) {
+    rtc_state = RTCS_Inactive;
+    rtc_mode  = RTCM_Linear;
+    rtc_index = 0;
+  }
+}
+
+unsigned SPC7110::datarom_addr(unsigned addr) {
+  unsigned size = memory::cartrom.size() - 0x100000;
+  while(addr >= size) addr -= size;
+  return addr + 0x100000;
+}
+
+unsigned SPC7110::data_pointer()   { return r4811 + (r4812 << 8) + (r4813 << 16); }
+unsigned SPC7110::data_adjust()    { return r4814 + (r4815 << 8); }
+unsigned SPC7110::data_increment() { return r4816 + (r4817 << 8); }
+void SPC7110::set_data_pointer(unsigned addr) { r4811 = addr; r4812 = addr >> 8; r4813 = addr >> 16; }
+void SPC7110::set_data_adjust(unsigned addr)  { r4814 = addr; r4815 = addr >> 8; }
+
+void SPC7110::update_time(int offset) {
+  time_t rtc_time;
+  rtc_time  = memory::cartrtc.read(16);
+  rtc_time |= memory::cartrtc.read(17) << 8;
+  rtc_time |= memory::cartrtc.read(18) << 16;
+  rtc_time |= memory::cartrtc.read(19) << 24;
+
+  bool update = true;
+  if(memory::cartrtc.read(13) & 1) update = false; //do not update if CR0 timer disable flag is set
+  if(memory::cartrtc.read(15) & 3) update = false; //do not update if CR2 timer disable flags are set
+
+  time_t current_time = time(0) - offset;
+  if(update && current_time > rtc_time) {
+    unsigned second  = memory::cartrtc.read( 0) + memory::cartrtc.read( 1) * 10;
+    unsigned minute  = memory::cartrtc.read( 2) + memory::cartrtc.read( 3) * 10;
+    unsigned hour    = memory::cartrtc.read( 4) + memory::cartrtc.read( 5) * 10;
+    unsigned day     = memory::cartrtc.read( 6) + memory::cartrtc.read( 7) * 10;
+    unsigned month   = memory::cartrtc.read( 8) + memory::cartrtc.read( 9) * 10;
+    unsigned year    = memory::cartrtc.read(10) + memory::cartrtc.read(11) * 10;
+    unsigned weekday = memory::cartrtc.read(12);
+
+    day--;
+    month--;
+    year += (year >= 90) ? 1900 : 2000; //range = 1990-2089
+
+    second += (unsigned)(current_time - rtc_time);
+    while(second >= 60) {
+      second -= 60;
+
+      minute++;
+      if(minute < 60) continue;
+      minute = 0;
+
+      hour++;
+      if(hour < 24) continue;
+      hour = 0;
+
+      day++;
+      weekday = (weekday + 1) % 7;
+      unsigned days = months[month % 12];
+      if(days == 28) {
+        bool leapyear = false;
+        if((year % 4) == 0) {
+          leapyear = true;
+          if((year % 100) == 0 && (year % 400) != 0) leapyear = false;
+        }
+        if(leapyear) days++;
+      }
+      if(day < days) continue;
+      day = 0;
+
+      month++;
+      if(month < 12) continue;
+      month = 0;
+
+      year++;
+    }
+
+    day++;
+    month++;
+    year %= 100;
+
+    memory::cartrtc.write( 0, second % 10);
+    memory::cartrtc.write( 1, second / 10);
+    memory::cartrtc.write( 2, minute % 10);
+    memory::cartrtc.write( 3, minute / 10);
+    memory::cartrtc.write( 4, hour % 10);
+    memory::cartrtc.write( 5, hour / 10);
+    memory::cartrtc.write( 6, day % 10);
+    memory::cartrtc.write( 7, day / 10);
+    memory::cartrtc.write( 8, month % 10);
+    memory::cartrtc.write( 9, month / 10);
+    memory::cartrtc.write(10, year % 10);
+    memory::cartrtc.write(11, (year / 10) % 10);
+    memory::cartrtc.write(12, weekday % 7);
+  }
+
+  memory::cartrtc.write(16, current_time);
+  memory::cartrtc.write(17, current_time >> 8);
+  memory::cartrtc.write(18, current_time >> 16);
+  memory::cartrtc.write(19, current_time >> 24);
+}
+
+uint8 SPC7110::mmio_read(uint addr) {
+  addr &= 0xffff;
+
+  switch(addr) {
+    //==================
+    //decompression unit
+    //==================
+
+    case 0x4800: {
+      uint16 counter = (r4809 + (r480a << 8));
+      counter--;
+      r4809 = counter;
+      r480a = counter >> 8;
+      return decomp.read();
+    }
+    case 0x4801: return r4801;
+    case 0x4802: return r4802;
+    case 0x4803: return r4803;
+    case 0x4804: return r4804;
+    case 0x4805: return r4805;
+    case 0x4806: return r4806;
+    case 0x4807: return r4807;
+    case 0x4808: return r4808;
+    case 0x4809: return r4809;
+    case 0x480a: return r480a;
+    case 0x480b: return r480b;
+    case 0x480c: {
+      uint8 status = r480c;
+      r480c &= 0x7f;
+      return status;
+    }
+
+    //==============
+    //data port unit
+    //==============
+
+    case 0x4810: {
+      if(r481x != 0x07) return 0x00;
+
+      unsigned addr = data_pointer();
+      unsigned adjust = data_adjust();
+      if(r4818 & 8) adjust = (int16)adjust; //16-bit sign extend
+
+      unsigned adjustaddr = addr;
+      if(r4818 & 2) {
+        adjustaddr += adjust;
+        set_data_adjust(adjust + 1);
+      }
+
+      uint8 data = memory::cartrom.read(datarom_addr(adjustaddr));
+      if(!(r4818 & 2)) {
+        unsigned increment = (r4818 & 1) ? data_increment() : 1;
+        if(r4818 & 4) increment = (int16)increment; //16-bit sign extend
+
+        if((r4818 & 16) == 0) {
+          set_data_pointer(addr + increment);
+        } else {
+          set_data_adjust(adjust + increment);
+        }
+      }
+
+      return data;
+    }
+    case 0x4811: return r4811;
+    case 0x4812: return r4812;
+    case 0x4813: return r4813;
+    case 0x4814: return r4814;
+    case 0x4815: return r4815;
+    case 0x4816: return r4816;
+    case 0x4817: return r4817;
+    case 0x4818: return r4818;
+    case 0x481a: {
+      if(r481x != 0x07) return 0x00;
+
+      unsigned addr = data_pointer();
+      unsigned adjust = data_adjust();
+      if(r4818 & 8) adjust = (int16)adjust; //16-bit sign extend
+
+      uint8 data = memory::cartrom.read(datarom_addr(addr + adjust));
+      if((r4818 & 0x60) == 0x60) {
+        if((r4818 & 16) == 0) {
+          set_data_pointer(addr + adjust);
+        } else {
+          set_data_adjust(adjust + adjust);
+        }
+      }
+
+      return data;
+    }
+
+    //=========
+    //math unit
+    //=========
+
+    case 0x4820: return r4820;
+    case 0x4821: return r4821;
+    case 0x4822: return r4822;
+    case 0x4823: return r4823;
+    case 0x4824: return r4824;
+    case 0x4825: return r4825;
+    case 0x4826: return r4826;
+    case 0x4827: return r4827;
+    case 0x4828: return r4828;
+    case 0x4829: return r4829;
+    case 0x482a: return r482a;
+    case 0x482b: return r482b;
+    case 0x482c: return r482c;
+    case 0x482d: return r482d;
+    case 0x482e: return r482e;
+    case 0x482f: {
+      uint8 status = r482f;
+      r482f &= 0x7f;
+      return status;
+    }
+
+    //===================
+    //memory mapping unit
+    //===================
+
+    case 0x4830: return r4830;
+    case 0x4831: return r4831;
+    case 0x4832: return r4832;
+    case 0x4833: return r4833;
+    case 0x4834: return r4834;
+
+    //====================
+    //real-time clock unit
+    //====================
+
+    case 0x4840: return r4840;
+    case 0x4841: {
+      if(rtc_state == RTCS_Inactive || rtc_state == RTCS_ModeSelect) return 0x00;
+
+      r4842 = 0x80;
+      uint8 data = memory::cartrtc.read(rtc_index);
+      rtc_index = (rtc_index + 1) & 15;
+      return data;
+    }
+    case 0x4842: {
+      uint8 status = r4842;
+      r4842 &= 0x7f;
+      return status;
+    }
+  }
+
+  return cpu.regs.mdr;
+}
+
+void SPC7110::mmio_write(uint addr, uint8 data) {
+  addr &= 0xffff;
+
+  switch(addr) {
+    //==================
+    //decompression unit
+    //==================
+
+    case 0x4801: r4801 = data; break;
+    case 0x4802: r4802 = data; break;
+    case 0x4803: r4803 = data; break;
+    case 0x4804: r4804 = data; break;
+    case 0x4805: r4805 = data; break;
+    case 0x4806: {
+      r4806 = data;
+
+      unsigned table   = (r4801 + (r4802 << 8) + (r4803 << 16));
+      unsigned index   = (r4804 << 2);
+      unsigned length  = (r4809 + (r480a << 8));
+      unsigned addr    = datarom_addr(table + index);
+      unsigned mode    = (memory::cartrom.read(addr + 0));
+      unsigned offset  = (memory::cartrom.read(addr + 1) << 16)
+                       + (memory::cartrom.read(addr + 2) <<  8)
+                       + (memory::cartrom.read(addr + 3) <<  0);
+
+      decomp.init(mode, offset, (r4805 + (r4806 << 8)) << mode);
+      r480c = 0x80;
+    } break;
+
+    case 0x4807: r4807 = data; break;
+    case 0x4808: r4808 = data; break;
+    case 0x4809: r4809 = data; break;
+    case 0x480a: r480a = data; break;
+    case 0x480b: r480b = data; break;
+
+    //==============
+    //data port unit
+    //==============
+
+    case 0x4811: r4811 = data; r481x |= 0x01; break;
+    case 0x4812: r4812 = data; r481x |= 0x02; break;
+    case 0x4813: r4813 = data; r481x |= 0x04; break;
+    case 0x4814: {
+      r4814 = data;
+      r4814_latch = true;
+      if(!r4815_latch) break;
+      if(!(r4818 & 2)) break;
+      if(r4818 & 0x10) break;
+
+      if((r4818 & 0x60) == 0x20) {
+        unsigned increment = data_adjust() & 0xff;
+        if(r4818 & 8) increment = (int8)increment; //8-bit sign extend
+        set_data_pointer(data_pointer() + increment);
+      } else if((r4818 & 0x60) == 0x40) {
+        unsigned increment = data_adjust();
+        if(r4818 & 8) increment = (int16)increment; //16-bit sign extend
+        set_data_pointer(data_pointer() + increment);
+      }
+    } break;
+    case 0x4815: {
+      r4815 = data;
+      r4815_latch = true;
+      if(!r4814_latch) break;
+      if(!(r4818 & 2)) break;
+      if(r4818 & 0x10) break;
+
+      if((r4818 & 0x60) == 0x20) {
+        unsigned increment = data_adjust() & 0xff;
+        if(r4818 & 8) increment = (int8)increment; //8-bit sign extend
+        set_data_pointer(data_pointer() + increment);
+      } else if((r4818 & 0x60) == 0x40) {
+        unsigned increment = data_adjust();
+        if(r4818 & 8) increment = (int16)increment; //16-bit sign extend
+        set_data_pointer(data_pointer() + increment);
+      }
+    } break;
+    case 0x4816: r4816 = data; break;
+    case 0x4817: r4817 = data; break;
+    case 0x4818: {
+      if(r481x != 0x07) break;
+
+      r4818 = data;
+      r4814_latch = r4815_latch = false;
+    } break;
+
+    //=========
+    //math unit
+    //=========
+
+    case 0x4820: r4820 = data; break;
+    case 0x4821: r4821 = data; break;
+    case 0x4822: r4822 = data; break;
+    case 0x4823: r4823 = data; break;
+    case 0x4824: r4824 = data; break;
+    case 0x4825: {
+      r4825 = data;
+
+      if(r482e & 1) {
+        //signed 16-bit x 16-bit multiplication
+        int16 r0 = (int16)(r4824 + (r4825 << 8));
+        int16 r1 = (int16)(r4820 + (r4821 << 8));
+
+        signed result = r0 * r1;
+        r4828 = result;
+        r4829 = result >> 8;
+        r482a = result >> 16;
+        r482b = result >> 24;
+      } else {
+        //unsigned 16-bit x 16-bit multiplication
+        uint16 r0 = (uint16)(r4824 + (r4825 << 8));
+        uint16 r1 = (uint16)(r4820 + (r4821 << 8));
+
+        unsigned result = r0 * r1;
+        r4828 = result;
+        r4829 = result >> 8;
+        r482a = result >> 16;
+        r482b = result >> 24;
+      }
+
+      r482f = 0x80;
+    } break;
+    case 0x4826: r4826 = data; break;
+    case 0x4827: {
+      r4827 = data;
+
+      if(r482e & 1) {
+        //signed 32-bit x 16-bit division
+        int32 dividend = (int32)(r4820 + (r4821 << 8) + (r4822 << 16) + (r4823 << 24));
+        int16 divisor  = (int16)(r4826 + (r4827 << 8));
+
+        int32 quotient;
+        int16 remainder;
+
+        if(divisor) {
+          quotient  = (int32)(dividend / divisor);
+          remainder = (int32)(dividend % divisor);
+        } else {
+          //illegal division by zero
+          quotient  = 0;
+          remainder = dividend & 0xffff;
+        }
+
+        r4828 = quotient;
+        r4829 = quotient >> 8;
+        r482a = quotient >> 16;
+        r482b = quotient >> 24;
+
+        r482c = remainder;
+        r482d = remainder >> 8;
+      } else {
+        //unsigned 32-bit x 16-bit division
+        uint32 dividend = (uint32)(r4820 + (r4821 << 8) + (r4822 << 16) + (r4823 << 24));
+        uint16 divisor  = (uint16)(r4826 + (r4827 << 8));
+
+        uint32 quotient;
+        uint16 remainder;
+
+        if(divisor) {
+          quotient  = (uint32)(dividend / divisor);
+          remainder = (uint16)(dividend % divisor);
+        } else {
+          //illegal division by zero
+          quotient  = 0;
+          remainder = dividend & 0xffff;
+        }
+
+        r4828 = quotient;
+        r4829 = quotient >> 8;
+        r482a = quotient >> 16;
+        r482b = quotient >> 24;
+
+        r482c = remainder;
+        r482d = remainder >> 8;
+      }
+
+      r482f = 0x80;
+    } break;
+
+    case 0x482e: {
+      //reset math unit
+      r4820 = r4821 = r4822 = r4823 = 0;
+      r4824 = r4825 = r4826 = r4827 = 0;
+      r4828 = r4829 = r482a = r482b = 0;
+      r482c = r482d = 0;
+
+      r482e = data;
+    } break;
+
+    //===================
+    //memory mapping unit
+    //===================
+
+    case 0x4830: r4830 = data; break;
+
+    case 0x4831: {
+      r4831 = data;
+      dx_offset = datarom_addr((data & 7) * 0x100000);
+    } break;
+
+    case 0x4832: {
+      r4832 = data;
+      ex_offset = datarom_addr((data & 7) * 0x100000);
+    } break;
+
+    case 0x4833: {
+      r4833 = data;
+      fx_offset = datarom_addr((data & 7) * 0x100000);
+    } break;
+
+    case 0x4834: r4834 = data; break;
+
+    //====================
+    //real-time clock unit
+    //====================
+
+    case 0x4840: {
+      r4840 = data;
+      if(!(r4840 & 1)) {
+        //disable RTC
+        rtc_state = RTCS_Inactive;
+        update_time();
+      } else {
+        //enable RTC
+        r4842 = 0x80;
+        rtc_state = RTCS_ModeSelect;
+      }
+    } break;
+
+    case 0x4841: {
+      r4841 = data;
+
+      switch(rtc_state) {
+        case RTCS_ModeSelect: {
+          if(data == RTCM_Linear || data == RTCM_Indexed) {
+            r4842 = 0x80;
+            rtc_state = RTCS_IndexSelect;
+            rtc_mode  = (RTC_Mode)data;
+            rtc_index = 0;
+          }
+        } break;
+
+        case RTCS_IndexSelect: {
+          r4842 = 0x80;
+          rtc_index = data & 15;
+          if(rtc_mode == RTCM_Linear) rtc_state = RTCS_Write;
+        } break;
+
+        case RTCS_Write: {
+          r4842 = 0x80;
+
+          //control register 0
+          if(rtc_index == 13) {
+            //increment second counter
+            if(data & 2) update_time(+1);
+
+            //round minute counter
+            if(data & 8) {
+              update_time();
+
+              unsigned second = memory::cartrtc.read( 0) + memory::cartrtc.read( 1) * 10;
+              //clear seconds
+              memory::cartrtc.write(0, 0);
+              memory::cartrtc.write(1, 0);
+
+              if(second >= 30) update_time(+60);
+            }
+          }
+
+          //control register 2
+          if(rtc_index == 15) {
+            //disable timer and clear second counter
+            if((data & 1) && !(memory::cartrtc.read(15) & 1)) {
+              update_time();
+
+              //clear seconds
+              memory::cartrtc.write(0, 0);
+              memory::cartrtc.write(1, 0);
+            }
+
+            //disable timer
+            if((data & 2) && !(memory::cartrtc.read(15) & 2)) {
+              update_time();
+            }
+          }
+
+          memory::cartrtc.write(rtc_index, data & 15);
+          rtc_index = (rtc_index + 1) & 15;
+        } break;
+      } //switch(rtc_state)
+    } break;
+  }
+}
+
+uint8 SPC7110::read(uint addr) {
+  //$[00-0f|80-8f]:[8000-ffff], $[c0-cf]:[0000-ffff] mapped directly to memory::cartrom
+
+  if((addr & 0xffe000) == 0x006000 || (addr & 0xffe000) == 0x306000) {
+    //$[00|30]:[6000-7fff]
+    return memory::cartram.read(addr & 0x1fff);
+  }
+
+  if((addr & 0xff0000) == 0x500000) {
+    //$[50]:[0000-ffff]
+    return mmio_read(0x4800);
+  }
+
+  if((addr & 0xf00000) == 0xd00000) {
+    //$[d0-df]:[0000-ffff]
+    return memory::cartrom.read(dx_offset + (addr & 0x0fffff));
+  }
+
+  if((addr & 0xf00000) == 0xe00000) {
+    //$[e0-ef]:[0000-ffff]
+    return memory::cartrom.read(ex_offset + (addr & 0x0fffff));
+  }
+
+  if((addr & 0xf00000) == 0xf00000) {
+    //$[f0-ff]:[0000-ffff]
+    return memory::cartrom.read(fx_offset + (addr & 0x0fffff));
+  }
+
+  return cpu.regs.mdr;
+}
+
+void SPC7110::write(uint addr, uint8 data) {
+  if((addr & 0xffe000) == 0x006000 || (addr & 0xffe000) == 0x306000) {
+    //$[00|30]:[6000-7fff]
+    if(r4830 & 0x80) memory::cartram.write(addr & 0x1fff, data);
+    return;
+  }
+}
+
+SPC7110::SPC7110() {
+}
@@ -0,0 +1,133 @@
+/*****
+ * SPC7110 emulator - version 0.03 (2008-08-10)
+ * Copyright (c) 2008, byuu and neviksti
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * The software is provided "as is" and the author disclaims all warranties
+ * with regard to this software including all implied warranties of
+ * merchantibility and fitness, in no event shall the author be liable for
+ * any special, direct, indirect, or consequential damages or any damages
+ * whatsoever resulting from loss of use, data or profits, whether in an
+ * action of contract, negligence or other tortious action, arising out of
+ * or in connection with the use or performance of this software.
+ *****/
+
+#include "decomp.h"
+
+class SPC7110 : public MMIO, public Memory {
+public:
+  void init();
+  void enable();
+  void power();
+  void reset();
+
+  unsigned datarom_addr(unsigned addr);
+
+  unsigned data_pointer();
+  unsigned data_adjust();
+  unsigned data_increment();
+  void set_data_pointer(unsigned addr);
+  void set_data_adjust(unsigned addr);
+
+  void update_time(int offset = 0);
+  time_t create_time();
+
+  uint8 mmio_read (uint addr);
+  void  mmio_write(uint addr, uint8 data);
+
+  uint8 read (uint addr);
+  void  write(uint addr, uint8 data);
+
+  //spc7110decomp
+  void decomp_init();
+  uint8 decomp_read();
+
+  SPC7110();
+
+private:
+  //==================
+  //decompression unit
+  //==================
+  uint8 r4801; //compression table low
+  uint8 r4802; //compression table high
+  uint8 r4803; //compression table bank
+  uint8 r4804; //compression table index
+  uint8 r4805; //decompression buffer index low
+  uint8 r4806; //decompression buffer index high
+  uint8 r4807; //???
+  uint8 r4808; //???
+  uint8 r4809; //compression length low
+  uint8 r480a; //compression length high
+  uint8 r480b; //decompression control register
+  uint8 r480c; //decompression status
+
+  SPC7110Decomp decomp;
+
+  //==============
+  //data port unit
+  //==============
+  uint8 r4811; //data pointer low
+  uint8 r4812; //data pointer high
+  uint8 r4813; //data pointer bank
+  uint8 r4814; //data adjust low
+  uint8 r4815; //data adjust high
+  uint8 r4816; //data increment low
+  uint8 r4817; //data increment high
+  uint8 r4818; //data port control register
+
+  uint8 r481x;
+
+  bool r4814_latch;
+  bool r4815_latch;
+
+  //=========
+  //math unit
+  //=========
+  uint8 r4820; //16-bit multiplicand B0, 32-bit dividend B0
+  uint8 r4821; //16-bit multiplicand B1, 32-bit dividend B1
+  uint8 r4822; //32-bit dividend B2
+  uint8 r4823; //32-bit dividend B3
+  uint8 r4824; //16-bit multiplier B0
+  uint8 r4825; //16-bit multiplier B1
+  uint8 r4826; //16-bit divisor B0
+  uint8 r4827; //16-bit divisor B1
+  uint8 r4828; //32-bit product B0, 32-bit quotient B0
+  uint8 r4829; //32-bit product B1, 32-bit quotient B1
+  uint8 r482a; //32-bit product B2, 32-bit quotient B2
+  uint8 r482b; //32-bit product B3, 32-bit quotient B3
+  uint8 r482c; //16-bit remainder B0
+  uint8 r482d; //16-bit remainder B1
+  uint8 r482e; //math control register
+  uint8 r482f; //math status
+
+  //===================
+  //memory mapping unit
+  //===================
+  uint8 r4830; //SRAM write enable
+  uint8 r4831; //$[d0-df]:[0000-ffff] mapping
+  uint8 r4832; //$[e0-ef]:[0000-ffff] mapping
+  uint8 r4833; //$[f0-ff]:[0000-ffff] mapping
+  uint8 r4834; //???
+
+  unsigned dx_offset;
+  unsigned ex_offset;
+  unsigned fx_offset;
+
+  //====================
+  //real-time clock unit
+  //====================
+  uint8 r4840; //RTC latch
+  uint8 r4841; //RTC index/data port
+  uint8 r4842; //RTC status
+
+  enum RTC_State { RTCS_Inactive, RTCS_ModeSelect, RTCS_IndexSelect, RTCS_Write } rtc_state;
+  enum RTC_Mode  { RTCM_Linear = 0x03, RTCM_Indexed = 0x0c } rtc_mode;
+  unsigned rtc_index;
+
+  static const unsigned months[12];
+};
+
+extern SPC7110 spc7110;
@@ -1,191 +1,213 @@
-/*
-  S-RTC chip emulation
-  Used by Hudson Soft in Dai Kaijuu Monogatari II and Far East of Eden Zero.
-  Currently, only the former is supported by bsnes.
-
-  Original S-RTC emulation code via John Weidman/SNES9x
-  Rewritten for compatibility with bsnes via byuu
-
-  The S-RTC is a real-time clock chip that was added to the above two carts
-  to allow the games to maintain the current time, even when the game was not
-  powered on. Thus allowing special events at certain times, and on certain
-  dates. Hudson Soft called this the PLG (Player's Life Gameplay System).
-
-  This chip is a special case to the term 'emulation' itself.
-  There are a few different ways to go about emulating this chip, and each
-  result in a different style of emulation.
-
-  The first is to simply return the current PC system time when the S-RTC is
-  read from. This emulates the original S-RTC in the sense that it always
-  returns the true current time, ignoring the speed that the SNES itself is
-  running at. The downside to this method is that you lose the ability to set
-  the time to whatever you choose inside the game itself. It will always return
-  the true time, regardless. This can be overcome by changing the PC system time,
-  which actually adds a greater degree of control over event timing, very useful
-  for emulation. It also has a timeshifting flaw discussed below.
-
-  The second is to run the S-RTC relative to the SNES speed. This means that
-  if the emulator is sped up (via fast forward key, frameskipping, etc), or
-  slowed down (via slowdown key, system bottlenecking, etc); the time increments
-  slower, thus ~60 frames on the SNES equal one second. Without this, timeshifting
-  will occur between the S-RTC and the real SNES.
-
-  The third and final method is to save a copy of the local system time when the
-  S-RTC is initially set, and compare the current system time against this value
-  when setting the S-RTC time. This overcomes the first methods' shortcoming of
-  not allowing the player to set the time in-game, however a new problem arises.
-  You now have to save the time when the RTC was initially set to both savestates
-  and to save-game data. This would require an extra file, or the breaking of
-  perhaps the only standard format (.srm savegame backups) in the entire SNES
-  emulation scene. You also give up the control of being able to override the
-  RTC clock at will via the PC system time outside of emulation.
-  The first method has another advantage over the third: Dai Kaijuu Monogatari II
-  only allows dates in the range of the years 1996-2199. The first method gets
-  around this limitation. But who knows, maybe it will break something in the
-  game if the date exceeds 2199... I guess we'll worry about that in two hundred
-  years from now.
-
-  For my implementation, I chose to go with the first method. Both for simplicity
-  and because I did not wish to create a new method for saving the system time
-  whenever the RTC is set.
-*/
-
-#include "../../base.h"
-
-SRTC *srtc;
-
-void SRTC::set_time() {
-time_t rawtime;
-tm *t;
-  ::time(&rawtime);
-  t = localtime(&rawtime);
-
-//see srtc.h for format of srtc.data[]
-  srtc.data[0]  = t->tm_sec % 10;
-  srtc.data[1]  = t->tm_sec / 10;
-  srtc.data[2]  = t->tm_min % 10;
-  srtc.data[3]  = t->tm_min / 10;
-  srtc.data[4]  = t->tm_hour % 10;
-  srtc.data[5]  = t->tm_hour / 10;
-  srtc.data[6]  = t->tm_mday % 10;
-  srtc.data[7]  = t->tm_mday / 10;
-  srtc.data[8]  = t->tm_mon + 1;
-  srtc.data[9]  = t->tm_year % 10;
-  srtc.data[10] = (t->tm_year / 10) % 10;
-  srtc.data[11] = 9 + (t->tm_year / 100);
-  srtc.data[12] = t->tm_wday;
-}
-
-void SRTC::init() {}
-
-void SRTC::enable() {
-  r_mem->set_mmio_mapper(0x2800, this);
-  r_mem->set_mmio_mapper(0x2801, this);
-}
-
-void SRTC::power() {
-  memset(&srtc, 0, sizeof(srtc));
-  reset();
-}
-
-void SRTC::reset() {
-  srtc.index = -1;
-  srtc.mode  = SRTC_READ;
-}
-
-uint8 SRTC::mmio_read(uint16 addr) {
-  switch(addr) {
-
-  case 0x2800: {
-    if(srtc.mode == SRTC_READ) {
-      if(srtc.index < 0) {
-        set_time();
-        srtc.index++;
-        return 0x0f; //send start message
-      } else if(srtc.index > MAX_SRTC_INDEX) {
-        srtc.index = -1;
-        return 0x0f; //send finished message
-      } else {
-        return srtc.data[srtc.index++];
-      }
-    } else {
-      return 0x00;
-    }
-  } break;
-
-  case 0x2801: {
-  } break;
-
-  }
-
-  return r_cpu->regs.mdr;
-}
-
-//Please see notes above about the implementation of the S-RTC
-//Writes are stored the srtc.data[] array, but they are ignored
-//as reads will refresh the data array with the current system
-//time. The write method is only here for the sake of faux
-//emulation of the real hardware.
-void SRTC::mmio_write(uint16 addr, uint8 data) {
-  switch(addr) {
-
-  case 0x2800: {
-  } break;
-
-  case 0x2801: {
-    data &= 0x0f; //only the low four bits are used
-
-    if(data >= 0x0d) {
-      switch(data) {
-      case 0x0d:
-        srtc.mode  = SRTC_READ;
-        srtc.index = -1;
-        break;
-      case 0x0e:
-        srtc.mode = SRTC_COMMAND;
-        break;
-      case 0x0f:
-      //unknown behaviour
-        break;
-      }
-      return;
-    }
-
-    if(srtc.mode == SRTC_WRITE) {
-      if(srtc.index >= 0 && srtc.index < MAX_SRTC_INDEX) {
-        srtc.data[srtc.index++] = data;
-
-        if(srtc.index == MAX_SRTC_INDEX) {
-        //all S-RTC data has been loaded by program
-          srtc.data[srtc.index++] = 0x00; //day_of_week
-        }
-      }
-    } else if(srtc.mode == SRTC_COMMAND) {
-      switch(data) {
-      case SRTC_COMMAND_CLEAR:
-        memset(srtc.data, 0, MAX_SRTC_INDEX + 1);
-        srtc.index = -1;
-        srtc.mode  = SRTC_READY;
-        break;
-      case SRTC_COMMAND_WRITE:
-        srtc.index = 0;
-        srtc.mode  = SRTC_WRITE;
-        break;
-      default:
-      //unknown behaviour
-        srtc.mode  = SRTC_READY;
-        break;
-      }
-    } else {
-      if(srtc.mode == SRTC_READ) {
-      //ignore writes while in read mode
-      } else if(srtc.mode == SRTC_READY) {
-      //unknown behaviour
-      }
-    }
-  } break;
-
-  }
-}
-
-SRTC::SRTC() {}
+#include "../../base.h"
+
+const unsigned SRTC::months[12] = { 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 };
+
+void SRTC::init() {
+}
+
+void SRTC::enable() {
+  memory::mmio.map(0x2800, *this);
+  memory::mmio.map(0x2801, *this);
+}
+
+void SRTC::power() {
+  reset();
+}
+
+void SRTC::reset() {
+  rtc_mode = RTCM_Read;
+  rtc_index = -1;
+  update_time();
+}
+
+void SRTC::update_time() {
+  time_t rtc_time;
+  rtc_time  = memory::cartrtc.read(16);
+  rtc_time |= memory::cartrtc.read(17) << 8;
+  rtc_time |= memory::cartrtc.read(18) << 16;
+  rtc_time |= memory::cartrtc.read(19) << 24;
+
+  time_t current_time = time(0);
+  if(current_time > rtc_time) {
+    unsigned second  = memory::cartrtc.read( 0) + memory::cartrtc.read( 1) * 10;
+    unsigned minute  = memory::cartrtc.read( 2) + memory::cartrtc.read( 3) * 10;
+    unsigned hour    = memory::cartrtc.read( 4) + memory::cartrtc.read( 5) * 10;
+    unsigned day     = memory::cartrtc.read( 6) + memory::cartrtc.read( 7) * 10;
+    unsigned month   = memory::cartrtc.read( 8);
+    unsigned year    = memory::cartrtc.read( 9) + memory::cartrtc.read(10) * 10 + memory::cartrtc.read(11) * 100;
+    unsigned weekday = memory::cartrtc.read(12);
+
+    day--;
+    month--;
+    year += 1000;
+
+    second += (unsigned)(current_time - rtc_time);
+
+    while(second >= 60) {
+      second -= 60;
+
+      minute++;
+      if(minute < 60) continue;
+      minute = 0;
+
+      hour++;
+      if(hour < 24) continue;
+      hour = 0;
+
+      day++;
+      weekday = (weekday + 1) % 7;
+      unsigned days = months[month % 12];
+      if(days == 28) {
+        bool leapyear = false;
+        if((year % 4) == 0) {
+          leapyear = true;
+          if((year % 100) == 0 && (year % 400) != 0) leapyear = false;
+        }
+        if(leapyear) days++;
+      }
+      if(day < days) continue;
+      day = 0;
+
+      month++;
+      if(month < 12) continue;
+      month = 0;
+
+      year++;
+    }
+
+    day++;
+    month++;
+    year -= 1000;
+
+    memory::cartrtc.write( 0, second % 10);
+    memory::cartrtc.write( 1, second / 10);
+    memory::cartrtc.write( 2, minute % 10);
+    memory::cartrtc.write( 3, minute / 10);
+    memory::cartrtc.write( 4, hour % 10);
+    memory::cartrtc.write( 5, hour / 10);
+    memory::cartrtc.write( 6, day % 10);
+    memory::cartrtc.write( 7, day / 10);
+    memory::cartrtc.write( 8, month);
+    memory::cartrtc.write( 9, year % 10);
+    memory::cartrtc.write(10, (year / 10) % 10);
+    memory::cartrtc.write(11, year / 100);
+    memory::cartrtc.write(12, weekday % 7);
+  }
+
+  memory::cartrtc.write(16, current_time);
+  memory::cartrtc.write(17, current_time >> 8);
+  memory::cartrtc.write(18, current_time >> 16);
+  memory::cartrtc.write(19, current_time >> 24);
+}
+
+//returns day of week for specified date
+//eg 0 = Sunday, 1 = Monday, ... 6 = Saturday
+//usage: weekday(2008, 1, 1) returns weekday of January 1st, 2008
+unsigned SRTC::weekday(unsigned year, unsigned month, unsigned day) {
+  unsigned y = 1900, m = 1; //epoch is 1900-01-01
+  unsigned sum = 0; //number of days passed since epoch
+
+  year = max(1900, year);
+  month = max(1, min(12, month));
+  day = max(1, min(31, day));
+
+  while(y < year) {
+    bool leapyear = false;
+    if((y % 4) == 0) {
+      leapyear = true;
+      if((y % 100) == 0 && (y % 400) != 0) leapyear = false;
+    }
+    sum += leapyear ? 366 : 365;
+    y++;
+  }
+
+  while(m < month) {
+    unsigned days = months[m - 1];
+    if(days == 28) {
+      bool leapyear = false;
+      if((y % 4) == 0) {
+        leapyear = true;
+        if((y % 100) == 0 && (y % 400) != 0) leapyear = false;
+      }
+      if(leapyear) days++;
+    }
+    sum += days;
+    m++;
+  }
+
+  sum += day - 1;
+  return (sum + 1) % 7; //1900-01-01 was a Monday
+}
+
+uint8 SRTC::mmio_read(uint addr) {
+  addr &= 0xffff;
+
+  if(addr == 0x2800) {
+    if(rtc_mode != RTCM_Read) return 0x00;
+
+    if(rtc_index < 0) {
+      update_time();
+      rtc_index++;
+      return 0x0f;
+    } else if(rtc_index > 12) {
+      rtc_index = -1;
+      return 0x0f;
+    } else {
+      return memory::cartrtc.read(rtc_index++);
+    }
+  }
+
+  return cpu.regs.mdr;
+}
+
+void SRTC::mmio_write(uint addr, uint8 data) {
+  addr &= 0xffff;
+
+  if(addr == 0x2801) {
+    data &= 0x0f; //only the low four bits are used
+
+    if(data == 0x0d) {
+      rtc_mode = RTCM_Read;
+      rtc_index = -1;
+      return;
+    }
+
+    if(data == 0x0e) {
+      rtc_mode = RTCM_Command;
+      return;
+    }
+
+    if(data == 0x0f) return; //unknown behavior
+
+    if(rtc_mode == RTCM_Write) {
+      if(rtc_index >= 0 && rtc_index < 12) {
+        memory::cartrtc.write(rtc_index++, data);
+
+        if(rtc_index == 12) {
+          //day of week is automatically calculated and written
+          unsigned day   = memory::cartrtc.read( 6) + memory::cartrtc.read( 7) * 10;
+          unsigned month = memory::cartrtc.read( 8);
+          unsigned year  = memory::cartrtc.read( 9) + memory::cartrtc.read(10) * 10 + memory::cartrtc.read(11) * 100;
+          year += 1000;
+
+          memory::cartrtc.write(rtc_index++, weekday(year, month, day));
+        }
+      }
+    } else if(rtc_mode == RTCM_Command) {
+      if(data == 0) {
+        rtc_mode = RTCM_Write;
+        rtc_index = 0;
+      } else if(data == 4) {
+        rtc_mode = RTCM_Ready;
+        rtc_index = -1;
+        for(unsigned i = 0; i < 13; i++) memory::cartrtc.write(i, 0);
+      } else {
+        //unknown behavior
+        rtc_mode = RTCM_Ready;
+      }
+    }
+  }
+}
+
+SRTC::SRTC() {
+}
@@ -1,52 +1,22 @@
-class SRTC : public MMIO {
-public:
-enum { MAX_SRTC_INDEX = 0x0c };
-
-enum {
-  SRTC_READ = 0,
-  SRTC_WRITE,
-  SRTC_COMMAND,
-  SRTC_READY
-};
-
-enum {
-  SRTC_COMMAND_WRITE = 0,
-  SRTC_COMMAND_CLEAR = 4
-};
-
-/******************************
-[srtc.data structure]
-Index  Description   Range
-----  -----------   -----
-    0  Seconds low   0-9
-    1  Seconds high  0-5
-    2  Minutes low   0-9
-    3  Minutes high  0-5
-    4  Hour low      0-9
-    5  Hour high     0-2
-    6  Day low       0-9
-    7  Day high      0-3
-    8  Month         1-12
-    9  Year ones     0-9
-   10  Year tens     0-9
-   11  Year hundreds 9-11 (9=19xx, 10=20xx, 11=21xx)
-   12  Day of week   0-6  (0=Sunday, ...)
-******************************/
-struct {
-  int8  index;
-  uint8 mode;
-  uint8 data[MAX_SRTC_INDEX + 1];
-} srtc;
-  void  set_time();
-  void  init();
-  void  enable();
-  void  power();
-  void  reset();
-
-  uint8 mmio_read (uint16 addr);
-  void  mmio_write(uint16 addr, uint8 data);
-
-  SRTC();
-};
-
-extern SRTC *srtc;
+class SRTC : public MMIO {
+public:
+  void update_time();
+  unsigned weekday(unsigned year, unsigned month, unsigned day);
+
+  void init();
+  void enable();
+  void power();
+  void reset();
+
+  uint8 mmio_read (uint addr);
+  void  mmio_write(uint addr, uint8 data);
+
+  SRTC();
+
+private:
+  static const unsigned months[12];
+  enum RTC_Mode { RTCM_Ready, RTCM_Command, RTCM_Read, RTCM_Write } rtc_mode;
+  signed rtc_index;
+};
+
+extern SRTC srtc;
@@ -0,0 +1,86 @@
+#include "../../base.h"
+#define ST010_CPP
+
+#include "st010_data.h"
+#include "st010_op.cpp"
+
+int16 ST010::sin(int16 theta) {
+  return sin_table[(theta >> 8) & 0xff];
+}
+
+int16 ST010::cos(int16 theta) {
+  return sin_table[((theta + 0x4000) >> 8) & 0xff];
+}
+
+uint8 ST010::readb(uint16 addr) {
+  return ram[addr & 0xfff];
+}
+
+uint16 ST010::readw(uint16 addr) {
+  return (readb(addr + 0) <<  0) |
+         (readb(addr + 1) <<  8);
+}
+
+uint32 ST010::readd(uint16 addr) {
+  return (readb(addr + 0) <<  0) |
+         (readb(addr + 1) <<  8) |
+         (readb(addr + 2) << 16) |
+         (readb(addr + 3) << 24);
+}
+
+void ST010::writeb(uint16 addr, uint8 data) {
+  ram[addr & 0xfff] = data;
+}
+
+void ST010::writew(uint16 addr, uint16 data) {
+  writeb(addr + 0, data);
+  writeb(addr + 1, data >> 8);
+}
+
+void ST010::writed(uint16 addr, uint32 data) {
+  writeb(addr + 0, data);
+  writeb(addr + 1, data >> 8);
+  writeb(addr + 2, data >> 16);
+  writeb(addr + 3, data >> 24);
+}
+
+//
+
+void ST010::init() {
+}
+
+void ST010::enable() {
+}
+
+void ST010::power() {
+  reset();
+}
+
+void ST010::reset() {
+  memset(ram, 0x00, sizeof ram);
+}
+
+//
+
+uint8 ST010::read(uint addr) {
+  return readb(addr);
+}
+
+void ST010::write(uint addr, uint8 data) {
+  writeb(addr, data);
+
+  if((addr & 0xfff) == 0x0021 && (data & 0x80)) {
+    switch(ram[0x0020]) {
+      case 0x01: op_01(); break;
+      case 0x02: op_02(); break;
+      case 0x03: op_03(); break;
+      case 0x04: op_04(); break;
+      case 0x05: op_05(); break;
+      case 0x06: op_06(); break;
+      case 0x07: op_07(); break;
+      case 0x08: op_08(); break;
+    }
+
+    ram[0x0021] &= ~0x80;
+  }
+}
@@ -0,0 +1,42 @@
+class ST010 : public Memory {
+public:
+  void init();
+  void enable();
+  void power();
+  void reset();
+
+  uint8 read (uint addr);
+  void  write(uint addr, uint8 data);
+
+private:
+  uint8 ram[0x1000];
+  static const int16 sin_table[256];
+  static const int16 mode7_scale[176];
+  static const uint8 arctan[32][32];
+
+//interfaces to sin table
+  int16 sin(int16 theta);
+  int16 cos(int16 theta);
+
+//interfaces to ram buffer
+  uint8  readb (uint16 addr);
+  uint16 readw (uint16 addr);
+  uint32 readd (uint16 addr);
+  void   writeb(uint16 addr, uint8  data);
+  void   writew(uint16 addr, uint16 data);
+  void   writed(uint16 addr, uint32 data);
+
+//opcodes
+  void op_01();
+  void op_02();
+  void op_03();
+  void op_04();
+  void op_05();
+  void op_06();
+  void op_07();
+  void op_08();
+
+  void op_01(int16 x0, int16 y0, int16 &x1, int16 &y1, int16 &quadrant, int16 &theta);
+};
+
+extern ST010 st010;
@@ -0,0 +1,126 @@
+const int16 ST010::sin_table[256] = {
+   0x0000,  0x0324,  0x0648,  0x096a,  0x0c8c,  0x0fab,  0x12c8,  0x15e2,
+   0x18f9,  0x1c0b,  0x1f1a,  0x2223,  0x2528,  0x2826,  0x2b1f,  0x2e11,
+   0x30fb,  0x33df,  0x36ba,  0x398c,  0x3c56,  0x3f17,  0x41ce,  0x447a,
+   0x471c,  0x49b4,  0x4c3f,  0x4ebf,  0x5133,  0x539b,  0x55f5,  0x5842,
+   0x5a82,  0x5cb3,  0x5ed7,  0x60eb,  0x62f1,  0x64e8,  0x66cf,  0x68a6,
+   0x6a6d,  0x6c23,  0x6dc9,  0x6f5e,  0x70e2,  0x7254,  0x73b5,  0x7504,
+   0x7641,  0x776b,  0x7884,  0x7989,  0x7a7c,  0x7b5c,  0x7c29,  0x7ce3,
+   0x7d89,  0x7e1d,  0x7e9c,  0x7f09,  0x7f61,  0x7fa6,  0x7fd8,  0x7ff5,
+   0x7fff,  0x7ff5,  0x7fd8,  0x7fa6,  0x7f61,  0x7f09,  0x7e9c,  0x7e1d,
+   0x7d89,  0x7ce3,  0x7c29,  0x7b5c,  0x7a7c,  0x7989,  0x7884,  0x776b,
+   0x7641,  0x7504,  0x73b5,  0x7254,  0x70e2,  0x6f5e,  0x6dc9,  0x6c23,
+   0x6a6d,  0x68a6,  0x66cf,  0x64e8,  0x62f1,  0x60eb,  0x5ed7,  0x5cb3,
+   0x5a82,  0x5842,  0x55f5,  0x539b,  0x5133,  0x4ebf,  0x4c3f,  0x49b4,
+   0x471c,  0x447a,  0x41ce,  0x3f17,  0x3c56,  0x398c,  0x36ba,  0x33df,
+   0x30fb,  0x2e11,  0x2b1f,  0x2826,  0x2528,  0x2223,  0x1f1a,  0x1c0b,
+   0x18f8,  0x15e2,  0x12c8,  0x0fab,  0x0c8c,  0x096a,  0x0648,  0x0324,
+   0x0000, -0x0324, -0x0648, -0x096b, -0x0c8c, -0x0fab, -0x12c8, -0x15e2,
+  -0x18f9, -0x1c0b, -0x1f1a, -0x2223, -0x2528, -0x2826, -0x2b1f, -0x2e11,
+  -0x30fb, -0x33df, -0x36ba, -0x398d, -0x3c56, -0x3f17, -0x41ce, -0x447a,
+  -0x471c, -0x49b4, -0x4c3f, -0x4ebf, -0x5133, -0x539b, -0x55f5, -0x5842,
+  -0x5a82, -0x5cb3, -0x5ed7, -0x60ec, -0x62f1, -0x64e8, -0x66cf, -0x68a6,
+  -0x6a6d, -0x6c23, -0x6dc9, -0x6f5e, -0x70e2, -0x7254, -0x73b5, -0x7504,
+  -0x7641, -0x776b, -0x7884, -0x7989, -0x7a7c, -0x7b5c, -0x7c29, -0x7ce3,
+  -0x7d89, -0x7e1d, -0x7e9c, -0x7f09, -0x7f61, -0x7fa6, -0x7fd8, -0x7ff5,
+  -0x7fff, -0x7ff5, -0x7fd8, -0x7fa6, -0x7f61, -0x7f09, -0x7e9c, -0x7e1d,
+  -0x7d89, -0x7ce3, -0x7c29, -0x7b5c, -0x7a7c, -0x7989, -0x7883, -0x776b,
+  -0x7641, -0x7504, -0x73b5, -0x7254, -0x70e2, -0x6f5e, -0x6dc9, -0x6c23,
+  -0x6a6d, -0x68a6, -0x66cf, -0x64e8, -0x62f1, -0x60eb, -0x5ed7, -0x5cb3,
+  -0x5a82, -0x5842, -0x55f5, -0x539a, -0x5133, -0x4ebf, -0x4c3f, -0x49b3,
+  -0x471c, -0x447a, -0x41cd, -0x3f17, -0x3c56, -0x398c, -0x36b9, -0x33de,
+  -0x30fb, -0x2e10, -0x2b1f, -0x2826, -0x2527, -0x2223, -0x1f19, -0x1c0b,
+  -0x18f8, -0x15e2, -0x12c8, -0x0fab, -0x0c8b, -0x096a, -0x0647, -0x0324
+};
+
+const int16 ST010::mode7_scale[176] = {
+  0x0380,  0x0325,  0x02da,  0x029c,  0x0268,  0x023b,  0x0215,  0x01f3,
+  0x01d5,  0x01bb,  0x01a3,  0x018e,  0x017b,  0x016a,  0x015a,  0x014b,
+  0x013e,  0x0132,  0x0126,  0x011c,  0x0112,  0x0109,  0x0100,  0x00f8,
+  0x00f0,  0x00e9,  0x00e3,  0x00dc,  0x00d6,  0x00d1,  0x00cb,  0x00c6,
+  0x00c1,  0x00bd,  0x00b8,  0x00b4,  0x00b0,  0x00ac,  0x00a8,  0x00a5,
+  0x00a2,  0x009e,  0x009b,  0x0098,  0x0095,  0x0093,  0x0090,  0x008d,
+  0x008b,  0x0088,  0x0086,  0x0084,  0x0082,  0x0080,  0x007e,  0x007c,
+  0x007a,  0x0078,  0x0076,  0x0074,  0x0073,  0x0071,  0x006f,  0x006e,
+  0x006c,  0x006b,  0x0069,  0x0068,  0x0067,  0x0065,  0x0064,  0x0063,
+  0x0062,  0x0060,  0x005f,  0x005e,  0x005d,  0x005c,  0x005b,  0x005a,
+  0x0059,  0x0058,  0x0057,  0x0056,  0x0055,  0x0054,  0x0053,  0x0052,
+  0x0051,  0x0051,  0x0050,  0x004f,  0x004e,  0x004d,  0x004d,  0x004c,
+  0x004b,  0x004b,  0x004a,  0x0049,  0x0048,  0x0048,  0x0047,  0x0047,
+  0x0046,  0x0045,  0x0045,  0x0044,  0x0044,  0x0043,  0x0042,  0x0042,
+  0x0041,  0x0041,  0x0040,  0x0040,  0x003f,  0x003f,  0x003e,  0x003e,
+  0x003d,  0x003d,  0x003c,  0x003c,  0x003b,  0x003b,  0x003a,  0x003a,
+  0x003a,  0x0039,  0x0039,  0x0038,  0x0038,  0x0038,  0x0037,  0x0037,
+  0x0036,  0x0036,  0x0036,  0x0035,  0x0035,  0x0035,  0x0034,  0x0034,
+  0x0034,  0x0033,  0x0033,  0x0033,  0x0032,  0x0032,  0x0032,  0x0031,
+  0x0031,  0x0031,  0x0030,  0x0030,  0x0030,  0x0030,  0x002f,  0x002f,
+  0x002f,  0x002e,  0x002e,  0x002e,  0x002e,  0x002d,  0x002d,  0x002d,
+  0x002d,  0x002c,  0x002c,  0x002c,  0x002c,  0x002b,  0x002b,  0x002b
+};
+
+const uint8 ST010::arctan[32][32] = {
+  { 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+    0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80 },
+  { 0x80, 0xa0, 0xad, 0xb3, 0xb6, 0xb8, 0xb9, 0xba, 0xbb, 0xbb, 0xbc, 0xbc, 0xbd, 0xbd, 0xbd, 0xbd,
+    0xbd, 0xbe, 0xbe, 0xbe, 0xbe, 0xbe, 0xbe, 0xbe, 0xbe, 0xbe, 0xbe, 0xbe, 0xbf, 0xbf, 0xbf, 0xbf },
+  { 0x80, 0x93, 0xa0, 0xa8, 0xad, 0xb0, 0xb3, 0xb5, 0xb6, 0xb7, 0xb8, 0xb9, 0xb9, 0xba, 0xba, 0xbb,
+    0xbb, 0xbb, 0xbb, 0xbc, 0xbc, 0xbc, 0xbc, 0xbc, 0xbd, 0xbd, 0xbd, 0xbd, 0xbd, 0xbd, 0xbd, 0xbd },
+  { 0x80, 0x8d, 0x98, 0xa0, 0xa6, 0xaa, 0xad, 0xb0, 0xb1, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7, 0xb7, 0xb8,
+    0xb8, 0xb9, 0xb9, 0xba, 0xba, 0xba, 0xba, 0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0xbc, 0xbc, 0xbc, 0xbc },
+  { 0x80, 0x8a, 0x93, 0x9a, 0xa0, 0xa5, 0xa8, 0xab, 0xad, 0xaf, 0xb0, 0xb2, 0xb3, 0xb4, 0xb5, 0xb5,
+    0xb6, 0xb7, 0xb7, 0xb8, 0xb8, 0xb8, 0xb9, 0xb9, 0xb9, 0xba, 0xba, 0xba, 0xba, 0xba, 0xbb, 0xbb },
+  { 0x80, 0x88, 0x90, 0x96, 0x9b, 0xa0, 0xa4, 0xa7, 0xa9, 0xab, 0xad, 0xaf, 0xb0, 0xb1, 0xb2, 0xb3,
+    0xb4, 0xb4, 0xb5, 0xb6, 0xb6, 0xb6, 0xb7, 0xb7, 0xb8, 0xb8, 0xb8, 0xb9, 0xb9, 0xb9, 0xb9, 0xb9 },
+  { 0x80, 0x87, 0x8d, 0x93, 0x98, 0x9c, 0xa0, 0xa3, 0xa6, 0xa8, 0xaa, 0xac, 0xad, 0xae, 0xb0, 0xb0,
+    0xb1, 0xb2, 0xb3, 0xb4, 0xb4, 0xb5, 0xb5, 0xb6, 0xb6, 0xb6, 0xb7, 0xb7, 0xb7, 0xb8, 0xb8, 0xb8 },
+  { 0x80, 0x86, 0x8b, 0x90, 0x95, 0x99, 0x9d, 0xa0, 0xa3, 0xa5, 0xa7, 0xa9, 0xaa, 0xac, 0xad, 0xae,
+    0xaf, 0xb0, 0xb1, 0xb2, 0xb2, 0xb3, 0xb3, 0xb4, 0xb4, 0xb5, 0xb5, 0xb6, 0xb6, 0xb6, 0xb7, 0xb7 },
+  { 0x80, 0x85, 0x8a, 0x8f, 0x93, 0x97, 0x9a, 0x9d, 0xa0, 0xa2, 0xa5, 0xa6, 0xa8, 0xaa, 0xab, 0xac,
+    0xad, 0xae, 0xaf, 0xb0, 0xb0, 0xb1, 0xb2, 0xb2, 0xb3, 0xb3, 0xb4, 0xb4, 0xb5, 0xb5, 0xb5, 0xb5 },
+  { 0x80, 0x85, 0x89, 0x8d, 0x91, 0x95, 0x98, 0x9b, 0x9e, 0xa0, 0xa0, 0xa4, 0xa6, 0xa7, 0xa9, 0xaa,
+    0xab, 0xac, 0xad, 0xae, 0xaf, 0xb0, 0xb0, 0xb1, 0xb1, 0xb2, 0xb2, 0xb3, 0xb3, 0xb4, 0xb4, 0xb4 },
+  { 0x80, 0x84, 0x88, 0x8c, 0x90, 0x93, 0x96, 0x99, 0x9b, 0x9e, 0xa0, 0xa2, 0xa4, 0xa5, 0xa7, 0xa8,
+    0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf, 0xaf, 0xb0, 0xb0, 0xb1, 0xb2, 0xb2, 0xb2, 0xb3, 0xb3 },
+  { 0x80, 0x84, 0x87, 0x8b, 0x8e, 0x91, 0x94, 0x97, 0x9a, 0x9c, 0x9e, 0xa0, 0xa2, 0xa3, 0xa5, 0xa6,
+    0xa7, 0xa9, 0xaa, 0xab, 0xac, 0xac, 0xad, 0xae, 0xae, 0xaf, 0xb0, 0xb0, 0xb1, 0xb1, 0xb2, 0xb2 },
+  { 0x80, 0x83, 0x87, 0x8a, 0x8d, 0x90, 0x93, 0x96, 0x98, 0x9a, 0x9c, 0x9e, 0xa0, 0xa2, 0xa3, 0xa5,
+    0xa6, 0xa7, 0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xac, 0xad, 0xae, 0xae, 0xaf, 0xb0, 0xb0, 0xb0, 0xb1 },
+  { 0x80, 0x83, 0x86, 0x89, 0x8c, 0x8f, 0x92, 0x94, 0x96, 0x99, 0x9b, 0x9d, 0x9e, 0xa0, 0xa2, 0xa3,
+    0xa4, 0xa5, 0xa7, 0xa8, 0xa9, 0xa9, 0xaa, 0xab, 0xac, 0xac, 0xad, 0xae, 0xae, 0xaf, 0xaf, 0xb0 },
+  { 0x80, 0x83, 0x86, 0x89, 0x8b, 0x8e, 0x90, 0x93, 0x95, 0x97, 0x99, 0x9b, 0x9d, 0x9e, 0xa0, 0xa1,
+    0xa3, 0xa4, 0xa5, 0xa6, 0xa7, 0xa8, 0xa9, 0xaa, 0xaa, 0xab, 0xac, 0xad, 0xad, 0xae, 0xae, 0xaf },
+  { 0x80, 0x83, 0x85, 0x88, 0x8b, 0x8d, 0x90, 0x92, 0x94, 0x96, 0x98, 0x9a, 0x9b, 0x9d, 0x9f, 0xa0,
+    0xa1, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, 0xa8, 0xa8, 0xa9, 0xaa, 0xab, 0xab, 0xac, 0xad, 0xad, 0xae },
+  { 0x80, 0x83, 0x85, 0x88, 0x8a, 0x8c, 0x8f, 0x91, 0x93, 0x95, 0x97, 0x99, 0x9a, 0x9c, 0x9d, 0x9f,
+    0xa0, 0xa1, 0xa2, 0xa3, 0xa5, 0xa5, 0xa6, 0xa7, 0xa8, 0xa9, 0xaa, 0xaa, 0xab, 0xab, 0xac, 0xad },
+  { 0x80, 0x82, 0x85, 0x87, 0x89, 0x8c, 0x8e, 0x90, 0x92, 0x94, 0x96, 0x97, 0x99, 0x9b, 0x9c, 0x9d,
+    0x9f, 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, 0xa8, 0xa8, 0xa9, 0xaa, 0xaa, 0xab, 0xac },
+  { 0x80, 0x82, 0x85, 0x87, 0x89, 0x8b, 0x8d, 0x8f, 0x91, 0x93, 0x95, 0x96, 0x98, 0x99, 0x9b, 0x9c,
+    0x9e, 0x9f, 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, 0xa7, 0xa8, 0xa9, 0xa9, 0xaa, 0xab },
+  { 0x80, 0x82, 0x84, 0x86, 0x88, 0x8a, 0x8c, 0x8e, 0x90, 0x92, 0x94, 0x95, 0x97, 0x98, 0x9a, 0x9b,
+    0x9d, 0x9e, 0x9f, 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa6, 0xa7, 0xa8, 0xa8, 0xa9, 0xaa },
+  { 0x80, 0x82, 0x84, 0x86, 0x88, 0x8a, 0x8c, 0x8e, 0x90, 0x91, 0x93, 0x94, 0x96, 0x97, 0x99, 0x9a,
+    0x9b, 0x9d, 0x9e, 0x9f, 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa5, 0xa6, 0xa7, 0xa7, 0xa8, 0xa9 },
+  { 0x80, 0x82, 0x84, 0x86, 0x88, 0x8a, 0x8b, 0x8d, 0x8f, 0x90, 0x92, 0x94, 0x95, 0x97, 0x98, 0x99,
+    0x9b, 0x9c, 0x9d, 0x9e, 0x9f, 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa4, 0xa5, 0xa6, 0xa6, 0xa7, 0xa8 },
+  { 0x80, 0x82, 0x84, 0x86, 0x87, 0x89, 0x8b, 0x8d, 0x8e, 0x90, 0x91, 0x93, 0x94, 0x96, 0x97, 0x98,
+    0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f, 0xa0, 0xa1, 0xa2, 0xa3, 0xa3, 0xa4, 0xa5, 0xa6, 0xa6, 0xa7 },
+  { 0x80, 0x82, 0x84, 0x85, 0x87, 0x89, 0x8a, 0x8c, 0x8e, 0x8f, 0x91, 0x92, 0x94, 0x95, 0x96, 0x98,
+    0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f, 0xa0, 0xa1, 0xa2, 0xa2, 0xa3, 0xa4, 0xa5, 0xa5, 0xa6 },
+  { 0x80, 0x82, 0x83, 0x85, 0x87, 0x88, 0x8a, 0x8c, 0x8d, 0x8f, 0x90, 0x92, 0x93, 0x94, 0x96, 0x97,
+    0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f, 0xa0, 0xa1, 0xa2, 0xa2, 0xa3, 0xa4, 0xa5, 0xa5 },
+  { 0x80, 0x82, 0x83, 0x85, 0x86, 0x88, 0x8a, 0x8b, 0x8d, 0x8e, 0x90, 0x91, 0x92, 0x94, 0x95, 0x96,
+    0x97, 0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f, 0xa0, 0xa1, 0xa2, 0xa2, 0xa3, 0xa4, 0xa4 },
+  { 0x80, 0x82, 0x83, 0x85, 0x86, 0x88, 0x89, 0x8b, 0x8c, 0x8e, 0x8f, 0x90, 0x92, 0x93, 0x94, 0x95,
+    0x96, 0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9e, 0x9f, 0xa0, 0xa1, 0xa2, 0xa2, 0xa3, 0xa4 },
+  { 0x80, 0x82, 0x83, 0x85, 0x86, 0x87, 0x89, 0x8a, 0x8c, 0x8d, 0x8e, 0x90, 0x91, 0x92, 0x93, 0x95,
+    0x96, 0x97, 0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9e, 0x9f, 0xa0, 0xa1, 0xa1, 0xa2, 0xa3 },
+  { 0x80, 0x81, 0x83, 0x84, 0x86, 0x87, 0x89, 0x8a, 0x8b, 0x8d, 0x8e, 0x8f, 0x90, 0x92, 0x93, 0x94,
+    0x95, 0x96, 0x97, 0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9e, 0x9f, 0xa0, 0xa1, 0xa1, 0xa2 },
+  { 0x80, 0x81, 0x83, 0x84, 0x86, 0x87, 0x88, 0x8a, 0x8b, 0x8c, 0x8e, 0x8f, 0x90, 0x91, 0x92, 0x93,
+    0x95, 0x96, 0x97, 0x98, 0x99, 0x9a, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f, 0x9f, 0xa0, 0xa1, 0xa1 },
+  { 0x80, 0x81, 0x83, 0x84, 0x85, 0x87, 0x88, 0x89, 0x8b, 0x8c, 0x8d, 0x8e, 0x90, 0x91, 0x92, 0x93,
+    0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9a, 0x9b, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f, 0x9f, 0xa0, 0xa1 },
+  { 0x80, 0x81, 0x83, 0x84, 0x85, 0x87, 0x88, 0x89, 0x8a, 0x8c, 0x8d, 0x8e, 0x8f, 0x90, 0x91, 0x92,
+    0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9c, 0x9d, 0x9e, 0x9f, 0x9f, 0xa0 }
+};
@@ -0,0 +1,261 @@
+#ifdef ST010_CPP
+
+//ST-010 emulation code - Copyright (C) 2003 The Dumper, Matthew Kendora, Overload, Feather
+//bsnes port - Copyright (C) 2007 byuu
+
+void ST010::op_01(int16 x0, int16 y0, int16 &x1, int16 &y1, int16 &quadrant, int16 &theta) {
+  if((x0 < 0) && (y0 < 0)) {
+    x1 = -x0;
+    y1 = -y0;
+    quadrant = -0x8000;
+  } else if(x0 < 0) {
+    x1 = y0;
+    y1 = -x0;
+    quadrant = -0x4000;
+  } else if(y0 < 0) {
+    x1 = -y0;
+    y1 = x0;
+    quadrant = 0x4000;
+  } else {
+    x1 = x0;
+    y1 = y0;
+    quadrant = 0x0000;
+  }
+
+  while((x1 > 0x1f) || (y1 > 0x1f)) {
+    if(x1 > 1) { x1 >>= 1; }
+    if(y1 > 1) { y1 >>= 1; }
+  }
+
+  if(y1 == 0) { quadrant += 0x4000; }
+
+  theta = (arctan[y1][x1] << 8) ^ quadrant;
+}
+
+//
+
+void ST010::op_01() {
+int16 x0 = readw(0x0000);
+int16 y0 = readw(0x0002);
+int16 x1, y1, quadrant, theta;
+
+  op_01(x0, y0, x1, y1, quadrant, theta);
+
+  writew(0x0000, x1);
+  writew(0x0002, y1);
+  writew(0x0004, quadrant);
+//writew(0x0006, y0); //Overload's docs note this write occurs, SNES9x disagrees
+  writew(0x0010, theta);
+}
+
+void ST010::op_02() {
+int16 positions = readw(0x0024);
+uint16 *places  = (uint16*)(ram + 0x0040);
+uint16 *drivers = (uint16*)(ram + 0x0080);
+
+bool sorted;
+uint16 temp;
+  if(positions > 1) {
+    do {
+      sorted = true;
+      for(int i = 0; i < positions - 1; i++) {
+        if(places[i] < places[i + 1]) {
+          temp = places[i + 1];
+          places[i + 1] = places[i];
+          places[i] = temp;
+
+          temp = drivers[i + 1];
+          drivers[i + 1] = drivers[i];
+          drivers[i] = temp;
+
+          sorted = false;
+        }
+      }
+      positions--;
+    } while(!sorted);
+  }
+}
+
+void ST010::op_03() {
+int16 x0 = readw(0x0000);
+int16 y0 = readw(0x0002);
+int16 multiplier = readw(0x0004);
+int32 x1, y1;
+
+  x1 = x0 * multiplier << 1;
+  y1 = y0 * multiplier << 1;
+
+  writed(0x0010, x1);
+  writed(0x0014, y1);
+}
+
+void ST010::op_04() {
+int16 x = readw(0x0000);
+int16 y = readw(0x0002);
+int16 square;
+//calculate the vector length of (x,y)
+  square = (int16)sqrt((double)(y * y + x * x));
+
+  writew(0x0010, square);
+}
+
+void ST010::op_05() {
+int32 dx, dy;
+int16 a1, b1, c1;
+uint16 o1;
+bool wrap = false;
+
+//target (x,y) coordinates
+int16 ypos_max = readw(0x00c0);
+int16 xpos_max = readw(0x00c2);
+
+//current coordinates and direction
+int32 ypos = readd(0x00c4);
+int32 xpos = readd(0x00c8);
+uint16 rot = readw(0x00cc);
+
+//physics
+uint16 speed = readw(0x00d4);
+uint16 accel = readw(0x00d6);
+uint16 speed_max = readw(0x00d8);
+
+//special condition acknowledgement
+int16 system = readw(0x00da);
+int16 flags = readw(0x00dc);
+
+//new target coordinates
+int16 ypos_new = readw(0x00de);
+int16 xpos_new = readw(0x00e0);
+
+//mask upper bit
+  xpos_new &= 0x7fff;
+
+//get the current distance
+  dx = xpos_max - (xpos >> 16);
+  dy = ypos_max - (ypos >> 16);
+
+//quirk: clear and move in9
+  writew(0x00d2, 0xffff);
+  writew(0x00da, 0x0000);
+
+//grab the target angle
+  op_01(dy, dx, a1, b1, c1, (int16&)o1);
+
+//check for wrapping
+  if(abs(o1 - rot) > 0x8000) {
+    o1 += 0x8000;
+    rot += 0x8000;
+    wrap = true;
+  }
+
+uint16 old_speed = speed;
+
+//special case
+  if(abs(o1 - rot) == 0x8000) {
+    speed = 0x100;
+  }
+
+//slow down for sharp curves
+  else if(abs(o1 - rot) >= 0x1000) {
+  uint32 slow = abs(o1 - rot);
+    slow >>= 4; //scaling
+    speed -= slow;
+  }
+
+//otherwise accelerate
+  else {
+    speed += accel;
+    if(speed > speed_max) {
+      speed = speed_max; //clip speed
+    }
+  }
+
+//prevent negative/positive overflow
+  if(abs(old_speed - speed) > 0x8000) {
+    if(old_speed < speed) { speed = 0; }
+    else speed = 0xff00;
+  }
+
+//adjust direction by so many degrees
+//be careful of negative adjustments
+  if((o1 > rot && (o1 - rot) > 0x80) || (o1 < rot && (rot - o1) >= 0x80)) {
+    if(o1 < rot) { rot -= 0x280; }
+    else if(o1 > rot) { rot += 0x280; }
+  }
+
+//turn of wrapping
+  if(wrap) { rot -= 0x8000; }
+
+//now check the distances (store for later)
+  dx = (xpos_max << 16) - xpos;
+  dy = (ypos_max << 16) - ypos;
+  dx >>= 16;
+  dy >>= 16;
+
+//if we're in so many units of the target, signal it
+  if((system && (dy <= 6 && dy >= -8) && (dx <= 126 && dx >= -128)) || (!system && (dx <= 6 && dx >= -8) && (dy <= 126 && dy >= -128))) {
+  //announce our new destination and flag it
+    xpos_max = xpos_new & 0x7fff;
+    ypos_max = ypos_new;
+    flags |= 0x08;
+  }
+
+//update position
+  xpos -= (cos(rot) * 0x400 >> 15) * (speed >> 8) << 1;
+  ypos -= (sin(rot) * 0x400 >> 15) * (speed >> 8) << 1;
+
+//quirk: mask upper byte
+  xpos &= 0x1fffffff;
+  ypos &= 0x1fffffff;
+
+  writew(0x00c0, ypos_max);
+  writew(0x00c2, xpos_max);
+  writed(0x00c4, ypos);
+  writed(0x00c8, xpos);
+  writew(0x00cc, rot);
+  writew(0x00d4, speed);
+  writew(0x00dc, flags);
+}
+
+void ST010::op_06() {
+int16 multiplicand = readw(0x0000);
+int16 multiplier = readw(0x0002);
+int32 product;
+
+  product = multiplicand * multiplier << 1;
+
+  writed(0x0010, product);
+}
+
+void ST010::op_07() {
+int16 theta = readw(0x0000);
+
+int16 data;
+  for(int i = 0, offset = 0; i < 176; i++) {
+    data = mode7_scale[i] * cos(theta) >> 15;
+    writew(0x00f0 + offset, data);
+    writew(0x0510 + offset, data);
+
+    data = mode7_scale[i] * sin(theta) >> 15;
+    writew(0x0250 + offset, data);
+    if(data) { data = ~data; }
+    writew(0x03b0 + offset, data);
+
+    offset += 2;
+  }
+}
+
+void ST010::op_08() {
+int16 x0 = readw(0x0000);
+int16 y0 = readw(0x0002);
+int16 theta = readw(0x0004);
+int16 x1, y1;
+
+  x1 = (y0 * sin(theta) >> 15) + (x0 * cos(theta) >> 15);
+  y1 = (y0 * cos(theta) >> 15) - (x0 * sin(theta) >> 15);
+
+  writew(0x0010, x1);
+  writew(0x0012, y1);
+}
+
+#endif //ifdef ST010_CPP
@@ -0,0 +1 @@
+@make platform=win compiler=mingw32-gcc clean
@@ -0,0 +1 @@
+make platform=x compiler=gcc clean
@@ -1,73 +1,127 @@
-Config config_file;
-
 namespace config {

-Setting FS::base_path(0, "fs.base_path",
-  "Directory that bsnes resides in", "");
-Setting FS::rom_path(&config_file, "fs.rom_path",
-  "Default path to look for ROM files in (\"\" = use default directory)", "");
-Setting FS::save_path(&config_file, "fs.save_path",
-  "Default path for all save RAM and cheat files (\"\" = use current directory)", "");
+configuration& config() {
+  static configuration config;
+  return config;
+}
+
+integral_setting File::autodetect_type(config(), "file.autodetect_type",
+  "Auto-detect file type by inspecting file header, rather than by file extension.\n"
+  "In other words, if a .zip file is renamed to .smc, it will still be correctly\n"
+  "identified as a .zip file. However, there is an infinitesimal (1:~500,000,000)\n"
+  "chance of a false detection when loading an uncompressed image file, if this\n"
+  "option is enabled.",
+  integral_setting::boolean, false);
+
+integral_setting File::bypass_patch_crc32(config(), "file.bypass_patch_crc32",
+  "UPS patches contain CRC32s to validate that a patch was applied successfully.\n"
+  "By default, if this validation fails, said patch will not be applied.\n"
+  "Setting this option to true will bypass the validation,\n"
+  "which may or may not result in a working image.\n"
+  "Enabling this option is strongly discouraged.",
+  integral_setting::boolean, false);

-Setting FS::save_ext(&config_file, "fs.save_ext",
-  "Extension to be used for all save RAM files", "srm");
+string file_updatepath(const char *req_file, const char *req_path) {
+  string file(req_file);
+  replace(file, "\\", "/");
+  if(!req_path || strlen(req_path) == 0) { return file; }

-Setting SNES::gamma_ramp(&config_file, "snes.colorfilter.gamma_ramp",
-  "Use precalculated TV-style gamma ramp", true, Setting::TRUE_FALSE);
-Setting SNES::sepia(&config_file, "snes.colorfilter.sepia",
-  "Convert color to sepia tone", false, Setting::TRUE_FALSE);
-Setting SNES::grayscale(&config_file, "snes.colorfilter.grayscale",
-  "Convert color to grayscale tone", false, Setting::TRUE_FALSE);
-Setting SNES::invert(&config_file, "snes.colorfilter.invert",
-  "Invert output image colors", false, Setting::TRUE_FALSE);
-Setting SNES::contrast(&config_file, "snes.colorfilter.contrast",
-  "Contrast", 0,  Setting::DEC);
-Setting SNES::brightness(&config_file, "snes.colorfilter.brightness",
-  "Brightness", 0, Setting::DEC);
-Setting SNES::gamma(&config_file, "snes.colorfilter.gamma",
-  "Gamma", 80, Setting::DEC);
+  string path(req_path);
+  replace(path, "\\", "/");
+  if(!strend(path, "/")) { strcat(path, "/"); }

-Setting SNES::ntsc_merge_fields(&config_file, "snes.ntsc_merge_fields",
-  "Merge fields in NTSC video filter\n"
-  "Set to true if using filter at any refresh rate other than 60hz\n"
-  "", true, Setting::TRUE_FALSE);
+  if(strbegin(path, "./")) {
+    ltrim(path(), "./");
+    string temp;
+    strcpy(temp, config::path.base);
+    strcat(temp, path);
+    strcpy(path, temp);
+  }

-Setting SNES::mute(&config_file, "snes.mute", "Mutes SNES audio output when enabled",
-  false, Setting::TRUE_FALSE);
+  lstring part;
+  split(part, "/", file);
+  strcat(path, part[count(part) - 1]);
+  return path;
+}

-Setting SNES::controller_port0(&config_file, "snes.controller_port_1",
-  "Controller attached to SNES port 1", ::SNES::DEVICEID_JOYPAD1, Setting::DEC);
-Setting SNES::controller_port1(&config_file, "snes.controller_port_2",
-  "Controller attached to SNES port 2", ::SNES::DEVICEID_JOYPAD2, Setting::DEC);
+string_setting Path::base("path.base", "Path that bsnes resides in", "");
+string_setting Path::user("path.user", "Path to user folder", "");

-Setting CPU::ntsc_clock_rate(&config_file, "cpu.ntsc_clock_rate",
-  "NTSC S-CPU clock rate (in hz)", 21477272, Setting::DEC);
-Setting CPU::pal_clock_rate(&config_file, "cpu.pal_clock_rate",
-  "PAL S-CPU clock rate (in hz)", 21241370, Setting::DEC);
-Setting CPU::hdma_enable(0, "cpu.hdma_enable",
-  "Enable HDMA effects", true, Setting::TRUE_FALSE);
+string_setting Path::rom(config(), "path.rom",
+  "Default path to look for ROM files in (\"\" = use default directory)", "");
+string_setting Path::patch(config(), "path.patch",
+  "Default path for all UPS patch files (\"\" = use current directory)", "");
+string_setting Path::save(config(), "path.save",
+  "Default path for all save RAM files (\"\" = use current directory)", "");
+string_setting Path::cheat(config(), "path.cheat",
+  "Default path for all cheat files (\"\" = use current directory)", "");
+string_setting Path::bsx(config(), "path.bsx", "", "");
+string_setting Path::st(config(), "path.st", "", "");

-Setting SMP::ntsc_clock_rate(&config_file, "smp.ntsc_clock_rate",
-  "NTSC S-SMP clock rate (in hz)", 24576000, Setting::DEC);
-Setting SMP::pal_clock_rate(&config_file, "smp.pal_clock_rate",
-  "PAL S-SMP clock rate (in hz)", 24576000, Setting::DEC);
+integral_setting SNES::controller_port1(config(), "snes.controller_port1",
+  "Controller attached to SNES port 1", integral_setting::decimal, ::SNES::Input::DeviceJoypad);
+integral_setting SNES::controller_port2(config(), "snes.controller_port2",
+  "Controller attached to SNES port 2", integral_setting::decimal, ::SNES::Input::DeviceJoypad);

-Setting PPU::render_scanline_position(&config_file, "ppu.render_scanline_position",
+integral_setting CPU::ntsc_clock_rate(config(), "cpu.ntsc_clock_rate",
+  "NTSC S-CPU clock rate (in hz)", integral_setting::decimal, 21477272);
+integral_setting CPU::pal_clock_rate(config(), "cpu.pal_clock_rate",
+  "PAL S-CPU clock rate (in hz)", integral_setting::decimal,  21281370);
+integral_setting CPU::wram_init_value(config(), "cpu.wram_init_value",
+  "Value to initialize 128k WRAM to upon power cycle.\n"
+  "Note that on real hardware, this value is undefined; meaning it can vary\n"
+  "per power-on, and per SNES unit. Such randomness is undesirable for an\n"
+  "emulator, so a static value is needed. There is also some form of pattern\n"
+  "to the randomness that has yet to be determined, which some games rely upon.\n"
+  "A value of 0x55 is safe for all known commercial software, and should be used.\n"
+  "However, some software written for SNES copiers, or backup units, relies on\n"
+  "WRAM being initialized to 0x00; which was a side-effect of the BIOS program\n"
+  "which executed on these copiers. Using 0x00 will therefore fix many homebrew\n"
+  "programs, but *will* break some poorly programmed commercial software titles,\n"
+  "which do not properly initialize WRAM upon power cycle.\n",
+  integral_setting::hex, 0x55);
+
+integral_setting SMP::ntsc_clock_rate(config(), "smp.ntsc_clock_rate",
+  "NTSC S-SMP clock rate (in hz)", integral_setting::decimal, 32040 * 768);
+integral_setting SMP::pal_clock_rate(config(), "smp.pal_clock_rate",
+  "PAL S-SMP clock rate (in hz)", integral_setting::decimal,  32040 * 768);
+
+integral_setting PPU::Hack::render_scanline_position(config(), "ppu.hack.render_scanline_position",
  "Approximate HCLOCK position to render at for scanline-based renderers",
-  256, Setting::DEC);
-Setting PPU::opt_enable(0, "ppu.opt_enable", "Enable offset-per-tile effects", true, Setting::TRUE_FALSE);
+  integral_setting::decimal, 512);
+integral_setting PPU::Hack::obj_cache(config(), "ppu.hack.obj_cache",
+  "Cache OAM OBJ attributes one scanline before rendering\n"
+  "This is technically closer to the actual operation of the SNES,\n"
+  "but can cause problems in some games if enabled",
+  integral_setting::boolean, false);
+integral_setting PPU::Hack::oam_address_invalidation(config(), "ppu.hack.oam_address_invalidation",
+  "OAM access address changes during active display, as the S-PPU reads\n"
+  "data to render the display. Thusly, the address retrieved when accessing\n"
+  "OAM during active display is unpredictable. Unfortunately, the exact\n"
+  "algorithm for this is completely unknown at this time. It is more hardware\n"
+  "accurate to enable this setting, but one must *not* rely on the actual\n"
+  "address to match hardware under emulation.",
+  integral_setting::boolean, true);
+integral_setting PPU::Hack::cgram_address_invalidation(config(), "ppu.hack.cgram_address_invalidation",
+  "CGRAM access address changes during active display (excluding hblank), as\n"
+  "the S-PPU reads data to render the display. Thusly, as with OAM, the access\n"
+  "address is unpredictable. Again, enabling this setting is more hardware\n"
+  "accurate, but one must *not* rely on the actual address to match hardware\n"
+  "under emulation.",
+  integral_setting::boolean, true);

-Setting PPU::bg1_pri0_enable(0, "ppu.bg1_pri0_enable", "Enable BG1 Priority 0", true, Setting::TRUE_FALSE);
-Setting PPU::bg1_pri1_enable(0, "ppu.bg1_pri1_enable", "Enable BG1 Priority 1", true, Setting::TRUE_FALSE);
-Setting PPU::bg2_pri0_enable(0, "ppu.bg2_pri0_enable", "Enable BG2 Priority 0", true, Setting::TRUE_FALSE);
-Setting PPU::bg2_pri1_enable(0, "ppu.bg2_pri1_enable", "Enable BG2 Priority 1", true, Setting::TRUE_FALSE);
-Setting PPU::bg3_pri0_enable(0, "ppu.bg3_pri0_enable", "Enable BG3 Priority 0", true, Setting::TRUE_FALSE);
-Setting PPU::bg3_pri1_enable(0, "ppu.bg3_pri1_enable", "Enable BG3 Priority 1", true, Setting::TRUE_FALSE);
-Setting PPU::bg4_pri0_enable(0, "ppu.bg4_pri0_enable", "Enable BG4 Priority 0", true, Setting::TRUE_FALSE);
-Setting PPU::bg4_pri1_enable(0, "ppu.bg4_pri1_enable", "Enable BG4 Priority 1", true, Setting::TRUE_FALSE);
-Setting PPU::oam_pri0_enable(0, "ppu.oam_pri0_enable", "Enable OAM Priority 0", true, Setting::TRUE_FALSE);
-Setting PPU::oam_pri1_enable(0, "ppu.oam_pri1_enable", "Enable OAM Priority 1", true, Setting::TRUE_FALSE);
-Setting PPU::oam_pri2_enable(0, "ppu.oam_pri2_enable", "Enable OAM Priority 2", true, Setting::TRUE_FALSE);
-Setting PPU::oam_pri3_enable(0, "ppu.oam_pri3_enable", "Enable OAM Priority 3", true, Setting::TRUE_FALSE);
+integral_setting PPU::opt_enable("ppu.opt_enable", "Enable offset-per-tile effects", integral_setting::boolean, true);
+integral_setting PPU::bg1_pri0_enable("ppu.bg1_pri0_enable", "Enable BG1 Priority 0", integral_setting::boolean, true);
+integral_setting PPU::bg1_pri1_enable("ppu.bg1_pri1_enable", "Enable BG1 Priority 1", integral_setting::boolean, true);
+integral_setting PPU::bg2_pri0_enable("ppu.bg2_pri0_enable", "Enable BG2 Priority 0", integral_setting::boolean, true);
+integral_setting PPU::bg2_pri1_enable("ppu.bg2_pri1_enable", "Enable BG2 Priority 1", integral_setting::boolean, true);
+integral_setting PPU::bg3_pri0_enable("ppu.bg3_pri0_enable", "Enable BG3 Priority 0", integral_setting::boolean, true);
+integral_setting PPU::bg3_pri1_enable("ppu.bg3_pri1_enable", "Enable BG3 Priority 1", integral_setting::boolean, true);
+integral_setting PPU::bg4_pri0_enable("ppu.bg4_pri0_enable", "Enable BG4 Priority 0", integral_setting::boolean, true);
+integral_setting PPU::bg4_pri1_enable("ppu.bg4_pri1_enable", "Enable BG4 Priority 1", integral_setting::boolean, true);
+integral_setting PPU::oam_pri0_enable("ppu.oam_pri0_enable", "Enable OAM Priority 0", integral_setting::boolean, true);
+integral_setting PPU::oam_pri1_enable("ppu.oam_pri1_enable", "Enable OAM Priority 1", integral_setting::boolean, true);
+integral_setting PPU::oam_pri2_enable("ppu.oam_pri2_enable", "Enable OAM Priority 2", integral_setting::boolean, true);
+integral_setting PPU::oam_pri3_enable("ppu.oam_pri3_enable", "Enable OAM Priority 3", integral_setting::boolean, true);

-};
+} //namespace config
@@ -1,39 +1,48 @@
-extern Config config_file;
-
 namespace config {

-extern struct FS {
-  static Setting base_path, rom_path, save_path;
-  static Setting save_ext;
-} fs;
+extern configuration& config();
+
+string file_updatepath(const char*, const char*);
+
+extern struct File {
+  static integral_setting autodetect_type;
+  static integral_setting bypass_patch_crc32;
+} file;
+
+extern struct Path {
+  static string_setting base, user, rom, patch, save, cheat;
+  static string_setting bsx, st;
+} path;

 extern struct SNES {
-  static Setting gamma_ramp, sepia, grayscale, invert, contrast, brightness, gamma;
-  static Setting ntsc_merge_fields;
-  static Setting mute;
-  static Setting controller_port0;
-  static Setting controller_port1;
+  static integral_setting controller_port1;
+  static integral_setting controller_port2;
 } snes;

 extern struct CPU {
-  static Setting ntsc_clock_rate, pal_clock_rate;
-  static Setting hdma_enable;
+  static integral_setting ntsc_clock_rate, pal_clock_rate;
+  static integral_setting wram_init_value;
 } cpu;

 extern struct SMP {
-  static Setting ntsc_clock_rate, pal_clock_rate;
+  static integral_setting ntsc_clock_rate, pal_clock_rate;
 } smp;

 extern struct PPU {
-  static Setting render_scanline_position;
-  static Setting opt_enable;
+  struct Hack {
+    static integral_setting render_scanline_position;
+    static integral_setting obj_cache;
+    static integral_setting oam_address_invalidation;
+    static integral_setting cgram_address_invalidation;
+  } hack;

-  static Setting bg1_pri0_enable, bg1_pri1_enable;
-  static Setting bg2_pri0_enable, bg2_pri1_enable;
-  static Setting bg3_pri0_enable, bg3_pri1_enable;
-  static Setting bg4_pri0_enable, bg4_pri1_enable;
-  static Setting oam_pri0_enable, oam_pri1_enable;
-  static Setting oam_pri2_enable, oam_pri3_enable;
+  static integral_setting opt_enable;
+  static integral_setting bg1_pri0_enable, bg1_pri1_enable;
+  static integral_setting bg2_pri0_enable, bg2_pri1_enable;
+  static integral_setting bg3_pri0_enable, bg3_pri1_enable;
+  static integral_setting bg4_pri0_enable, bg4_pri1_enable;
+  static integral_setting oam_pri0_enable, oam_pri1_enable;
+  static integral_setting oam_pri2_enable, oam_pri3_enable;
 } ppu;

 };
@@ -1,97 +0,0 @@
-#include "../../base.h"
-
-#include "core/core.cpp"
-#include "memory/memory.cpp"
-#include "dma/dma.cpp"
-#include "timing/timing.cpp"
-
-#include "bcpu_exec.cpp"
-#include "bcpu_mmio.cpp"
-#include "bcpu_int.cpp"
-
-uint8 bCPU::pio_status() { return status.pio; }
-
-void bCPU::run() {
-  if(run_state.hdma) {
-    exec_hdma();
-    return;
-  }
-
-  if(run_state.dma) {
-    exec_dma();
-    return;
-  }
-
-  if(status.cycle_pos == 0) { //interrupts only trigger on opcode edges
-    if(run_state.irq && !run_state.stp) {
-      run_state.irq = false;
-      if(time.nmi_pending == true) {
-        time.nmi_pending = false;
-        aa.w = (regs.e == false) ? 0xffea : 0xfffa;
-      } else if(time.irq_pending == true) {
-        time.irq_pending = false;
-        aa.w = (regs.e == false) ? 0xffee : 0xfffe;
-      }
-      irq_run();
-    }
-  }
-
-  exec_cycle();
-}
-
-void bCPU::power() {
-  region = snes->region();
-
-  regs.a = regs.x = regs.y = 0x0000;
-  regs.s = 0x01ff;
-  reset();
-}
-
-void bCPU::reset() {
-//reset vector location
-  regs.pc.d = 0;
-  regs.pc.l = r_mem->read(0xfffc);
-  regs.pc.h = r_mem->read(0xfffd);
-
-//registers are not fully reset by SNES
-  regs.x.h = 0x00;
-  regs.y.h = 0x00;
-  regs.s.h = 0x01;
-  regs.d   = 0x0000;
-  regs.db  = 0x00;
-  regs.p   = 0x34;
-  regs.e   = 1;
-  regs.mdr = 0x00;
-
-  time_reset();
-  mmio_reset();
-  dma_reset();
-
-  run_state.hdma = false;
-  run_state.dma  = false;
-  run_state.irq  = false;
-  run_state.wai  = false;
-  run_state.stp  = false;
-
-  status.cycle_pos       = 0;
-  status.cycle_count     = 0;
-  status.cycles_executed = 0;
-
-  apu_port[0] = 0x00;
-  apu_port[1] = 0x00;
-  apu_port[2] = 0x00;
-  apu_port[3] = 0x00;
-
-  frame();
-
-//initial latch values for $213c/$213d
-//[x]0035 : [y]0000 (53.0 -> 212) [lda $2137]
-//[x]0038 : [y]0000 (56.5 -> 226) [nop : lda $2137]
-  add_cycles(186);
-}
-
-bCPU::bCPU() {
-  init_op_tables();
-}
-
-bCPU::~bCPU() {}
@@ -1,165 +0,0 @@
-class bCPU : public CPU {
-public:
-#include "core/core.h"
-#include "memory/memory.h"
-#include "dma/dma.h"
-#include "timing/timing.h"
-
-enum { NTSC = 0, PAL = 1 };
-uint8 region;
-
-enum {
-  DMASTATE_DMASYNC,
-  DMASTATE_DMASYNC2,
-  DMASTATE_DMASYNC3,
-  DMASTATE_RUN,
-  DMASTATE_CPUSYNC,
-
-  HDMASTATE_IDMASYNC,
-  HDMASTATE_IDMASYNC2,
-  HDMASTATE_IDMASYNC3,
-  HDMASTATE_ICPUSYNC,
-
-  HDMASTATE_DMASYNC,
-  HDMASTATE_DMASYNC2,
-  HDMASTATE_DMASYNC3,
-  HDMASTATE_RUN,
-  HDMASTATE_CPUSYNC
-};
-
-struct {
-  bool hdma;
-  bool dma;
-  bool irq;
-  bool stp;
-  bool wai;
-} run_state;
-
-struct {
-  uint8  cycle_pos, cycle_count;
-  uint8  opcode;
-  uint32 cycles_executed;
-
-  uint8  dma_state, hdma_state;
-  uint32 dma_cycle_count, hdma_cycle_count;
-
-//$4207-$420a
-  uint16 virq_trigger, hirq_trigger;
-
-//$2181-$2183
-  uint32 wram_addr;
-
-//$4016-$4017
-  bool   joypad_strobe_latch;
-  uint8  joypad1_read_pos, joypad2_read_pos;
-
-//$4200
-  bool   nmi_enabled;
-  bool   hirq_enabled, virq_enabled;
-  bool   auto_joypad_poll;
-
-//$4201
-  uint8  pio;
-
-//$4202-$4203
-  uint8  mul_a, mul_b;
-
-//$4204-$4206
-  uint16 div_a;
-  uint8  div_b;
-
-//$4207-$420a
-  uint16 hirq_pos, virq_pos;
-
-//$4214-$4216
-  uint16 r4214;
-  uint16 r4216;
-} status;
-
-  inline bool   hdma_test();
-  inline bool   nmi_test();
-  inline bool   irq_test();
-
-  inline uint8  pio_status();
-  inline void   run();
-  inline uint32 clocks_executed();
-  inline void   power();
-  inline void   reset();
-
-  inline void   irq_run();
-
-//mmio commands
-  void  mmio_reset();
-  uint8 mmio_r2180();
-  uint8 mmio_r4016();
-  uint8 mmio_r4017();
-  uint8 mmio_r4210();
-  uint8 mmio_r4211();
-  uint8 mmio_r4212();
-  uint8 mmio_r4213();
-  uint8 mmio_r4214();
-  uint8 mmio_r4215();
-  uint8 mmio_r4216();
-  uint8 mmio_r4217();
-  uint8 mmio_r4218();
-  uint8 mmio_r4219();
-  uint8 mmio_r421a();
-  uint8 mmio_r421b();
-  uint8 mmio_r43x0(uint8 i);
-  uint8 mmio_r43x1(uint8 i);
-  uint8 mmio_r43x2(uint8 i);
-  uint8 mmio_r43x3(uint8 i);
-  uint8 mmio_r43x4(uint8 i);
-  uint8 mmio_r43x5(uint8 i);
-  uint8 mmio_r43x6(uint8 i);
-  uint8 mmio_r43x7(uint8 i);
-  uint8 mmio_r43x8(uint8 i);
-  uint8 mmio_r43x9(uint8 i);
-  uint8 mmio_r43xa(uint8 i);
-  uint8 mmio_r43xb(uint8 i);
-  void  mmio_w2180(uint8 value);
-  void  mmio_w2181(uint8 value);
-  void  mmio_w2182(uint8 value);
-  void  mmio_w2183(uint8 value);
-  void  mmio_w4016(uint8 value);
-  void  mmio_w4200(uint8 value);
-  void  mmio_w4201(uint8 value);
-  void  mmio_w4202(uint8 value);
-  void  mmio_w4203(uint8 value);
-  void  mmio_w4204(uint8 value);
-  void  mmio_w4205(uint8 value);
-  void  mmio_w4206(uint8 value);
-  void  mmio_w4207(uint8 value);
-  void  mmio_w4208(uint8 value);
-  void  mmio_w4209(uint8 value);
-  void  mmio_w420a(uint8 value);
-  void  mmio_w420b(uint8 value);
-  void  mmio_w420c(uint8 value);
-  void  mmio_w420d(uint8 value);
-  void  mmio_w43x0(uint8 value, uint8 i);
-  void  mmio_w43x1(uint8 value, uint8 i);
-  void  mmio_w43x2(uint8 value, uint8 i);
-  void  mmio_w43x3(uint8 value, uint8 i);
-  void  mmio_w43x4(uint8 value, uint8 i);
-  void  mmio_w43x5(uint8 value, uint8 i);
-  void  mmio_w43x6(uint8 value, uint8 i);
-  void  mmio_w43x7(uint8 value, uint8 i);
-  void  mmio_w43x8(uint8 value, uint8 i);
-  void  mmio_w43x9(uint8 value, uint8 i);
-  void  mmio_w43xa(uint8 value, uint8 i);
-  void  mmio_w43xb(uint8 value, uint8 i);
-
-  uint8 mmio_read (uint16 addr);
-  void  mmio_write(uint16 addr, uint8 data);
-
-enum { CYCLE_OPREAD, CYCLE_READ, CYCLE_WRITE, CYCLE_IO };
-  inline void pre_exec_cycle();
-  inline void exec_hdma();
-  inline void exec_dma();
-  inline void exec_cycle();
-  inline void last_cycle();
-  inline bool in_opcode();
-
-  bCPU();
-  ~bCPU();
-};
@@ -1,163 +0,0 @@
-void bCPU::last_cycle() {
-  time.nmi_pending |= nmi_test();
-  time.irq_pending |= irq_test();
-
-  run_state.irq = (time.nmi_pending || time.irq_pending);
-}
-
-void bCPU::pre_exec_cycle() {
-  if(!run_state.dma && !run_state.hdma)return;
-
-int c, z;
-  if(run_state.hdma) {
-    switch(status.hdma_state) {
-    case HDMASTATE_ICPUSYNC:
-    case HDMASTATE_CPUSYNC:
-      c = status.cycle_count;
-      z = c - (status.hdma_cycle_count % c);
-      if(!z)z = c;
-      add_cycles(z);
-      run_state.hdma = false;
-      break;
-    }
-  }
-
-  if(run_state.dma) {
-    switch(status.dma_state) {
-    case DMASTATE_CPUSYNC:
-      c = status.cycle_count;
-      z = c - (status.dma_cycle_count % c);
-      if(!z)z = c;
-      add_cycles(z);
-      run_state.dma = false;
-      break;
-    }
-  }
-}
-
-void bCPU::exec_hdma() {
-int n;
-static int z;
-  switch(status.hdma_state) {
-  case HDMASTATE_IDMASYNC:
-    status.hdma_cycle_count = 0;
-    z = 0;
-    if(!run_state.dma) {
-      exec_cycle();
-      status.hdma_state = HDMASTATE_IDMASYNC2;
-    } else {
-      status.hdma_state = HDMASTATE_IDMASYNC3;
-    }
-    break;
-  case HDMASTATE_IDMASYNC2:
-    n = 8 - dma_counter() + 8;
-    add_cycles(n);
-    status.hdma_cycle_count += n;
-    status.hdma_state = HDMASTATE_IDMASYNC3;
-    break;
-  case HDMASTATE_IDMASYNC3:
-    hdma_init();
-    if(!run_state.dma) {
-      status.hdma_state = HDMASTATE_ICPUSYNC;
-    } else {
-      run_state.hdma = false;
-    }
-    break;
-  case HDMASTATE_ICPUSYNC:
-    exec_cycle();
-    break;
-
-  case HDMASTATE_DMASYNC:
-    status.hdma_cycle_count = 0;
-    z = 0;
-    if(!run_state.dma) {
-      exec_cycle();
-      status.hdma_state = HDMASTATE_DMASYNC2;
-    } else {
-      status.hdma_state = HDMASTATE_DMASYNC3;
-    }
-    break;
-  case HDMASTATE_DMASYNC2:
-    n = 8 - dma_counter() + 8;
-    add_cycles(n);
-    status.hdma_cycle_count += n;
-    status.hdma_state = HDMASTATE_DMASYNC3;
-    break;
-  case HDMASTATE_DMASYNC3:
-    if(channel[z].hdma_line_counter) {
-      add_cycles(8);
-      status.hdma_cycle_count += 8;
-    }
-    if(++z < 8)break;
-    status.hdma_state = HDMASTATE_RUN;
-    break;
-  case HDMASTATE_RUN:
-    hdma_run(); //updates status.hdma_cycle_count
-    if(!run_state.dma) {
-      status.hdma_state = HDMASTATE_CPUSYNC;
-    } else {
-      run_state.hdma = false;
-    }
-    break;
-  case HDMASTATE_CPUSYNC:
-    exec_cycle();
-    break;
-  }
-}
-
-void bCPU::exec_dma() {
-int n;
-static int z;
-  switch(status.dma_state) {
-  case DMASTATE_DMASYNC:
-    exec_cycle();
-    status.dma_state = DMASTATE_DMASYNC2;
-    break;
-  case DMASTATE_DMASYNC2:
-    n = 8 - dma_counter() + 8;
-    add_cycles(n);
-    status.dma_cycle_count = n;
-    z = 0;
-    status.dma_state = DMASTATE_DMASYNC3;
-    break;
-  case DMASTATE_DMASYNC3:
-    if(channel[z].dma_enabled == true) {
-      add_cycles(8);
-      status.dma_cycle_count += 8;
-    }
-    if(++z < 8)break;
-    status.dma_state = DMASTATE_RUN;
-    break;
-  case DMASTATE_RUN:
-    dma_run(); //updates status.dma_cycle_count
-    cycle_edge();
-    break;
-  case DMASTATE_CPUSYNC:
-    exec_cycle();
-    break;
-  }
-}
-
-void bCPU::exec_cycle() {
-  if(status.cycle_pos) {
-    (this->*optbl[status.opcode])();
-  #ifdef DEBUGGER
-    if(status.cycle_pos == 0) {
-      snes->notify(SNES::CPU_EXEC_OPCODE_END);
-    }
-  #endif
-    return;
-  }
-
-//on first cycle?
-#ifdef DEBUGGER
-  snes->notify(SNES::CPU_EXEC_OPCODE_BEGIN);
-#endif
-  status.opcode = op_readpc();
-  status.cycle_pos = 1;
-}
-
-//only return true when we are on an opcode edge
-bool bCPU::in_opcode() {
-  return (status.cycle_pos != 0);
-}
@@ -1,50 +0,0 @@
-void bCPU::irq_run() {
-  mem_read(regs.pc.d);
-  cpu_io();
-  if(!regs.e)op_writestack(regs.pc.b);
-  op_writestack(regs.pc.h);
-  op_writestack(regs.pc.l);
-  op_writestack(regs.e ? (regs.p & ~0x10) : regs.p);
-  rd.l = op_readaddr(aa.w + 0);
-  regs.pc.b = 0x00;
-  regs.p.i  = 1;
-  regs.p.d  = 0;
-  rd.h = op_readaddr(aa.w + 1);
-  regs.pc.w = rd.w;
-#ifdef DEBUGGER
-//let debugger know the new IRQ opcode address
-  snes->notify(SNES::CPU_EXEC_OPCODE_END);
-#endif
-}
-
-bool bCPU::nmi_test() {
-  if(time.nmi_transition == 0)return false;
-  time.nmi_transition = 0;
-
-  run_state.wai = false;
-  return true;
-}
-
-bool bCPU::irq_test() {
-  if(time.irq_transition == 1)goto _true;
-
-  if(time.irq_read == 0) {
-    if(time.irq_line == 1 && (irq_trigger_pos_match(0) || irq_trigger_pos_match(2))) {
-      return false;
-    }
-    goto _true;
-  }
-
-  if(time.irq_line == 0) {
-    time.irq_line = 1;
-    goto _true;
-  }
-
-  return false;
-
-_true:
-  time.irq_transition = 0;
-
-  run_state.wai = false;
-  return (regs.p.i) ? false : true;
-}
@@ -1,650 +0,0 @@
-void bCPU::mmio_reset() {
-//$2181-$2183
-  status.wram_addr = 0x000000;
-
-//$4016-$4017
-  status.joypad_strobe_latch = 0;
-  status.joypad1_read_pos    = 0;
-  status.joypad2_read_pos    = 0;
-
-//$4200
-  status.nmi_enabled      = false;
-  status.hirq_enabled     = false;
-  status.virq_enabled     = false;
-  status.auto_joypad_poll = false;
-
-//$4201
-  status.pio = 0xff;
-
-//$4202-$4203
-  status.mul_a = 0xff;
-  status.mul_b = 0xff;
-
-//$4204-$4206
-  status.div_a = 0xffff;
-  status.div_b = 0xff;
-
-//$4207-$420a
-  status.hirq_pos = 0x01ff;
-  status.virq_pos = 0x01ff;
-
-//$4214-$4217
-  status.r4214 = 0x0000;
-  status.r4216 = 0x0000;
-}
-
-//WMDATA
-uint8 bCPU::mmio_r2180() {
-uint8 r;
-  r = r_mem->read(0x7e0000 | status.wram_addr);
-  status.wram_addr++;
-  status.wram_addr &= 0x01ffff;
-  return r;
-}
-
-//JOYSER0
-//7-2 = MDR
-//1-0 = Joypad serial data
-/* The joypad contains a small bit shifter that has 16 bits.
- * Reading from 4016 reads one bit from this buffer, then moves
- * the buffer left one, and adds a '1' to the rightmost bit.
- * Writing a one to $4016 will fill the buffer with the current
- * joypad button states, and lock the bit shifter at position
- * zero. All reads will be the first buffer state, or 'B'.
- * A zero must be written back to $4016 to unlock the buffer,
- * so that reads will increment the bit shifting position.
- */
-uint8 bCPU::mmio_r4016() {
-uint8 r;
-  r = regs.mdr & 0xfc;
-
-  if(status.joypad_strobe_latch == 1) {
-    r |= (uint8)snes->get_input_status(SNES::DEVICEID_JOYPAD1, SNES::JOYPAD_B);
-  } else {
-    switch(status.joypad1_read_pos) {
-    case  0: r |= (uint8)snes->get_input_status(SNES::DEVICEID_JOYPAD1, SNES::JOYPAD_B);      break;
-    case  1: r |= (uint8)snes->get_input_status(SNES::DEVICEID_JOYPAD1, SNES::JOYPAD_Y);      break;
-    case  2: r |= (uint8)snes->get_input_status(SNES::DEVICEID_JOYPAD1, SNES::JOYPAD_SELECT); break;
-    case  3: r |= (uint8)snes->get_input_status(SNES::DEVICEID_JOYPAD1, SNES::JOYPAD_START);  break;
-    case  4: r |= (uint8)snes->get_input_status(SNES::DEVICEID_JOYPAD1, SNES::JOYPAD_UP);     break;
-    case  5: r |= (uint8)snes->get_input_status(SNES::DEVICEID_JOYPAD1, SNES::JOYPAD_DOWN);   break;
-    case  6: r |= (uint8)snes->get_input_status(SNES::DEVICEID_JOYPAD1, SNES::JOYPAD_LEFT);   break;
-    case  7: r |= (uint8)snes->get_input_status(SNES::DEVICEID_JOYPAD1, SNES::JOYPAD_RIGHT);  break;
-    case  8: r |= (uint8)snes->get_input_status(SNES::DEVICEID_JOYPAD1, SNES::JOYPAD_A);      break;
-    case  9: r |= (uint8)snes->get_input_status(SNES::DEVICEID_JOYPAD1, SNES::JOYPAD_X);      break;
-    case 10: r |= (uint8)snes->get_input_status(SNES::DEVICEID_JOYPAD1, SNES::JOYPAD_L);      break;
-    case 11: r |= (uint8)snes->get_input_status(SNES::DEVICEID_JOYPAD1, SNES::JOYPAD_R);      break;
-    case 12: break;
-    case 13: break;
-    case 14: break;
-    case 15: break; //bits 12-15 always return 0
-  //all subsequent reads return joypad connection status
-    case 16: r |= 1; break; //joypad connected bit
-    }
-    if(++status.joypad1_read_pos > 16)status.joypad1_read_pos = 16;
-  }
-
-  return r;
-}
-
-//JOYSER1
-//7-5 = MDR
-//4-2 = Always 1 (pins are connected to GND)
-//1-0 = Joypad serial data
-uint8 bCPU::mmio_r4017() {
-uint8 r;
-  r  = regs.mdr & 0xe0;
-  r |= 0x1c;
-
-  if(status.joypad_strobe_latch == 1) {
-    r |= (uint8)snes->get_input_status(SNES::DEVICEID_JOYPAD2, SNES::JOYPAD_B);
-  } else {
-    switch(status.joypad2_read_pos) {
-    case  0: r |= (uint8)snes->get_input_status(SNES::DEVICEID_JOYPAD2, SNES::JOYPAD_B);      break;
-    case  1: r |= (uint8)snes->get_input_status(SNES::DEVICEID_JOYPAD2, SNES::JOYPAD_Y);      break;
-    case  2: r |= (uint8)snes->get_input_status(SNES::DEVICEID_JOYPAD2, SNES::JOYPAD_SELECT); break;
-    case  3: r |= (uint8)snes->get_input_status(SNES::DEVICEID_JOYPAD2, SNES::JOYPAD_START);  break;
-    case  4: r |= (uint8)snes->get_input_status(SNES::DEVICEID_JOYPAD2, SNES::JOYPAD_UP);     break;
-    case  5: r |= (uint8)snes->get_input_status(SNES::DEVICEID_JOYPAD2, SNES::JOYPAD_DOWN);   break;
-    case  6: r |= (uint8)snes->get_input_status(SNES::DEVICEID_JOYPAD2, SNES::JOYPAD_LEFT);   break;
-    case  7: r |= (uint8)snes->get_input_status(SNES::DEVICEID_JOYPAD2, SNES::JOYPAD_RIGHT);  break;
-    case  8: r |= (uint8)snes->get_input_status(SNES::DEVICEID_JOYPAD2, SNES::JOYPAD_A);      break;
-    case  9: r |= (uint8)snes->get_input_status(SNES::DEVICEID_JOYPAD2, SNES::JOYPAD_X);      break;
-    case 10: r |= (uint8)snes->get_input_status(SNES::DEVICEID_JOYPAD2, SNES::JOYPAD_L);      break;
-    case 11: r |= (uint8)snes->get_input_status(SNES::DEVICEID_JOYPAD2, SNES::JOYPAD_R);      break;
-    case 12: break;
-    case 13: break;
-    case 14: break;
-    case 15: break; //bits 12-15 always return 0
-  //all subsequent reads return joypad connection status
-    case 16: r |= 1; break; //joypad connected bit
-    }
-    if(++status.joypad2_read_pos > 16)status.joypad2_read_pos = 16;
-  }
-
-  return r;
-}
-
-//RDNMI
-//7   = NMI acknowledge
-//6-4 = MDR
-//3-0 = CPU (5a22) version
-uint8 bCPU::mmio_r4210() {
-uint8 r;
-  r  = regs.mdr & 0x70;
-  r |= uint8(!time.nmi_read) << 7;
-
-  if(!nmi_trigger_pos_match(0) && !nmi_trigger_pos_match(2)) {
-    time.nmi_read = 1;
-  }
-
-  r |= (cpu_version & 0x0f);
-  return r;
-}
-
-//TIMEUP
-//7   = IRQ acknowledge
-//6-0 = MDR
-uint8 bCPU::mmio_r4211() {
-uint8 r;
-  r  = regs.mdr & 0x7f;
-  r |= uint8(!time.irq_read) << 7;
-
-  if(!irq_trigger_pos_match(0) && !irq_trigger_pos_match(2)) {
-    time.irq_read = 1;
-    time.irq_line = 1;
-    time.irq_transition = 0;
-  }
-
-  return r;
-}
-
-//HVBJOY
-//7   = in vblank
-//6   = in hblank
-//5-1 = MDR
-//0   = joypad ready
-uint8 bCPU::mmio_r4212() {
-uint8 r;
-  r = regs.mdr & 0x3e;
-
-uint16 vs = overscan() ? 240 : 225;
-
-//auto joypad polling
-  if(time.v >= vs && time.v <= (vs + 2))r |= 0x01;
-
-//hblank
-  if(time.hc <= 2 || time.hc >= 1096)r |= 0x40;
-
-//vblank
-  if(time.v >= vs)r |= 0x80;
-
-  return r;
-}
-
-//RDIO
-uint8 bCPU::mmio_r4213() {
-  return status.pio;
-}
-
-//RDDIVL
-uint8 bCPU::mmio_r4214() {
-  return status.r4214;
-}
-
-//RDDIVH
-uint8 bCPU::mmio_r4215() {
-  return status.r4214 >> 8;
-}
-
-//RDMPYL
-uint8 bCPU::mmio_r4216() {
-  return status.r4216;
-}
-
-//RDMPYH
-uint8 bCPU::mmio_r4217() {
-  return status.r4216 >> 8;
-}
-
-//JOY1L
-uint8 bCPU::mmio_r4218() {
-uint8  r = 0x00;
-uint16 v = vcounter();
-  if(status.auto_joypad_poll == false)return 0x00; //can't read joypad if auto polling not enabled
-//if(v >= 225 && v <= 227)return 0x00; //can't read joypad while SNES is polling input
-  r |= (uint8)snes->get_input_status(SNES::DEVICEID_JOYPAD1, SNES::JOYPAD_A) << 7;
-  r |= (uint8)snes->get_input_status(SNES::DEVICEID_JOYPAD1, SNES::JOYPAD_X) << 6;
-  r |= (uint8)snes->get_input_status(SNES::DEVICEID_JOYPAD1, SNES::JOYPAD_L) << 5;
-  r |= (uint8)snes->get_input_status(SNES::DEVICEID_JOYPAD1, SNES::JOYPAD_R) << 4;
-  return r;
-}
-
-//JOY1H
-uint8 bCPU::mmio_r4219() {
-uint8  r = 0x00;
-uint16 v = vcounter();
-  if(status.auto_joypad_poll == false)return 0x00; //can't read joypad if auto polling not enabled
-//if(v >= 225 && v <= 227)return 0x00; //can't read joypad while SNES is polling input
-  r |= (uint8)snes->get_input_status(SNES::DEVICEID_JOYPAD1, SNES::JOYPAD_B)      << 7;
-  r |= (uint8)snes->get_input_status(SNES::DEVICEID_JOYPAD1, SNES::JOYPAD_Y)      << 6;
-  r |= (uint8)snes->get_input_status(SNES::DEVICEID_JOYPAD1, SNES::JOYPAD_SELECT) << 5;
-  r |= (uint8)snes->get_input_status(SNES::DEVICEID_JOYPAD1, SNES::JOYPAD_START)  << 4;
-  r |= (uint8)snes->get_input_status(SNES::DEVICEID_JOYPAD1, SNES::JOYPAD_UP)     << 3;
-  r |= (uint8)snes->get_input_status(SNES::DEVICEID_JOYPAD1, SNES::JOYPAD_DOWN)   << 2;
-  r |= (uint8)snes->get_input_status(SNES::DEVICEID_JOYPAD1, SNES::JOYPAD_LEFT)   << 1;
-  r |= (uint8)snes->get_input_status(SNES::DEVICEID_JOYPAD1, SNES::JOYPAD_RIGHT);
-  return r;
-}
-
-//JOY2L
-uint8 bCPU::mmio_r421a() {
-uint8  r = 0x00;
-uint16 v = vcounter();
-  if(status.auto_joypad_poll == false)return 0x00; //can't read joypad if auto polling not enabled
-//if(v >= 225 && v <= 227)return 0x00; //can't read joypad while SNES is polling input
-  r |= (uint8)snes->get_input_status(SNES::DEVICEID_JOYPAD2, SNES::JOYPAD_A) << 7;
-  r |= (uint8)snes->get_input_status(SNES::DEVICEID_JOYPAD2, SNES::JOYPAD_X) << 6;
-  r |= (uint8)snes->get_input_status(SNES::DEVICEID_JOYPAD2, SNES::JOYPAD_L) << 5;
-  r |= (uint8)snes->get_input_status(SNES::DEVICEID_JOYPAD2, SNES::JOYPAD_R) << 4;
-  return r;
-}
-
-//JOY2H
-uint8 bCPU::mmio_r421b() {
-uint8  r = 0x00;
-uint16 v = vcounter();
-  if(status.auto_joypad_poll == false)return 0x00; //can't read joypad if auto polling not enabled
-//if(v >= 225 && v <= 227)return 0x00; //can't read joypad while SNES is polling input
-  r |= (uint8)snes->get_input_status(SNES::DEVICEID_JOYPAD2, SNES::JOYPAD_B)      << 7;
-  r |= (uint8)snes->get_input_status(SNES::DEVICEID_JOYPAD2, SNES::JOYPAD_Y)      << 6;
-  r |= (uint8)snes->get_input_status(SNES::DEVICEID_JOYPAD2, SNES::JOYPAD_SELECT) << 5;
-  r |= (uint8)snes->get_input_status(SNES::DEVICEID_JOYPAD2, SNES::JOYPAD_START)  << 4;
-  r |= (uint8)snes->get_input_status(SNES::DEVICEID_JOYPAD2, SNES::JOYPAD_UP)     << 3;
-  r |= (uint8)snes->get_input_status(SNES::DEVICEID_JOYPAD2, SNES::JOYPAD_DOWN)   << 2;
-  r |= (uint8)snes->get_input_status(SNES::DEVICEID_JOYPAD2, SNES::JOYPAD_LEFT)   << 1;
-  r |= (uint8)snes->get_input_status(SNES::DEVICEID_JOYPAD2, SNES::JOYPAD_RIGHT);
-  return r;
-}
-
-//DMAPx
-uint8 bCPU::mmio_r43x0(uint8 i) {
-  return channel[i].dmap;
-}
-
-//BBADx
-uint8 bCPU::mmio_r43x1(uint8 i) {
-  return channel[i].destaddr;
-}
-
-//A1TxL
-uint8 bCPU::mmio_r43x2(uint8 i) {
-  return channel[i].srcaddr;
-}
-
-//A1TxH
-uint8 bCPU::mmio_r43x3(uint8 i) {
-  return channel[i].srcaddr >> 8;
-}
-
-//A1Bx
-uint8 bCPU::mmio_r43x4(uint8 i) {
-  return channel[i].srcbank;
-}
-
-//DASxL
-uint8 bCPU::mmio_r43x5(uint8 i) {
-  return channel[i].xfersize;
-}
-
-//DASxH
-uint8 bCPU::mmio_r43x6(uint8 i) {
-  return channel[i].xfersize >> 8;
-}
-
-//DASBx
-uint8 bCPU::mmio_r43x7(uint8 i) {
-  return channel[i].hdma_ibank;
-}
-
-//A2AxL
-uint8 bCPU::mmio_r43x8(uint8 i) {
-  return channel[i].hdma_addr;
-}
-
-//A2AxH
-uint8 bCPU::mmio_r43x9(uint8 i) {
-  return channel[i].hdma_addr >> 8;
-}
-
-//NTRLx
-uint8 bCPU::mmio_r43xa(uint8 i) {
-  return channel[i].hdma_line_counter;
-}
-
-//???
-uint8 bCPU::mmio_r43xb(uint8 i) {
-  return channel[i].hdma_unknown;
-}
-
-uint8 bCPU::mmio_read(uint16 addr) {
-//APU
-  if((addr & 0xffc0) == 0x2140) { //$2140-$217f
-    return r_smp->port_read(addr & 3);
-  }
-
-//HDMA
-  if((addr & 0xff80) == 0x4300) { //$4300-$437f
-  uint i = (addr >> 4) & 7;
-    switch(addr & 0xf) {
-    case 0x0: return mmio_r43x0(i);
-    case 0x1: return mmio_r43x1(i);
-    case 0x2: return mmio_r43x2(i);
-    case 0x3: return mmio_r43x3(i);
-    case 0x4: return mmio_r43x4(i);
-    case 0x5: return mmio_r43x5(i);
-    case 0x6: return mmio_r43x6(i);
-    case 0x7: return mmio_r43x7(i);
-    case 0x8: return mmio_r43x8(i);
-    case 0x9: return mmio_r43x9(i);
-    case 0xa: return mmio_r43xa(i);
-    case 0xb: return mmio_r43xb(i);
-    case 0xc: return regs.mdr; //unmapped
-    case 0xd: return regs.mdr; //unmapped
-    case 0xe: return regs.mdr; //unmapped
-    case 0xf: return mmio_r43xb(i); //mirror of 43xb
-    }
-  }
-
-  switch(addr) {
-  case 0x2180: return mmio_r2180(); //WMDATA
-  case 0x4016: return mmio_r4016(); //JOYSER0
-  case 0x4017: return mmio_r4017(); //JOYSER1
-  case 0x4210: return mmio_r4210(); //RDNMI
-  case 0x4211: return mmio_r4211(); //TIMEUP
-  case 0x4212: return mmio_r4212(); //HVBJOY
-  case 0x4213: return mmio_r4213(); //RDIO
-  case 0x4214: return mmio_r4214(); //RDDIVL
-  case 0x4215: return mmio_r4215(); //RDDIVH
-  case 0x4216: return mmio_r4216(); //RDMPYL
-  case 0x4217: return mmio_r4217(); //RDMPYH
-  case 0x4218: return mmio_r4218(); //JOY1L
-  case 0x4219: return mmio_r4219(); //JOY1H
-  case 0x421a: return mmio_r421a(); //JOY2L
-  case 0x421b: return mmio_r421b(); //JOY2H
-  case 0x421c: return 0x00;
-  case 0x421d: return 0x00;
-  case 0x421e: return 0x00;
-  case 0x421f: return 0x00;
-  }
-
-  return regs.mdr;
-}
-
-//WMDATA
-void bCPU::mmio_w2180(uint8 value) {
-  r_mem->write(0x7e0000 | status.wram_addr, value);
-  status.wram_addr++;
-  status.wram_addr &= 0x01ffff;
-}
-
-//WMADDL
-void bCPU::mmio_w2181(uint8 value) {
-  status.wram_addr = (status.wram_addr & 0xffff00) | value;
-  status.wram_addr &= 0x01ffff;
-}
-
-//WMADDM
-void bCPU::mmio_w2182(uint8 value) {
-  status.wram_addr = (status.wram_addr & 0xff00ff) | (value << 8);
-  status.wram_addr &= 0x01ffff;
-}
-
-//WMADDH
-void bCPU::mmio_w2183(uint8 value) {
-  status.wram_addr = (status.wram_addr & 0x00ffff) | (value << 16);
-  status.wram_addr &= 0x01ffff;
-}
-
-//JOYSER0
-//bit 0 is shared between JOYSER0 and JOYSER1, therefore
-//strobing $4016.d0 affects both controller port latches.
-//$4017 bit 0 writes are ignored.
-void bCPU::mmio_w4016(uint8 value) {
-  status.joypad_strobe_latch = bool(value & 1);
-
-  if(status.joypad_strobe_latch == 1) {
-    snes->poll_input();
-    status.joypad1_read_pos = 0;
-    status.joypad2_read_pos = 0;
-  }
-}
-
-//NMITIMEN
-void bCPU::mmio_w4200(uint8 value) {
-  status.nmi_enabled      = bool(value & 0x80);
-  status.virq_enabled     = bool(value & 0x20);
-  status.hirq_enabled     = bool(value & 0x10);
-  status.auto_joypad_poll = bool(value & 0x01);
-
-  if(time.nmi_read == 0) {
-    if(time.nmi_line == 1 && !status.nmi_enabled == 0) {
-      time.nmi_transition = 1;
-    }
-    time.nmi_line = !status.nmi_enabled;
-  }
-
-  if(status.virq_enabled == false && status.hirq_enabled == false) {
-    time.irq_line = 1;
-    time.irq_read = 1;
-    time.irq_transition = 0;
-  }
-
-  update_interrupts();
-}
-
-//WRIO
-void bCPU::mmio_w4201(uint8 value) {
-  if((status.pio & 0x80) && !(value & 0x80)) {
-    r_ppu->latch_counters();
-  }
-  status.pio = value;
-}
-
-//WRMPYA
-void bCPU::mmio_w4202(uint8 value) {
-  status.mul_a = value;
-}
-
-//WRMPYB
-void bCPU::mmio_w4203(uint8 value) {
-  status.mul_b = value;
-  status.r4216 = status.mul_a * status.mul_b;
-}
-
-//WRDIVL
-void bCPU::mmio_w4204(uint8 value) {
-  status.div_a = (status.div_a & 0xff00) | (value);
-}
-
-//WRDIVH
-void bCPU::mmio_w4205(uint8 value) {
-  status.div_a = (status.div_a & 0x00ff) | (value << 8);
-}
-
-//WRDIVB
-void bCPU::mmio_w4206(uint8 value) {
-  status.div_b = value;
-  status.r4214 = (status.div_b) ? status.div_a / status.div_b : 0xffff;
-  status.r4216 = (status.div_b) ? status.div_a % status.div_b : status.div_a;
-}
-
-//HTIMEL
-void bCPU::mmio_w4207(uint8 value) {
-  status.hirq_pos = ((status.hirq_pos & 0xff00) | value) & 0x01ff;
-  update_interrupts();
-}
-
-//HTIMEH
-void bCPU::mmio_w4208(uint8 value) {
-  status.hirq_pos = ((status.hirq_pos & 0x00ff) | (value << 8)) & 0x01ff;
-  update_interrupts();
-}
-
-//VTIMEL
-void bCPU::mmio_w4209(uint8 value) {
-  status.virq_pos = ((status.virq_pos & 0xff00) | value) & 0x01ff;
-  update_interrupts();
-}
-
-//VTIMEH
-void bCPU::mmio_w420a(uint8 value) {
-  status.virq_pos = ((status.virq_pos & 0x00ff) | (value << 8)) & 0x01ff;
-  update_interrupts();
-}
-
-//DMAEN
-//DMA enable does not disable active HDMA channels
-void bCPU::mmio_w420b(uint8 value) {
-  if(value != 0x00) {
-    run_state.dma = true;
-    status.dma_state = DMASTATE_DMASYNC;
-  }
-
-  for(int i = 0; i < 8; i++) {
-    channel[i].dma_enabled = bool(value & (1 << i));
-  //TODO: clearing read_index may interfere with DMA+HDMA occurring simultaneously
-    if(channel[i].dma_enabled)channel[i].read_index = 0;
-  }
-}
-
-//HDMAEN
-void bCPU::mmio_w420c(uint8 value) {
-  for(int i = 0; i < 8; i++) {
-    channel[i].hdma_enabled = bool(value & (1 << i));
-  }
-}
-
-//MEMSEL
-void bCPU::mmio_w420d(uint8 value) {
-  r_mem->set_speed(value & 1);
-}
-
-//DMAPx
-void bCPU::mmio_w43x0(uint8 value, uint8 i) {
-  channel[i].dmap          = value;
-  channel[i].direction     = bool(value & 0x80);
-  channel[i].hdma_indirect = bool(value & 0x40);
-  channel[i].incmode       = (value & 0x10) ? -1 : 1;
-  channel[i].fixedxfer     = bool(value & 0x08);
-  channel[i].xfermode      = value & 7;
-}
-
-//BBADx
-void bCPU::mmio_w43x1(uint8 value, uint8 i) {
-  channel[i].destaddr = value;
-}
-
-//A1TxL
-void bCPU::mmio_w43x2(uint8 value, uint8 i) {
-  channel[i].srcaddr = (channel[i].srcaddr & 0xff00) | value;
-}
-
-//A1TxH
-void bCPU::mmio_w43x3(uint8 value, uint8 i) {
-  channel[i].srcaddr = (channel[i].srcaddr & 0x00ff) | (value << 8);
-}
-
-//A1Bx
-void bCPU::mmio_w43x4(uint8 value, uint8 i) {
-  channel[i].srcbank = value;
-}
-
-//DASxL
-void bCPU::mmio_w43x5(uint8 value, uint8 i) {
-  channel[i].xfersize = (channel[i].xfersize & 0xff00) | value;
-}
-
-//DASxH
-void bCPU::mmio_w43x6(uint8 value, uint8 i) {
-  channel[i].xfersize = (channel[i].xfersize & 0x00ff) | (value << 8);
-}
-
-//DASBx
-void bCPU::mmio_w43x7(uint8 value, uint8 i) {
-  channel[i].hdma_ibank = value;
-}
-
-//A2AxL
-void bCPU::mmio_w43x8(uint8 value, uint8 i) {
-  channel[i].hdma_addr = (channel[i].hdma_addr & 0xff00) | value;
-}
-
-//A2AxH
-void bCPU::mmio_w43x9(uint8 value, uint8 i) {
-  channel[i].hdma_addr = (channel[i].hdma_addr & 0x00ff) | (value << 8);
-}
-
-//NTRLx
-void bCPU::mmio_w43xa(uint8 value, uint8 i) {
-  channel[i].hdma_line_counter = value;
-}
-
-//???
-void bCPU::mmio_w43xb(uint8 value, uint8 i) {
-  channel[i].hdma_unknown = value;
-}
-
-void bCPU::mmio_write(uint16 addr, uint8 data) {
-//APU
-  if((addr & 0xffc0) == 0x2140) { //$2140-$217f
-    port_write(addr & 3, data);
-    return;
-  }
-
-//HDMA
-  if((addr & 0xff80) == 0x4300) { //$4300-$437f
-  uint i = (addr >> 4) & 7;
-    switch(addr & 0xf) {
-    case 0x0: mmio_w43x0(data, i); return;
-    case 0x1: mmio_w43x1(data, i); return;
-    case 0x2: mmio_w43x2(data, i); return;
-    case 0x3: mmio_w43x3(data, i); return;
-    case 0x4: mmio_w43x4(data, i); return;
-    case 0x5: mmio_w43x5(data, i); return;
-    case 0x6: mmio_w43x6(data, i); return;
-    case 0x7: mmio_w43x7(data, i); return;
-    case 0x8: mmio_w43x8(data, i); return;
-    case 0x9: mmio_w43x9(data, i); return;
-    case 0xa: mmio_w43xa(data, i); return;
-    case 0xb: mmio_w43xb(data, i); return;
-    case 0xc: return; //unmapped
-    case 0xd: return; //unmapped
-    case 0xe: return; //unmapped
-    case 0xf: mmio_w43xb(data, i); return; //mirror of 43xb
-    }
-  }
-
-  switch(addr) {
-  case 0x2180: mmio_w2180(data); return; //WMDATA
-  case 0x2181: mmio_w2181(data); return; //WMADDL
-  case 0x2182: mmio_w2182(data); return; //WMADDM
-  case 0x2183: mmio_w2183(data); return; //WMADDH
-  case 0x4016: mmio_w4016(data); return; //JOYSER0
-  case 0x4017: return; //unmapped
-  case 0x4200: mmio_w4200(data); return; //NMITIMEN
-  case 0x4201: mmio_w4201(data); return; //WRIO
-  case 0x4202: mmio_w4202(data); return; //WRMPYA
-  case 0x4203: mmio_w4203(data); return; //WRMPYB
-  case 0x4204: mmio_w4204(data); return; //WRDIVL
-  case 0x4205: mmio_w4205(data); return; //WRDIVH
-  case 0x4206: mmio_w4206(data); return; //WRDIVB
-  case 0x4207: mmio_w4207(data); return; //HTIMEL
-  case 0x4208: mmio_w4208(data); return; //HTIMEH
-  case 0x4209: mmio_w4209(data); return; //VTIMEL
-  case 0x420a: mmio_w420a(data); return; //VTIMEH
-  case 0x420b: mmio_w420b(data); return; //DMAEN
-  case 0x420c: mmio_w420c(data); return; //HDMAEN
-  case 0x420d: mmio_w420d(data); return; //MEMSEL
-  }
-}
@@ -1,18 +0,0 @@
-#define CLASS_NAME "bCPU"
-#include "../../../lib/opgen.cpp"
-
-int main() {
-  fph = fopen("op.h", "wb");
-  fpt = fopen("optable.cpp", "wb");
-
-  generate("op_read.cpp",  "op_read.b");
-  generate("op_rmw.cpp",   "op_rmw.b");
-  generate("op_write.cpp", "op_write.b");
-  generate("op_pc.cpp",    "op_pc.b");
-  generate("op_misc.cpp",  "op_misc.b");
-
-  fclose(fph);
-  fclose(fpt);
-
-  return 0;
-}
@@ -1,3 +0,0 @@
-cl /O2 /wd4996 bcpugen.cpp
-@pause
-@del *.obj
@@ -1 +0,0 @@
-@del *.exe
@@ -1,28 +0,0 @@
-#include "opfn.cpp"
-#include "op_read.cpp"
-#include "op_rmw.cpp"
-#include "op_write.cpp"
-#include "op_pc.cpp"
-#include "op_misc.cpp"
-
-void bCPU::cpu_c2() {
-  if(regs.d.l != 0x00) {
-    cpu_io();
-  }
-}
-
-void bCPU::cpu_c4(uint16 x, uint16 y) {
-  if(!regs.p.x || (x & 0xff00) != (y & 0xff00)) {
-    cpu_io();
-  }
-}
-
-void bCPU::cpu_c6(uint16 addr) {
-  if(regs.e && (regs.pc.w & 0xff00) != (addr & 0xff00)) {
-    cpu_io();
-  }
-}
-
-void bCPU::init_op_tables() {
-  #include "optable.cpp"
-}
@@ -1,62 +0,0 @@
-/* External functions:
- *   void   last_cycle();
- *   void   cpu_io();
- *   uint8  mem_read(uint32 addr);
- *   void   mem_write(uint32 addr, uint8 value);
- */
-
-void (bCPU::*optbl[256])();
-
-CPUReg24 aa, rd;
-uint8    dp, sp;
-
-//op_read
-  inline void   op_adc_b();
-  inline void   op_adc_w();
-  inline void   op_and_b();
-  inline void   op_and_w();
-  inline void   op_bit_b();
-  inline void   op_bit_w();
-  inline void   op_cmp_b();
-  inline void   op_cmp_w();
-  inline void   op_cpx_b();
-  inline void   op_cpx_w();
-  inline void   op_cpy_b();
-  inline void   op_cpy_w();
-  inline void   op_eor_b();
-  inline void   op_eor_w();
-  inline void   op_lda_b();
-  inline void   op_lda_w();
-  inline void   op_ldx_b();
-  inline void   op_ldx_w();
-  inline void   op_ldy_b();
-  inline void   op_ldy_w();
-  inline void   op_ora_b();
-  inline void   op_ora_w();
-  inline void   op_sbc_b();
-  inline void   op_sbc_w();
-//op_rmw
-  inline void   op_inc_b();
-  inline void   op_inc_w();
-  inline void   op_dec_b();
-  inline void   op_dec_w();
-  inline void   op_asl_b();
-  inline void   op_asl_w();
-  inline void   op_lsr_b();
-  inline void   op_lsr_w();
-  inline void   op_rol_b();
-  inline void   op_rol_w();
-  inline void   op_ror_b();
-  inline void   op_ror_w();
-  inline void   op_trb_b();
-  inline void   op_trb_w();
-  inline void   op_tsb_b();
-  inline void   op_tsb_w();
-
-  inline void   cpu_c2();
-  inline void   cpu_c4(uint16 x, uint16 y);
-  inline void   cpu_c6(uint16 addr);
-
-  inline void   init_op_tables();
-
-#include "op.h"
@@ -1,256 +0,0 @@
-void op_adc_const();
-void op_and_const();
-void op_cmp_const();
-void op_cpx_const();
-void op_cpy_const();
-void op_eor_const();
-void op_lda_const();
-void op_ldx_const();
-void op_ldy_const();
-void op_ora_const();
-void op_sbc_const();
-void op_adc_addr();
-void op_and_addr();
-void op_bit_addr();
-void op_cmp_addr();
-void op_cpx_addr();
-void op_cpy_addr();
-void op_eor_addr();
-void op_lda_addr();
-void op_ldx_addr();
-void op_ldy_addr();
-void op_ora_addr();
-void op_sbc_addr();
-void op_adc_addrx();
-void op_and_addrx();
-void op_bit_addrx();
-void op_cmp_addrx();
-void op_eor_addrx();
-void op_lda_addrx();
-void op_ldy_addrx();
-void op_ora_addrx();
-void op_sbc_addrx();
-void op_adc_addry();
-void op_and_addry();
-void op_cmp_addry();
-void op_eor_addry();
-void op_lda_addry();
-void op_ldx_addry();
-void op_ora_addry();
-void op_sbc_addry();
-void op_adc_long();
-void op_and_long();
-void op_cmp_long();
-void op_eor_long();
-void op_lda_long();
-void op_ora_long();
-void op_sbc_long();
-void op_adc_longx();
-void op_and_longx();
-void op_cmp_longx();
-void op_eor_longx();
-void op_lda_longx();
-void op_ora_longx();
-void op_sbc_longx();
-void op_adc_dp();
-void op_and_dp();
-void op_bit_dp();
-void op_cmp_dp();
-void op_cpx_dp();
-void op_cpy_dp();
-void op_eor_dp();
-void op_lda_dp();
-void op_ldx_dp();
-void op_ldy_dp();
-void op_ora_dp();
-void op_sbc_dp();
-void op_adc_dpx();
-void op_and_dpx();
-void op_bit_dpx();
-void op_cmp_dpx();
-void op_eor_dpx();
-void op_lda_dpx();
-void op_ldy_dpx();
-void op_ora_dpx();
-void op_sbc_dpx();
-void op_ldx_dpy();
-void op_adc_idp();
-void op_and_idp();
-void op_cmp_idp();
-void op_eor_idp();
-void op_lda_idp();
-void op_ora_idp();
-void op_sbc_idp();
-void op_adc_idpx();
-void op_and_idpx();
-void op_cmp_idpx();
-void op_eor_idpx();
-void op_lda_idpx();
-void op_ora_idpx();
-void op_sbc_idpx();
-void op_adc_idpy();
-void op_and_idpy();
-void op_cmp_idpy();
-void op_eor_idpy();
-void op_lda_idpy();
-void op_ora_idpy();
-void op_sbc_idpy();
-void op_adc_ildp();
-void op_and_ildp();
-void op_cmp_ildp();
-void op_eor_ildp();
-void op_lda_ildp();
-void op_ora_ildp();
-void op_sbc_ildp();
-void op_adc_ildpy();
-void op_and_ildpy();
-void op_cmp_ildpy();
-void op_eor_ildpy();
-void op_lda_ildpy();
-void op_ora_ildpy();
-void op_sbc_ildpy();
-void op_adc_sr();
-void op_and_sr();
-void op_cmp_sr();
-void op_eor_sr();
-void op_lda_sr();
-void op_ora_sr();
-void op_sbc_sr();
-void op_adc_isry();
-void op_and_isry();
-void op_cmp_isry();
-void op_eor_isry();
-void op_lda_isry();
-void op_ora_isry();
-void op_sbc_isry();
-void op_bit_const();
-void op_inc();
-void op_inx();
-void op_iny();
-void op_dec();
-void op_dex();
-void op_dey();
-void op_asl();
-void op_lsr();
-void op_rol();
-void op_ror();
-void op_inc_addr();
-void op_dec_addr();
-void op_asl_addr();
-void op_lsr_addr();
-void op_rol_addr();
-void op_ror_addr();
-void op_trb_addr();
-void op_tsb_addr();
-void op_inc_addrx();
-void op_dec_addrx();
-void op_asl_addrx();
-void op_lsr_addrx();
-void op_rol_addrx();
-void op_ror_addrx();
-void op_inc_dp();
-void op_dec_dp();
-void op_asl_dp();
-void op_lsr_dp();
-void op_rol_dp();
-void op_ror_dp();
-void op_trb_dp();
-void op_tsb_dp();
-void op_inc_dpx();
-void op_dec_dpx();
-void op_asl_dpx();
-void op_lsr_dpx();
-void op_rol_dpx();
-void op_ror_dpx();
-void op_sta_addr();
-void op_stx_addr();
-void op_sty_addr();
-void op_stz_addr();
-void op_sta_addrx();
-void op_stz_addrx();
-void op_sta_addry();
-void op_sta_long();
-void op_sta_longx();
-void op_sta_dp();
-void op_stx_dp();
-void op_sty_dp();
-void op_stz_dp();
-void op_sta_dpx();
-void op_sty_dpx();
-void op_stz_dpx();
-void op_stx_dpy();
-void op_sta_idp();
-void op_sta_ildp();
-void op_sta_idpx();
-void op_sta_idpy();
-void op_sta_ildpy();
-void op_sta_sr();
-void op_sta_isry();
-void op_bcc();
-void op_bcs();
-void op_bne();
-void op_beq();
-void op_bpl();
-void op_bmi();
-void op_bvc();
-void op_bvs();
-void op_bra();
-void op_brl();
-void op_jmp_addr();
-void op_jmp_long();
-void op_jmp_iaddr();
-void op_jmp_iaddrx();
-void op_jmp_iladdr();
-void op_jsr_addr();
-void op_jsr_long();
-void op_jsr_iaddrx();
-void op_rti();
-void op_rts();
-void op_rtl();
-void op_nop();
-void op_wdm();
-void op_xba();
-void op_mvn();
-void op_mvp();
-void op_brk();
-void op_cop();
-void op_stp();
-void op_wai();
-void op_xce();
-void op_clc();
-void op_cld();
-void op_cli();
-void op_clv();
-void op_sec();
-void op_sed();
-void op_sei();
-void op_rep();
-void op_sep();
-void op_tax();
-void op_tay();
-void op_txa();
-void op_txy();
-void op_tya();
-void op_tyx();
-void op_tcd();
-void op_tcs();
-void op_tdc();
-void op_tsc();
-void op_tsx();
-void op_txs();
-void op_pha();
-void op_phx();
-void op_phy();
-void op_phd();
-void op_phb();
-void op_phk();
-void op_php();
-void op_pla();
-void op_plx();
-void op_ply();
-void op_pld();
-void op_plb();
-void op_plp();
-void op_pea();
-void op_pei();
-void op_per();
@@ -1,282 +0,0 @@
-nop(0xea) {
-1:last_cycle();
-  cpu_io();
-}
-
-wdm(0x42) {
-1:last_cycle();
-  op_readpc();
-}
-
-xba(0xeb) {
-1:cpu_io();
-2:last_cycle();
-  cpu_io();
-  regs.a.l ^= regs.a.h;
-  regs.a.h ^= regs.a.l;
-  regs.a.l ^= regs.a.h;
-  regs.p.n = !!(regs.a.l & 0x80);
-  regs.p.z = (regs.a.l == 0);
-}
-
-mvn(0x54, ++),
-mvp(0x44, --) {
-1:dp = op_readpc();
-2:sp = op_readpc();
-3:regs.db = dp;
-  rd.l = op_readlong((sp << 16) | regs.x.w);
-4:op_writelong((dp << 16) | regs.y.w, rd.l);
-5:cpu_io();
-  if(regs.p.x) { regs.x.l$1; regs.y.l$1; }
-  else         { regs.x.w$1; regs.y.w$1; }
-6:last_cycle();
-  cpu_io();
-  if(regs.a.w--)regs.pc.w -= 3;
-}
-
-brk(0x00, 0xfffe, 0xffff, 0xffe6, 0xffe7),
-cop(0x02, 0xfff4, 0xfff5, 0xffe4, 0xffe5) {
-1:op_readpc();
-  if(regs.e)skip;
-2:op_writestack(regs.pc.b);
-3:op_writestack(regs.pc.h);
-4:op_writestack(regs.pc.l);
-5:op_writestack(regs.p);
-6:rd.l = op_readlong((regs.e) ? $1 : $3);
-  regs.pc.b = 0x00;
-  regs.p.i  = 1;
-  regs.p.d  = 0;
-7:last_cycle();
-  rd.h = op_readlong((regs.e) ? $2 : $4);
-  regs.pc.w = rd.w;
-}
-
-stp(0xdb) {
-1:cpu_io();
-  run_state.stp = true;
-2:last_cycle();
-  cpu_io();
-  regs.pc.w--;
-}
-
-wai(0xcb) {
-1:cpu_io();
-  run_state.wai = true;
-2:last_cycle();
-  cpu_io();
-//no wakeup delay if last_cycle() cancelled wai
-  if(run_state.wai == false)end;
-3:last_cycle();
-  cpu_io();
-//sleep another i/o cycle
-//note: this should alert the debugger that wai is continuing...
-  if(run_state.wai == true)status.cycle_pos--;
-//wai wakeup delay (one i/o cycle)
-4:last_cycle();
-  cpu_io();
-}
-
-xce(0xfb) {
-1:last_cycle();
-  cpu_io();
-bool c = regs.p.c;
-  regs.p.c = regs.e;
-  regs.e = c;
-  if(regs.e) {
-    regs.p  |= 0x30;
-    regs.x.h = 0x00;
-    regs.y.h = 0x00;
-    regs.s.h = 0x01;
-  }
-}
-
-clc(0x18, regs.p.c = 0),
-cld(0xd8, regs.p.d = 0),
-cli(0x58, regs.p.i = 0),
-clv(0xb8, regs.p.v = 0),
-sec(0x38, regs.p.c = 1),
-sed(0xf8, regs.p.d = 1),
-sei(0x78, regs.p.i = 1) {
-1:last_cycle();
-  cpu_io();
-  $1;
-}
-
-rep(0xc2, &=~),
-sep(0xe2, |=) {
-1:rd.l = op_readpc();
-2:last_cycle();
-  cpu_io();
-  regs.p $1 rd.l;
-  if(regs.e)regs.p |= 0x30;
-  if(regs.p.x) {
-    regs.x.h = 0x00;
-    regs.y.h = 0x00;
-  }
-}
-
-tax(0xaa, regs.p.x, x, a),
-tay(0xa8, regs.p.x, y, a),
-txa(0x8a, regs.p.m, a, x),
-txy(0x9b, regs.p.x, y, x),
-tya(0x98, regs.p.m, a, y),
-tyx(0xbb, regs.p.x, x, y) {
-1:last_cycle();
-  cpu_io();
-  if($1) {
-    regs.$2.l = regs.$3.l;
-    regs.p.n = !!(regs.$2.l & 0x80);
-    regs.p.z = (regs.$2.l == 0);
-  } else {
-    regs.$2.w = regs.$3.w;
-    regs.p.n = !!(regs.$2.w & 0x8000);
-    regs.p.z = (regs.$2.w == 0);
-  }
-}
-
-tcd(0x5b) {
-1:last_cycle();
-  cpu_io();
-  regs.d.w = regs.a.w;
-  regs.p.n = !!(regs.d.w & 0x8000);
-  regs.p.z = (regs.d.w == 0);
-}
-
-tcs(0x1b) {
-1:last_cycle();
-  cpu_io();
-  regs.s.w = regs.a.w;
-  if(regs.e)regs.s.h = 0x01;
-}
-
-tdc(0x7b) {
-1:last_cycle();
-  cpu_io();
-  regs.a.w = regs.d.w;
-  regs.p.n = !!(regs.a.w & 0x8000);
-  regs.p.z = (regs.a.w == 0);
-}
-
-tsc(0x3b) {
-1:last_cycle();
-  cpu_io();
-  regs.a.w = regs.s.w;
-  if(regs.e) {
-    regs.p.n = !!(regs.a.l & 0x80);
-    regs.p.z = (regs.a.l == 0);
-  } else {
-    regs.p.n = !!(regs.a.w & 0x8000);
-    regs.p.z = (regs.a.w == 0);
-  }
-}
-
-tsx(0xba) {
-1:last_cycle();
-  cpu_io();
-  if(regs.p.x) {
-    regs.x.l = regs.s.l;
-    regs.p.n = !!(regs.x.l & 0x80);
-    regs.p.z = (regs.x.l == 0);
-  } else {
-    regs.x.w = regs.s.w;
-    regs.p.n = !!(regs.x.w & 0x8000);
-    regs.p.z = (regs.x.w == 0);
-  }
-}
-
-txs(0x9a) {
-1:last_cycle();
-  cpu_io();
-  if(regs.e) {
-    regs.s.l = regs.x.l;
-  } else {
-    regs.s.w = regs.x.w;
-  }
-}
-
-pha(0x48, regs.p.m, a),
-phx(0xda, regs.p.x, x),
-phy(0x5a, regs.p.x, y),
-phd(0x0b, 0,        d) {
-1:cpu_io();
-  if($1)skip;
-2:op_writestack(regs.$2.h);
-3:last_cycle();
-  op_writestack(regs.$2.l);
-}
-
-phb(0x8b, regs.db),
-phk(0x4b, regs.pc.b),
-php(0x08, regs.p) {
-1:cpu_io();
-2:last_cycle();
-  op_writestack($1);
-}
-
-pla(0x68, regs.p.m, a),
-plx(0xfa, regs.p.x, x),
-ply(0x7a, regs.p.x, y),
-pld(0x2b, 0,        d) {
-1:cpu_io();
-2:cpu_io();
-3:if($1)last_cycle();
-  regs.$2.l = op_readstack();
-  if($1) {
-    regs.p.n = !!(regs.$2.l & 0x80);
-    regs.p.z = (regs.$2.l == 0);
-    end;
-  }
-4:last_cycle();
-  regs.$2.h = op_readstack();
-  regs.p.n = !!(regs.$2.w & 0x8000);
-  regs.p.z = (regs.$2.w == 0);
-}
-
-plb(0xab) {
-1:cpu_io();
-2:cpu_io();
-3:last_cycle();
-  regs.db = op_readstack();
-  regs.p.n = !!(regs.db & 0x80);
-  regs.p.z = (regs.db == 0);
-}
-
-plp(0x28) {
-1:cpu_io();
-2:cpu_io();
-3:last_cycle();
-  regs.p = op_readstack();
-  if(regs.e)regs.p |= 0x30;
-  if(regs.p.x) {
-    regs.x.h = 0x00;
-    regs.y.h = 0x00;
-  }
-}
-
-pea(0xf4) {
-1:aa.l = op_readpc();
-2:aa.h = op_readpc();
-3:op_writestack(aa.h);
-4:last_cycle();
-  op_writestack(aa.l);
-}
-
-pei(0xd4) {
-1:dp = op_readpc();
-2:cpu_c2();
-3:aa.l = op_readdp(dp);
-4:aa.h = op_readdp(dp + 1);
-5:op_writestack(aa.h);
-6:last_cycle();
-  op_writestack(aa.l);
-}
-
-per(0x62) {
-1:aa.l = op_readpc();
-2:aa.h = op_readpc();
-3:cpu_io();
-  rd.w = regs.pc.d + (int16)aa.w;
-4:op_writestack(rd.h);
-5:last_cycle();
-  op_writestack(rd.l);
-}
@@ -1,864 +0,0 @@
-void bCPU::op_nop() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    last_cycle();
-    cpu_io();
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_wdm() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    last_cycle();
-    op_readpc();
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_xba() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    cpu_io();
-    } break;
-  case 2: {
-    last_cycle();
-    cpu_io();
-    regs.a.l ^= regs.a.h;
-    regs.a.h ^= regs.a.l;
-    regs.a.l ^= regs.a.h;
-    regs.p.n = !!(regs.a.l & 0x80);
-    regs.p.z = (regs.a.l == 0);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_mvn() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp = op_readpc();
-    } break;
-  case 2: {
-    sp = op_readpc();
-    } break;
-  case 3: {
-    regs.db = dp;
-    rd.l = op_readlong((sp << 16) | regs.x.w);
-    } break;
-  case 4: {
-    op_writelong((dp << 16) | regs.y.w, rd.l);
-    } break;
-  case 5: {
-    cpu_io();
-    if(regs.p.x) { regs.x.l++; regs.y.l++; }
-    else         { regs.x.w++; regs.y.w++; }
-    } break;
-  case 6: {
-    last_cycle();
-    cpu_io();
-    if(regs.a.w--)regs.pc.w -= 3;
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_mvp() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp = op_readpc();
-    } break;
-  case 2: {
-    sp = op_readpc();
-    } break;
-  case 3: {
-    regs.db = dp;
-    rd.l = op_readlong((sp << 16) | regs.x.w);
-    } break;
-  case 4: {
-    op_writelong((dp << 16) | regs.y.w, rd.l);
-    } break;
-  case 5: {
-    cpu_io();
-    if(regs.p.x) { regs.x.l--; regs.y.l--; }
-    else         { regs.x.w--; regs.y.w--; }
-    } break;
-  case 6: {
-    last_cycle();
-    cpu_io();
-    if(regs.a.w--)regs.pc.w -= 3;
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_brk() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    op_readpc();
-    if(regs.e)status.cycle_pos++;
-    } break;
-  case 2: {
-    op_writestack(regs.pc.b);
-    } break;
-  case 3: {
-    op_writestack(regs.pc.h);
-    } break;
-  case 4: {
-    op_writestack(regs.pc.l);
-    } break;
-  case 5: {
-    op_writestack(regs.p);
-    } break;
-  case 6: {
-    rd.l = op_readlong((regs.e) ? 0xfffe : 0xffe6);
-    regs.pc.b = 0x00;
-    regs.p.i  = 1;
-    regs.p.d  = 0;
-    } break;
-  case 7: {
-    last_cycle();
-    rd.h = op_readlong((regs.e) ? 0xffff : 0xffe7);
-    regs.pc.w = rd.w;
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_cop() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    op_readpc();
-    if(regs.e)status.cycle_pos++;
-    } break;
-  case 2: {
-    op_writestack(regs.pc.b);
-    } break;
-  case 3: {
-    op_writestack(regs.pc.h);
-    } break;
-  case 4: {
-    op_writestack(regs.pc.l);
-    } break;
-  case 5: {
-    op_writestack(regs.p);
-    } break;
-  case 6: {
-    rd.l = op_readlong((regs.e) ? 0xfff4 : 0xffe4);
-    regs.pc.b = 0x00;
-    regs.p.i  = 1;
-    regs.p.d  = 0;
-    } break;
-  case 7: {
-    last_cycle();
-    rd.h = op_readlong((regs.e) ? 0xfff5 : 0xffe5);
-    regs.pc.w = rd.w;
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_stp() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    cpu_io();
-    run_state.stp = true;
-    } break;
-  case 2: {
-    last_cycle();
-    cpu_io();
-    regs.pc.w--;
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_wai() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    cpu_io();
-    run_state.wai = true;
-    } break;
-  case 2: {
-    last_cycle();
-    cpu_io();
-  //no wakeup delay if last_cycle() cancelled wai
-    if(run_state.wai == false)status.cycle_pos = 0;
-    } break;
-  case 3: {
-    last_cycle();
-    cpu_io();
-  //sleep another i/o cycle
-  //note: this should alert the debugger that wai is continuing...
-    if(run_state.wai == true)status.cycle_pos--;
-  //wai wakeup delay (one i/o cycle)
-    } break;
-  case 4: {
-    last_cycle();
-    cpu_io();
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_xce() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    last_cycle();
-    cpu_io();
-  bool c = regs.p.c;
-    regs.p.c = regs.e;
-    regs.e = c;
-    if(regs.e) {
-      regs.p  |= 0x30;
-      regs.x.h = 0x00;
-      regs.y.h = 0x00;
-      regs.s.h = 0x01;
-    }
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_clc() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    last_cycle();
-    cpu_io();
-    regs.p.c = 0;
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_cld() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    last_cycle();
-    cpu_io();
-    regs.p.d = 0;
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_cli() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    last_cycle();
-    cpu_io();
-    regs.p.i = 0;
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_clv() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    last_cycle();
-    cpu_io();
-    regs.p.v = 0;
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_sec() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    last_cycle();
-    cpu_io();
-    regs.p.c = 1;
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_sed() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    last_cycle();
-    cpu_io();
-    regs.p.d = 1;
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_sei() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    last_cycle();
-    cpu_io();
-    regs.p.i = 1;
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_rep() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    rd.l = op_readpc();
-    } break;
-  case 2: {
-    last_cycle();
-    cpu_io();
-    regs.p &=~ rd.l;
-    if(regs.e)regs.p |= 0x30;
-    if(regs.p.x) {
-      regs.x.h = 0x00;
-      regs.y.h = 0x00;
-    }
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_sep() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    rd.l = op_readpc();
-    } break;
-  case 2: {
-    last_cycle();
-    cpu_io();
-    regs.p |= rd.l;
-    if(regs.e)regs.p |= 0x30;
-    if(regs.p.x) {
-      regs.x.h = 0x00;
-      regs.y.h = 0x00;
-    }
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_tax() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    last_cycle();
-    cpu_io();
-    if(regs.p.x) {
-      regs.x.l = regs.a.l;
-      regs.p.n = !!(regs.x.l & 0x80);
-      regs.p.z = (regs.x.l == 0);
-    } else {
-      regs.x.w = regs.a.w;
-      regs.p.n = !!(regs.x.w & 0x8000);
-      regs.p.z = (regs.x.w == 0);
-    }
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_tay() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    last_cycle();
-    cpu_io();
-    if(regs.p.x) {
-      regs.y.l = regs.a.l;
-      regs.p.n = !!(regs.y.l & 0x80);
-      regs.p.z = (regs.y.l == 0);
-    } else {
-      regs.y.w = regs.a.w;
-      regs.p.n = !!(regs.y.w & 0x8000);
-      regs.p.z = (regs.y.w == 0);
-    }
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_txa() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    last_cycle();
-    cpu_io();
-    if(regs.p.m) {
-      regs.a.l = regs.x.l;
-      regs.p.n = !!(regs.a.l & 0x80);
-      regs.p.z = (regs.a.l == 0);
-    } else {
-      regs.a.w = regs.x.w;
-      regs.p.n = !!(regs.a.w & 0x8000);
-      regs.p.z = (regs.a.w == 0);
-    }
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_txy() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    last_cycle();
-    cpu_io();
-    if(regs.p.x) {
-      regs.y.l = regs.x.l;
-      regs.p.n = !!(regs.y.l & 0x80);
-      regs.p.z = (regs.y.l == 0);
-    } else {
-      regs.y.w = regs.x.w;
-      regs.p.n = !!(regs.y.w & 0x8000);
-      regs.p.z = (regs.y.w == 0);
-    }
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_tya() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    last_cycle();
-    cpu_io();
-    if(regs.p.m) {
-      regs.a.l = regs.y.l;
-      regs.p.n = !!(regs.a.l & 0x80);
-      regs.p.z = (regs.a.l == 0);
-    } else {
-      regs.a.w = regs.y.w;
-      regs.p.n = !!(regs.a.w & 0x8000);
-      regs.p.z = (regs.a.w == 0);
-    }
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_tyx() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    last_cycle();
-    cpu_io();
-    if(regs.p.x) {
-      regs.x.l = regs.y.l;
-      regs.p.n = !!(regs.x.l & 0x80);
-      regs.p.z = (regs.x.l == 0);
-    } else {
-      regs.x.w = regs.y.w;
-      regs.p.n = !!(regs.x.w & 0x8000);
-      regs.p.z = (regs.x.w == 0);
-    }
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_tcd() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    last_cycle();
-    cpu_io();
-    regs.d.w = regs.a.w;
-    regs.p.n = !!(regs.d.w & 0x8000);
-    regs.p.z = (regs.d.w == 0);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_tcs() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    last_cycle();
-    cpu_io();
-    regs.s.w = regs.a.w;
-    if(regs.e)regs.s.h = 0x01;
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_tdc() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    last_cycle();
-    cpu_io();
-    regs.a.w = regs.d.w;
-    regs.p.n = !!(regs.a.w & 0x8000);
-    regs.p.z = (regs.a.w == 0);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_tsc() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    last_cycle();
-    cpu_io();
-    regs.a.w = regs.s.w;
-    if(regs.e) {
-      regs.p.n = !!(regs.a.l & 0x80);
-      regs.p.z = (regs.a.l == 0);
-    } else {
-      regs.p.n = !!(regs.a.w & 0x8000);
-      regs.p.z = (regs.a.w == 0);
-    }
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_tsx() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    last_cycle();
-    cpu_io();
-    if(regs.p.x) {
-      regs.x.l = regs.s.l;
-      regs.p.n = !!(regs.x.l & 0x80);
-      regs.p.z = (regs.x.l == 0);
-    } else {
-      regs.x.w = regs.s.w;
-      regs.p.n = !!(regs.x.w & 0x8000);
-      regs.p.z = (regs.x.w == 0);
-    }
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_txs() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    last_cycle();
-    cpu_io();
-    if(regs.e) {
-      regs.s.l = regs.x.l;
-    } else {
-      regs.s.w = regs.x.w;
-    }
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_pha() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    cpu_io();
-    if(regs.p.m)status.cycle_pos++;
-    } break;
-  case 2: {
-    op_writestack(regs.a.h);
-    } break;
-  case 3: {
-    last_cycle();
-    op_writestack(regs.a.l);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_phx() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    cpu_io();
-    if(regs.p.x)status.cycle_pos++;
-    } break;
-  case 2: {
-    op_writestack(regs.x.h);
-    } break;
-  case 3: {
-    last_cycle();
-    op_writestack(regs.x.l);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_phy() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    cpu_io();
-    if(regs.p.x)status.cycle_pos++;
-    } break;
-  case 2: {
-    op_writestack(regs.y.h);
-    } break;
-  case 3: {
-    last_cycle();
-    op_writestack(regs.y.l);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_phd() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    cpu_io();
-    if(0)status.cycle_pos++;
-    } break;
-  case 2: {
-    op_writestack(regs.       d.h);
-    } break;
-  case 3: {
-    last_cycle();
-    op_writestack(regs.       d.l);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_phb() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    cpu_io();
-    } break;
-  case 2: {
-    last_cycle();
-    op_writestack(regs.db);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_phk() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    cpu_io();
-    } break;
-  case 2: {
-    last_cycle();
-    op_writestack(regs.pc.b);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_php() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    cpu_io();
-    } break;
-  case 2: {
-    last_cycle();
-    op_writestack(regs.p);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_pla() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    cpu_io();
-    } break;
-  case 2: {
-    cpu_io();
-    } break;
-  case 3: {
-    if(regs.p.m)last_cycle();
-    regs.a.l = op_readstack();
-    if(regs.p.m) {
-      regs.p.n = !!(regs.a.l & 0x80);
-      regs.p.z = (regs.a.l == 0);
-      status.cycle_pos = 0;
-    }
-    } break;
-  case 4: {
-    last_cycle();
-    regs.a.h = op_readstack();
-    regs.p.n = !!(regs.a.w & 0x8000);
-    regs.p.z = (regs.a.w == 0);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_plx() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    cpu_io();
-    } break;
-  case 2: {
-    cpu_io();
-    } break;
-  case 3: {
-    if(regs.p.x)last_cycle();
-    regs.x.l = op_readstack();
-    if(regs.p.x) {
-      regs.p.n = !!(regs.x.l & 0x80);
-      regs.p.z = (regs.x.l == 0);
-      status.cycle_pos = 0;
-    }
-    } break;
-  case 4: {
-    last_cycle();
-    regs.x.h = op_readstack();
-    regs.p.n = !!(regs.x.w & 0x8000);
-    regs.p.z = (regs.x.w == 0);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_ply() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    cpu_io();
-    } break;
-  case 2: {
-    cpu_io();
-    } break;
-  case 3: {
-    if(regs.p.x)last_cycle();
-    regs.y.l = op_readstack();
-    if(regs.p.x) {
-      regs.p.n = !!(regs.y.l & 0x80);
-      regs.p.z = (regs.y.l == 0);
-      status.cycle_pos = 0;
-    }
-    } break;
-  case 4: {
-    last_cycle();
-    regs.y.h = op_readstack();
-    regs.p.n = !!(regs.y.w & 0x8000);
-    regs.p.z = (regs.y.w == 0);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_pld() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    cpu_io();
-    } break;
-  case 2: {
-    cpu_io();
-    } break;
-  case 3: {
-    if(0)last_cycle();
-    regs.       d.l = op_readstack();
-    if(0) {
-      regs.p.n = !!(regs.       d.l & 0x80);
-      regs.p.z = (regs.       d.l == 0);
-      status.cycle_pos = 0;
-    }
-    } break;
-  case 4: {
-    last_cycle();
-    regs.       d.h = op_readstack();
-    regs.p.n = !!(regs.       d.w & 0x8000);
-    regs.p.z = (regs.       d.w == 0);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_plb() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    cpu_io();
-    } break;
-  case 2: {
-    cpu_io();
-    } break;
-  case 3: {
-    last_cycle();
-    regs.db = op_readstack();
-    regs.p.n = !!(regs.db & 0x80);
-    regs.p.z = (regs.db == 0);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_plp() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    cpu_io();
-    } break;
-  case 2: {
-    cpu_io();
-    } break;
-  case 3: {
-    last_cycle();
-    regs.p = op_readstack();
-    if(regs.e)regs.p |= 0x30;
-    if(regs.p.x) {
-      regs.x.h = 0x00;
-      regs.y.h = 0x00;
-    }
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_pea() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    aa.l = op_readpc();
-    } break;
-  case 2: {
-    aa.h = op_readpc();
-    } break;
-  case 3: {
-    op_writestack(aa.h);
-    } break;
-  case 4: {
-    last_cycle();
-    op_writestack(aa.l);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_pei() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp = op_readpc();
-    } break;
-  case 2: {
-    cpu_c2();
-    } break;
-  case 3: {
-    aa.l = op_readdp(dp);
-    } break;
-  case 4: {
-    aa.h = op_readdp(dp + 1);
-    } break;
-  case 5: {
-    op_writestack(aa.h);
-    } break;
-  case 6: {
-    last_cycle();
-    op_writestack(aa.l);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_per() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    aa.l = op_readpc();
-    } break;
-  case 2: {
-    aa.h = op_readpc();
-    } break;
-  case 3: {
-    cpu_io();
-    rd.w = regs.pc.d + (int16)aa.w;
-    } break;
-  case 4: {
-    op_writestack(rd.h);
-    } break;
-  case 5: {
-    last_cycle();
-    op_writestack(rd.l);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
@@ -1,160 +0,0 @@
-bcc(0x90, !regs.p.c),
-bcs(0xb0, regs.p.c),
-bne(0xd0, !regs.p.z),
-beq(0xf0, regs.p.z),
-bpl(0x10, !regs.p.n),
-bmi(0x30, regs.p.n),
-bvc(0x50, !regs.p.v),
-bvs(0x70, regs.p.v) {
-1:if(!$1)last_cycle();
-  rd.l = op_readpc();
-  if($1) {
-    aa.w = regs.pc.d + (int8)rd.l;
-    regs.pc.w = aa.w;
-  } else {
-    end;
-  }
-2:cpu_c6(aa.w);
-3:last_cycle();
-  cpu_io();
-}
-
-bra(0x80) {
-1:rd.l = op_readpc();
-  aa.w = regs.pc.d + (int8)rd.l;
-  regs.pc.w = aa.w;
-2:cpu_c6(aa.w);
-3:last_cycle();
-  cpu_io();
-}
-
-brl(0x82) {
-1:rd.l = op_readpc();
-2:rd.h = op_readpc();
-3:last_cycle();
-  cpu_io();
-  regs.pc.w = regs.pc.d + (int16)rd.w;
-}
-
-jmp_addr(0x4c) {
-1:rd.l = op_readpc();
-2:last_cycle();
-  rd.h = op_readpc();
-  regs.pc.w = rd.w;
-}
-
-jmp_long(0x5c) {
-1:rd.l = op_readpc();
-2:rd.h = op_readpc();
-3:last_cycle();
-  rd.b = op_readpc();
-  regs.pc.d = rd.d & 0xffffff;
-}
-
-jmp_iaddr(0x6c) {
-1:aa.l = op_readpc();
-2:aa.h = op_readpc();
-3:rd.l = op_readaddr(aa.w);
-4:last_cycle();
-  rd.h = op_readaddr(aa.w + 1);
-  regs.pc.w = rd.w;
-}
-
-jmp_iaddrx(0x7c) {
-1:aa.l = op_readpc();
-2:aa.h = op_readpc();
-3:cpu_io();
-4:rd.l = op_readpbr(aa.w + regs.x.w);
-5:last_cycle();
-  rd.h = op_readpbr(aa.w + regs.x.w + 1);
-  regs.pc.w = rd.w;
-}
-
-jmp_iladdr(0xdc) {
-1:aa.l = op_readpc();
-2:aa.h = op_readpc();
-3:rd.l = op_readaddr(aa.w);
-4:rd.h = op_readaddr(aa.w + 1);
-5:last_cycle();
-  rd.b = op_readaddr(aa.w + 2);
-  regs.pc.d = rd.d & 0xffffff;
-}
-
-jsr_addr(0x20) {
-1:aa.l = op_readpc();
-2:aa.h = op_readpc();
-3:cpu_io();
-4:regs.pc.w--;
-  op_writestack(regs.pc.h);
-5:last_cycle();
-  op_writestack(regs.pc.l);
-  regs.pc.w = aa.w;
-}
-
-jsr_long(0x22) {
-1:aa.l = op_readpc();
-2:aa.h = op_readpc();
-3:op_writestack(regs.pc.b);
-4:cpu_io();
-5:aa.b = op_readpc();
-6:regs.pc.w--;
-  op_writestack(regs.pc.h);
-7:last_cycle();
-  op_writestack(regs.pc.l);
-  regs.pc.d = aa.d & 0xffffff;
-}
-
-jsr_iaddrx(0xfc) {
-1:aa.l = op_readpc();
-2:op_writestack(regs.pc.h);
-3:op_writestack(regs.pc.l);
-4:aa.h = op_readpc();
-5:cpu_io();
-6:rd.l = op_readpbr(aa.w + regs.x.w);
-7:last_cycle();
-  rd.h = op_readpbr(aa.w + regs.x.w + 1);
-  regs.pc.w = rd.w;
-}
-
-rti(0x40) {
-1:cpu_io();
-2:cpu_io();
-3:regs.p = op_readstack();
-  if(regs.e)regs.p |= 0x30;
-  if(regs.p.x) {
-    regs.x.h = 0x00;
-    regs.y.h = 0x00;
-  }
-4:rd.l = op_readstack();
-5:if(regs.e)last_cycle();
-  rd.h = op_readstack();
-  if(regs.e) {
-    regs.pc.w = rd.w;
-    end;
-  }
-6:last_cycle();
-  rd.b = op_readstack();
-  regs.pc.d = rd.d & 0xffffff;
-}
-
-rts(0x60) {
-1:cpu_io();
-2:cpu_io();
-3:rd.l = op_readstack();
-4:rd.h = op_readstack();
-5:last_cycle();
-  cpu_io();
-  regs.pc.w = rd.w;
-  regs.pc.w++;
-}
-
-rtl(0x6b) {
-1:cpu_io();
-2:cpu_io();
-3:rd.l = op_readstack();
-4:rd.h = op_readstack();
-5:last_cycle();
-  rd.b = op_readstack();
-  regs.pc.d = rd.d & 0xffffff;
-  regs.pc.w++;
-}
@@ -1,483 +0,0 @@
-void bCPU::op_bcc() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    if(!!regs.p.c)last_cycle();
-    rd.l = op_readpc();
-    if(!regs.p.c) {
-      aa.w = regs.pc.d + (int8)rd.l;
-      regs.pc.w = aa.w;
-    } else {
-      status.cycle_pos = 0;
-    }
-    } break;
-  case 2: {
-    cpu_c6(aa.w);
-    } break;
-  case 3: {
-    last_cycle();
-    cpu_io();
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_bcs() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    if(!regs.p.c)last_cycle();
-    rd.l = op_readpc();
-    if(regs.p.c) {
-      aa.w = regs.pc.d + (int8)rd.l;
-      regs.pc.w = aa.w;
-    } else {
-      status.cycle_pos = 0;
-    }
-    } break;
-  case 2: {
-    cpu_c6(aa.w);
-    } break;
-  case 3: {
-    last_cycle();
-    cpu_io();
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_bne() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    if(!!regs.p.z)last_cycle();
-    rd.l = op_readpc();
-    if(!regs.p.z) {
-      aa.w = regs.pc.d + (int8)rd.l;
-      regs.pc.w = aa.w;
-    } else {
-      status.cycle_pos = 0;
-    }
-    } break;
-  case 2: {
-    cpu_c6(aa.w);
-    } break;
-  case 3: {
-    last_cycle();
-    cpu_io();
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_beq() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    if(!regs.p.z)last_cycle();
-    rd.l = op_readpc();
-    if(regs.p.z) {
-      aa.w = regs.pc.d + (int8)rd.l;
-      regs.pc.w = aa.w;
-    } else {
-      status.cycle_pos = 0;
-    }
-    } break;
-  case 2: {
-    cpu_c6(aa.w);
-    } break;
-  case 3: {
-    last_cycle();
-    cpu_io();
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_bpl() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    if(!!regs.p.n)last_cycle();
-    rd.l = op_readpc();
-    if(!regs.p.n) {
-      aa.w = regs.pc.d + (int8)rd.l;
-      regs.pc.w = aa.w;
-    } else {
-      status.cycle_pos = 0;
-    }
-    } break;
-  case 2: {
-    cpu_c6(aa.w);
-    } break;
-  case 3: {
-    last_cycle();
-    cpu_io();
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_bmi() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    if(!regs.p.n)last_cycle();
-    rd.l = op_readpc();
-    if(regs.p.n) {
-      aa.w = regs.pc.d + (int8)rd.l;
-      regs.pc.w = aa.w;
-    } else {
-      status.cycle_pos = 0;
-    }
-    } break;
-  case 2: {
-    cpu_c6(aa.w);
-    } break;
-  case 3: {
-    last_cycle();
-    cpu_io();
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_bvc() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    if(!!regs.p.v)last_cycle();
-    rd.l = op_readpc();
-    if(!regs.p.v) {
-      aa.w = regs.pc.d + (int8)rd.l;
-      regs.pc.w = aa.w;
-    } else {
-      status.cycle_pos = 0;
-    }
-    } break;
-  case 2: {
-    cpu_c6(aa.w);
-    } break;
-  case 3: {
-    last_cycle();
-    cpu_io();
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_bvs() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    if(!regs.p.v)last_cycle();
-    rd.l = op_readpc();
-    if(regs.p.v) {
-      aa.w = regs.pc.d + (int8)rd.l;
-      regs.pc.w = aa.w;
-    } else {
-      status.cycle_pos = 0;
-    }
-    } break;
-  case 2: {
-    cpu_c6(aa.w);
-    } break;
-  case 3: {
-    last_cycle();
-    cpu_io();
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_bra() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    rd.l = op_readpc();
-    aa.w = regs.pc.d + (int8)rd.l;
-    regs.pc.w = aa.w;
-    } break;
-  case 2: {
-    cpu_c6(aa.w);
-    } break;
-  case 3: {
-    last_cycle();
-    cpu_io();
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_brl() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    rd.l = op_readpc();
-    } break;
-  case 2: {
-    rd.h = op_readpc();
-    } break;
-  case 3: {
-    last_cycle();
-    cpu_io();
-    regs.pc.w = regs.pc.d + (int16)rd.w;
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_jmp_addr() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    rd.l = op_readpc();
-    } break;
-  case 2: {
-    last_cycle();
-    rd.h = op_readpc();
-    regs.pc.w = rd.w;
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_jmp_long() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    rd.l = op_readpc();
-    } break;
-  case 2: {
-    rd.h = op_readpc();
-    } break;
-  case 3: {
-    last_cycle();
-    rd.b = op_readpc();
-    regs.pc.d = rd.d & 0xffffff;
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_jmp_iaddr() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    aa.l = op_readpc();
-    } break;
-  case 2: {
-    aa.h = op_readpc();
-    } break;
-  case 3: {
-    rd.l = op_readaddr(aa.w);
-    } break;
-  case 4: {
-    last_cycle();
-    rd.h = op_readaddr(aa.w + 1);
-    regs.pc.w = rd.w;
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_jmp_iaddrx() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    aa.l = op_readpc();
-    } break;
-  case 2: {
-    aa.h = op_readpc();
-    } break;
-  case 3: {
-    cpu_io();
-    } break;
-  case 4: {
-    rd.l = op_readpbr(aa.w + regs.x.w);
-    } break;
-  case 5: {
-    last_cycle();
-    rd.h = op_readpbr(aa.w + regs.x.w + 1);
-    regs.pc.w = rd.w;
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_jmp_iladdr() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    aa.l = op_readpc();
-    } break;
-  case 2: {
-    aa.h = op_readpc();
-    } break;
-  case 3: {
-    rd.l = op_readaddr(aa.w);
-    } break;
-  case 4: {
-    rd.h = op_readaddr(aa.w + 1);
-    } break;
-  case 5: {
-    last_cycle();
-    rd.b = op_readaddr(aa.w + 2);
-    regs.pc.d = rd.d & 0xffffff;
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_jsr_addr() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    aa.l = op_readpc();
-    } break;
-  case 2: {
-    aa.h = op_readpc();
-    } break;
-  case 3: {
-    cpu_io();
-    } break;
-  case 4: {
-    regs.pc.w--;
-    op_writestack(regs.pc.h);
-    } break;
-  case 5: {
-    last_cycle();
-    op_writestack(regs.pc.l);
-    regs.pc.w = aa.w;
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_jsr_long() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    aa.l = op_readpc();
-    } break;
-  case 2: {
-    aa.h = op_readpc();
-    } break;
-  case 3: {
-    op_writestack(regs.pc.b);
-    } break;
-  case 4: {
-    cpu_io();
-    } break;
-  case 5: {
-    aa.b = op_readpc();
-    } break;
-  case 6: {
-    regs.pc.w--;
-    op_writestack(regs.pc.h);
-    } break;
-  case 7: {
-    last_cycle();
-    op_writestack(regs.pc.l);
-    regs.pc.d = aa.d & 0xffffff;
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_jsr_iaddrx() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    aa.l = op_readpc();
-    } break;
-  case 2: {
-    op_writestack(regs.pc.h);
-    } break;
-  case 3: {
-    op_writestack(regs.pc.l);
-    } break;
-  case 4: {
-    aa.h = op_readpc();
-    } break;
-  case 5: {
-    cpu_io();
-    } break;
-  case 6: {
-    rd.l = op_readpbr(aa.w + regs.x.w);
-    } break;
-  case 7: {
-    last_cycle();
-    rd.h = op_readpbr(aa.w + regs.x.w + 1);
-    regs.pc.w = rd.w;
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_rti() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    cpu_io();
-    } break;
-  case 2: {
-    cpu_io();
-    } break;
-  case 3: {
-    regs.p = op_readstack();
-    if(regs.e)regs.p |= 0x30;
-    if(regs.p.x) {
-      regs.x.h = 0x00;
-      regs.y.h = 0x00;
-    }
-    } break;
-  case 4: {
-    rd.l = op_readstack();
-    } break;
-  case 5: {
-    if(regs.e)last_cycle();
-    rd.h = op_readstack();
-    if(regs.e) {
-      regs.pc.w = rd.w;
-      status.cycle_pos = 0;
-    }
-    } break;
-  case 6: {
-    last_cycle();
-    rd.b = op_readstack();
-    regs.pc.d = rd.d & 0xffffff;
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_rts() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    cpu_io();
-    } break;
-  case 2: {
-    cpu_io();
-    } break;
-  case 3: {
-    rd.l = op_readstack();
-    } break;
-  case 4: {
-    rd.h = op_readstack();
-    } break;
-  case 5: {
-    last_cycle();
-    cpu_io();
-    regs.pc.w = rd.w;
-    regs.pc.w++;
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_rtl() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    cpu_io();
-    } break;
-  case 2: {
-    cpu_io();
-    } break;
-  case 3: {
-    rd.l = op_readstack();
-    } break;
-  case 4: {
-    rd.h = op_readstack();
-    } break;
-  case 5: {
-    last_cycle();
-    rd.b = op_readstack();
-    regs.pc.d = rd.d & 0xffffff;
-    regs.pc.w++;
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
@@ -1,317 +0,0 @@
-adc_const(0x69, adc, regs.p.m),
-and_const(0x29, and, regs.p.m),
-cmp_const(0xc9, cmp, regs.p.m),
-cpx_const(0xe0, cpx, regs.p.x),
-cpy_const(0xc0, cpy, regs.p.x),
-eor_const(0x49, eor, regs.p.m),
-lda_const(0xa9, lda, regs.p.m),
-ldx_const(0xa2, ldx, regs.p.x),
-ldy_const(0xa0, ldy, regs.p.x),
-ora_const(0x09, ora, regs.p.m),
-sbc_const(0xe9, sbc, regs.p.m) {
-1:if($2)last_cycle();
-  rd.l = op_readpc();
-  if($2) { op_$1_b(); end; }
-2:last_cycle();
-  rd.h = op_readpc();
-  op_$1_w();
-}
-
-adc_addr(0x6d, adc, regs.p.m),
-and_addr(0x2d, and, regs.p.m),
-bit_addr(0x2c, bit, regs.p.m),
-cmp_addr(0xcd, cmp, regs.p.m),
-cpx_addr(0xec, cpx, regs.p.x),
-cpy_addr(0xcc, cpy, regs.p.x),
-eor_addr(0x4d, eor, regs.p.m),
-lda_addr(0xad, lda, regs.p.m),
-ldx_addr(0xae, ldx, regs.p.x),
-ldy_addr(0xac, ldy, regs.p.x),
-ora_addr(0x0d, ora, regs.p.m),
-sbc_addr(0xed, sbc, regs.p.m) {
-1:aa.l = op_readpc();
-2:aa.h = op_readpc();
-3:if($2)last_cycle();
-  rd.l = op_readdbr(aa.w);
-  if($2) { op_$1_b(); end; }
-4:last_cycle();
-  rd.h = op_readdbr(aa.w + 1);
-  op_$1_w();
-}
-
-adc_addrx(0x7d, adc, regs.p.m),
-and_addrx(0x3d, and, regs.p.m),
-bit_addrx(0x3c, bit, regs.p.m),
-cmp_addrx(0xdd, cmp, regs.p.m),
-eor_addrx(0x5d, eor, regs.p.m),
-lda_addrx(0xbd, lda, regs.p.m),
-ldy_addrx(0xbc, ldy, regs.p.x),
-ora_addrx(0x1d, ora, regs.p.m),
-sbc_addrx(0xfd, sbc, regs.p.m) {
-1:aa.l = op_readpc();
-2:aa.h = op_readpc();
-3:cpu_c4(aa.w, aa.w + regs.x.w);
-4:if($2)last_cycle();
-  rd.l = op_readdbr(aa.w + regs.x.w);
-  if($2) { op_$1_b(); end; }
-5:last_cycle();
-  rd.h = op_readdbr(aa.w + regs.x.w + 1);
-  op_$1_w();
-}
-
-adc_addry(0x79, adc, regs.p.m),
-and_addry(0x39, and, regs.p.m),
-cmp_addry(0xd9, cmp, regs.p.m),
-eor_addry(0x59, eor, regs.p.m),
-lda_addry(0xb9, lda, regs.p.m),
-ldx_addry(0xbe, ldx, regs.p.x),
-ora_addry(0x19, ora, regs.p.m),
-sbc_addry(0xf9, sbc, regs.p.m) {
-1:aa.l = op_readpc();
-2:aa.h = op_readpc();
-3:cpu_c4(aa.w, aa.w + regs.y.w);
-4:if($2)last_cycle();
-  rd.l = op_readdbr(aa.w + regs.y.w);
-  if($2) { op_$1_b(); end; }
-5:last_cycle();
-  rd.h = op_readdbr(aa.w + regs.y.w + 1);
-  op_$1_w();
-}
-
-adc_long(0x6f, adc, regs.p.m),
-and_long(0x2f, and, regs.p.m),
-cmp_long(0xcf, cmp, regs.p.m),
-eor_long(0x4f, eor, regs.p.m),
-lda_long(0xaf, lda, regs.p.m),
-ora_long(0x0f, ora, regs.p.m),
-sbc_long(0xef, sbc, regs.p.m) {
-1:aa.l = op_readpc();
-2:aa.h = op_readpc();
-3:aa.b = op_readpc();
-4:if($2)last_cycle();
-  rd.l = op_readlong(aa.d);
-  if($2) { op_$1_b(); end; }
-5:last_cycle();
-  rd.h = op_readlong(aa.d + 1);
-  op_$1_w();
-}
-
-adc_longx(0x7f, adc, regs.p.m),
-and_longx(0x3f, and, regs.p.m),
-cmp_longx(0xdf, cmp, regs.p.m),
-eor_longx(0x5f, eor, regs.p.m),
-lda_longx(0xbf, lda, regs.p.m),
-ora_longx(0x1f, ora, regs.p.m),
-sbc_longx(0xff, sbc, regs.p.m) {
-1:aa.l = op_readpc();
-2:aa.h = op_readpc();
-3:aa.b = op_readpc();
-4:if($2)last_cycle();
-  rd.l = op_readlong(aa.d + regs.x.w);
-  if($2) { op_$1_b(); end; }
-5:last_cycle();
-  rd.h = op_readlong(aa.d + regs.x.w + 1);
-  op_$1_w();
-}
-
-adc_dp(0x65, adc, regs.p.m),
-and_dp(0x25, and, regs.p.m),
-bit_dp(0x24, bit, regs.p.m),
-cmp_dp(0xc5, cmp, regs.p.m),
-cpx_dp(0xe4, cpx, regs.p.x),
-cpy_dp(0xc4, cpy, regs.p.x),
-eor_dp(0x45, eor, regs.p.m),
-lda_dp(0xa5, lda, regs.p.m),
-ldx_dp(0xa6, ldx, regs.p.x),
-ldy_dp(0xa4, ldy, regs.p.x),
-ora_dp(0x05, ora, regs.p.m),
-sbc_dp(0xe5, sbc, regs.p.m) {
-1:dp = op_readpc();
-2:cpu_c2();
-3:if($2)last_cycle();
-  rd.l = op_readdp(dp);
-  if($2) { op_$1_b(); end; }
-4:last_cycle();
-  rd.h = op_readdp(dp + 1);
-  op_$1_w();
-}
-
-adc_dpx(0x75, adc, regs.p.m),
-and_dpx(0x35, and, regs.p.m),
-bit_dpx(0x34, bit, regs.p.m),
-cmp_dpx(0xd5, cmp, regs.p.m),
-eor_dpx(0x55, eor, regs.p.m),
-lda_dpx(0xb5, lda, regs.p.m),
-ldy_dpx(0xb4, ldy, regs.p.x),
-ora_dpx(0x15, ora, regs.p.m),
-sbc_dpx(0xf5, sbc, regs.p.m) {
-1:dp = op_readpc();
-2:cpu_c2();
-3:cpu_io();
-4:if($2)last_cycle();
-  rd.l = op_readdp(dp + regs.x.w);
-  if($2) { op_$1_b(); end; }
-5:last_cycle();
-  rd.h = op_readdp(dp + regs.x.w + 1);
-  op_$1_w();
-}
-
-ldx_dpy(0xb6, ldx, regs.p.x) {
-1:dp = op_readpc();
-2:cpu_c2();
-3:cpu_io();
-4:if($2)last_cycle();
-  rd.l = op_readdp(dp + regs.y.w);
-  if($2) { op_$1_b(); end; }
-5:last_cycle();
-  rd.h = op_readdp(dp + regs.y.w + 1);
-  op_$1_w();
-}
-
-adc_idp(0x72, adc, regs.p.m),
-and_idp(0x32, and, regs.p.m),
-cmp_idp(0xd2, cmp, regs.p.m),
-eor_idp(0x52, eor, regs.p.m),
-lda_idp(0xb2, lda, regs.p.m),
-ora_idp(0x12, ora, regs.p.m),
-sbc_idp(0xf2, sbc, regs.p.m) {
-1:dp = op_readpc();
-2:cpu_c2();
-3:aa.l = op_readdp(dp);
-4:aa.h = op_readdp(dp + 1);
-5:if($2)last_cycle();
-  rd.l = op_readdbr(aa.w);
-  if($2) { op_$1_b(); end; }
-6:last_cycle();
-  rd.h = op_readdbr(aa.w + 1);
-  op_$1_w();
-}
-
-adc_idpx(0x61, adc, regs.p.m),
-and_idpx(0x21, and, regs.p.m),
-cmp_idpx(0xc1, cmp, regs.p.m),
-eor_idpx(0x41, eor, regs.p.m),
-lda_idpx(0xa1, lda, regs.p.m),
-ora_idpx(0x01, ora, regs.p.m),
-sbc_idpx(0xe1, sbc, regs.p.m) {
-1:dp = op_readpc();
-2:cpu_c2();
-3:cpu_io();
-4:aa.l = op_readdp(dp + regs.x.w);
-5:aa.h = op_readdp(dp + regs.x.w + 1);
-6:if($2)last_cycle();
-  rd.l = op_readdbr(aa.w);
-  if($2) { op_$1_b(); end; }
-7:last_cycle();
-  rd.h = op_readdbr(aa.w + 1);
-  op_$1_w();
-}
-
-adc_idpy(0x71, adc, regs.p.m),
-and_idpy(0x31, and, regs.p.m),
-cmp_idpy(0xd1, cmp, regs.p.m),
-eor_idpy(0x51, eor, regs.p.m),
-lda_idpy(0xb1, lda, regs.p.m),
-ora_idpy(0x11, ora, regs.p.m),
-sbc_idpy(0xf1, sbc, regs.p.m) {
-1:dp = op_readpc();
-2:cpu_c2();
-3:aa.l = op_readdp(dp);
-4:aa.h = op_readdp(dp + 1);
-5:cpu_c4(aa.w, aa.w + regs.y.w);
-6:if($2)last_cycle();
-  rd.l = op_readdbr(aa.w + regs.y.w);
-  if($2) { op_$1_b(); end; }
-7:last_cycle();
-  rd.h = op_readdbr(aa.w + regs.y.w + 1);
-  op_$1_w();
-}
-
-adc_ildp(0x67, adc, regs.p.m),
-and_ildp(0x27, and, regs.p.m),
-cmp_ildp(0xc7, cmp, regs.p.m),
-eor_ildp(0x47, eor, regs.p.m),
-lda_ildp(0xa7, lda, regs.p.m),
-ora_ildp(0x07, ora, regs.p.m),
-sbc_ildp(0xe7, sbc, regs.p.m) {
-1:dp = op_readpc();
-2:cpu_c2();
-3:aa.l = op_readdp(dp);
-4:aa.h = op_readdp(dp + 1);
-5:aa.b = op_readdp(dp + 2);
-6:if($2)last_cycle();
-  rd.l = op_readlong(aa.d);
-  if($2) { op_$1_b(); end; }
-7:last_cycle();
-  rd.h = op_readlong(aa.d + 1);
-  op_$1_w();
-}
-
-adc_ildpy(0x77, adc, regs.p.m),
-and_ildpy(0x37, and, regs.p.m),
-cmp_ildpy(0xd7, cmp, regs.p.m),
-eor_ildpy(0x57, eor, regs.p.m),
-lda_ildpy(0xb7, lda, regs.p.m),
-ora_ildpy(0x17, ora, regs.p.m),
-sbc_ildpy(0xf7, sbc, regs.p.m) {
-1:dp = op_readpc();
-2:cpu_c2();
-3:aa.l = op_readdp(dp);
-4:aa.h = op_readdp(dp + 1);
-5:aa.b = op_readdp(dp + 2);
-6:if($2)last_cycle();
-  rd.l = op_readlong(aa.d + regs.y.w);
-  if($2) { op_$1_b(); end; }
-7:last_cycle();
-  rd.h = op_readlong(aa.d + regs.y.w + 1);
-  op_$1_w();
-}
-
-adc_sr(0x63, adc, regs.p.m),
-and_sr(0x23, and, regs.p.m),
-cmp_sr(0xc3, cmp, regs.p.m),
-eor_sr(0x43, eor, regs.p.m),
-lda_sr(0xa3, lda, regs.p.m),
-ora_sr(0x03, ora, regs.p.m),
-sbc_sr(0xe3, sbc, regs.p.m) {
-1:sp = op_readpc();
-2:cpu_io();
-3:if($2)last_cycle();
-  rd.l = op_readsp(sp);
-  if($2) { op_$1_b(); end; }
-4:last_cycle();
-  rd.h = op_readsp(sp + 1);
-  op_$1_w();
-}
-
-adc_isry(0x73, adc),
-and_isry(0x33, and),
-cmp_isry(0xd3, cmp),
-eor_isry(0x53, eor),
-lda_isry(0xb3, lda),
-ora_isry(0x13, ora),
-sbc_isry(0xf3, sbc) {
-1:sp = op_readpc();
-2:cpu_io();
-3:aa.l = op_readsp(sp);
-4:aa.h = op_readsp(sp + 1);
-5:cpu_io();
-6:if(regs.p.m)last_cycle();
-  rd.l = op_readdbr(aa.w + regs.y.w);
-  if(regs.p.m) { op_$1_b(); end; }
-7:last_cycle();
-  rd.h = op_readdbr(aa.w + regs.y.w + 1);
-  op_$1_w();
-}
-
-bit_const(0x89) {
-1:if(regs.p.m)last_cycle();
-  rd.l = op_readpc();
-  if(regs.p.m) {
-    regs.p.z = ((rd.l & regs.a.l) == 0);
-    end;
-  }
-2:last_cycle();
-  rd.h = op_readpc();
-  regs.p.z = ((rd.w & regs.a.w) == 0);
-}
@@ -1,185 +0,0 @@
-inc(0x1a, regs.p.m, a),
-inx(0xe8, regs.p.x, x),
-iny(0xc8, regs.p.x, y) {
-1:last_cycle();
-  cpu_io();
-  if($1) {
-    regs.$2.l++;
-    regs.p.n = !!(regs.$2.l & 0x80);
-    regs.p.z = (regs.$2.l == 0);
-  } else {
-    regs.$2.w++;
-    regs.p.n = !!(regs.$2.w & 0x8000);
-    regs.p.z = (regs.$2.w == 0);
-  }
-}
-
-dec(0x3a, regs.p.m, a),
-dex(0xca, regs.p.x, x),
-dey(0x88, regs.p.x, y) {
-1:last_cycle();
-  cpu_io();
-  if($1) {
-    regs.$2.l--;
-    regs.p.n = !!(regs.$2.l & 0x80);
-    regs.p.z = (regs.$2.l == 0);
-  } else {
-    regs.$2.w--;
-    regs.p.n = !!(regs.$2.w & 0x8000);
-    regs.p.z = (regs.$2.w == 0);
-  }
-}
-
-asl(0x0a) {
-1:last_cycle();
-  cpu_io();
-  if(regs.p.m) {
-    regs.p.c = !!(regs.a.l & 0x80);
-    regs.a.l <<= 1;
-    regs.p.n = !!(regs.a.l & 0x80);
-    regs.p.z = (regs.a.l == 0);
-  } else {
-    regs.p.c = !!(regs.a.w & 0x8000);
-    regs.a.w <<= 1;
-    regs.p.n = !!(regs.a.w & 0x8000);
-    regs.p.z = (regs.a.w == 0);
-  }
-}
-
-lsr(0x4a) {
-1:last_cycle();
-  cpu_io();
-  if(regs.p.m) {
-    regs.p.c = regs.a.l & 1;
-    regs.a.l >>= 1;
-    regs.p.n = !!(regs.a.l & 0x80);
-    regs.p.z = (regs.a.l == 0);
-  } else {
-    regs.p.c = regs.a.w & 1;
-    regs.a.w >>= 1;
-    regs.p.n = !!(regs.a.w & 0x8000);
-    regs.p.z = (regs.a.w == 0);
-  }
-}
-
-rol(0x2a) {
-1:last_cycle();
-  cpu_io();
-  uint16 c = regs.p.c;
-  if(regs.p.m) {
-    regs.p.c = !!(regs.a.l & 0x80);
-    regs.a.l <<= 1;
-    regs.a.l |= c;
-    regs.p.n = !!(regs.a.l & 0x80);
-    regs.p.z = (regs.a.l == 0);
-  } else {
-    regs.p.c = !!(regs.a.w & 0x8000);
-    regs.a.w <<= 1;
-    regs.a.w |= c;
-    regs.p.n = !!(regs.a.w & 0x8000);
-    regs.p.z = (regs.a.w == 0);
-  }
-}
-
-ror(0x6a) {
-1:last_cycle();
-  cpu_io();
-  uint16 c;
-  if(regs.p.m) {
-    c = (regs.p.c)?0x80:0;
-    regs.p.c = regs.a.l & 1;
-    regs.a.l >>= 1;
-    regs.a.l |= c;
-    regs.p.n = !!(regs.a.l & 0x80);
-    regs.p.z = (regs.a.l == 0);
-  } else {
-    c = (regs.p.c)?0x8000:0;
-    regs.p.c = regs.a.w & 1;
-    regs.a.w >>= 1;
-    regs.a.w |= c;
-    regs.p.n = !!(regs.a.w & 0x8000);
-    regs.p.z = (regs.a.w == 0);
-  }
-}
-
-inc_addr(0xee, inc),
-dec_addr(0xce, dec),
-asl_addr(0x0e, asl),
-lsr_addr(0x4e, lsr),
-rol_addr(0x2e, rol),
-ror_addr(0x6e, ror),
-trb_addr(0x1c, trb),
-tsb_addr(0x0c, tsb) {
-1:aa.l = op_readpc();
-2:aa.h = op_readpc();
-3:rd.l = op_readdbr(aa.w);
-  if(regs.p.m)skip;
-4:rd.h = op_readdbr(aa.w + 1);
-5:cpu_io();
-  if(regs.p.m) { op_$1_b(); skip; }
-  else op_$1_w();
-6:op_writedbr(aa.w + 1, rd.h);
-7:last_cycle();
-  op_writedbr(aa.w,     rd.l);
-}
-
-inc_addrx(0xfe, inc),
-dec_addrx(0xde, dec),
-asl_addrx(0x1e, asl),
-lsr_addrx(0x5e, lsr),
-rol_addrx(0x3e, rol),
-ror_addrx(0x7e, ror) {
-1:aa.l = op_readpc();
-2:aa.h = op_readpc();
-3:cpu_io();
-4:rd.l = op_readdbr(aa.w + regs.x.w);
-  if(regs.p.m)skip;
-5:rd.h = op_readdbr(aa.w + regs.x.w + 1);
-6:cpu_io();
-  if(regs.p.m) { op_$1_b(); skip; }
-  else op_$1_w();
-7:op_writedbr(aa.w + regs.x.w + 1, rd.h);
-8:last_cycle();
-  op_writedbr(aa.w + regs.x.w,     rd.l);
-}
-
-inc_dp(0xe6, inc),
-dec_dp(0xc6, dec),
-asl_dp(0x06, asl),
-lsr_dp(0x46, lsr),
-rol_dp(0x26, rol),
-ror_dp(0x66, ror),
-trb_dp(0x14, trb),
-tsb_dp(0x04, tsb) {
-1:dp = op_readpc();
-2:cpu_c2();
-3:rd.l = op_readdp(dp);
-  if(regs.p.m)skip;
-4:rd.h = op_readdp(dp + 1);
-5:cpu_io();
-  if(regs.p.m) { op_$1_b(); skip; }
-  else op_$1_w();
-6:op_writedp(dp + 1, rd.h);
-7:last_cycle();
-  op_writedp(dp,     rd.l);
-}
-
-inc_dpx(0xf6, inc),
-dec_dpx(0xd6, dec),
-asl_dpx(0x16, asl),
-lsr_dpx(0x56, lsr),
-rol_dpx(0x36, rol),
-ror_dpx(0x76, ror) {
-1:dp = op_readpc();
-2:cpu_c2();
-3:cpu_io();
-4:rd.l = op_readdp(dp + regs.x.w);
-  if(regs.p.m)skip;
-5:rd.h = op_readdp(dp + regs.x.w + 1);
-6:cpu_io();
-  if(regs.p.m) { op_$1_b(); skip; }
-  else op_$1_w();
-7:op_writedp(dp + regs.x.w + 1, rd.h);
-8:last_cycle();
-  op_writedp(dp + regs.x.w,     rd.l);
-}
@@ -1,181 +0,0 @@
-sta_addr(0x8d, regs.p.m, regs.a.w),
-stx_addr(0x8e, regs.p.x, regs.x.w),
-sty_addr(0x8c, regs.p.x, regs.y.w),
-stz_addr(0x9c, regs.p.m, 0x0000) {
-1:aa.l = op_readpc();
-2:aa.h = op_readpc();
-3:if($1)last_cycle();
-  op_writedbr(aa.w,     $2);
-  if($1)end;
-4:last_cycle();
-  op_writedbr(aa.w + 1, $2 >> 8);
-}
-
-sta_addrx(0x9d, regs.p.m, regs.a.w),
-stz_addrx(0x9e, regs.p.m, 0x0000) {
-1:aa.l = op_readpc();
-2:aa.h = op_readpc();
-3:cpu_io();
-4:if($1)last_cycle();
-  op_writedbr(aa.w + regs.x.w,     $2);
-  if($1)end;
-5:last_cycle();
-  op_writedbr(aa.w + regs.x.w + 1, $2 >> 8);
-}
-
-sta_addry(0x99) {
-1:aa.l = op_readpc();
-2:aa.h = op_readpc();
-3:cpu_io();
-4:if(regs.p.m)last_cycle();
-  op_writedbr(aa.w + regs.y.w,     regs.a.l);
-  if(regs.p.m)end;
-5:last_cycle();
-  op_writedbr(aa.w + regs.y.w + 1, regs.a.h);
-}
-
-sta_long(0x8f) {
-1:aa.l = op_readpc();
-2:aa.h = op_readpc();
-3:aa.b = op_readpc();
-4:if(regs.p.m)last_cycle();
-  op_writelong(aa.d,     regs.a.l);
-  if(regs.p.m)end;
-5:last_cycle();
-  op_writelong(aa.d + 1, regs.a.h);
-}
-
-sta_longx(0x9f) {
-1:aa.l = op_readpc();
-2:aa.h = op_readpc();
-3:aa.b = op_readpc();
-4:if(regs.p.m)last_cycle();
-  op_writelong(aa.d + regs.x.w,     regs.a.l);
-  if(regs.p.m)end;
-5:last_cycle();
-  op_writelong(aa.d + regs.x.w + 1, regs.a.h);
-}
-
-sta_dp(0x85, regs.p.m, regs.a.w),
-stx_dp(0x86, regs.p.x, regs.x.w),
-sty_dp(0x84, regs.p.x, regs.y.w),
-stz_dp(0x64, regs.p.m, 0x0000) {
-1:dp = op_readpc();
-2:cpu_c2();
-3:if($1)last_cycle();
-  op_writedp(dp,     $2);
-  if($1)end;
-4:last_cycle();
-  op_writedp(dp + 1, $2 >> 8);
-}
-
-sta_dpx(0x95, regs.p.m, regs.a.w),
-sty_dpx(0x94, regs.p.x, regs.y.w),
-stz_dpx(0x74, regs.p.m, 0x0000) {
-1:dp = op_readpc();
-2:cpu_c2();
-3:cpu_io();
-4:if($1)last_cycle();
-  op_writedp(dp + regs.x.w,     $2);
-  if($1)end;
-5:last_cycle();
-  op_writedp(dp + regs.x.w + 1, $2 >> 8);
-}
-
-stx_dpy(0x96) {
-1:dp = op_readpc();
-2:cpu_c2();
-3:cpu_io();
-4:if(regs.p.x)last_cycle();
-  op_writedp(dp + regs.y.w,     regs.x.l);
-  if(regs.p.x)end;
-5:last_cycle();
-  op_writedp(dp + regs.y.w + 1, regs.x.h);
-}
-
-sta_idp(0x92) {
-1:dp = op_readpc();
-2:cpu_c2();
-3:aa.l = op_readdp(dp);
-4:aa.h = op_readdp(dp + 1);
-5:if(regs.p.m)last_cycle();
-  op_writedbr(aa.w,     regs.a.l);
-  if(regs.p.m)end;
-6:last_cycle();
-  op_writedbr(aa.w + 1, regs.a.h);
-}
-
-sta_ildp(0x87) {
-1:dp = op_readpc();
-2:cpu_c2();
-3:aa.l = op_readdp(dp);
-4:aa.h = op_readdp(dp + 1);
-5:aa.b = op_readdp(dp + 2);
-6:if(regs.p.m)last_cycle();
-  op_writelong(aa.d,     regs.a.l);
-  if(regs.p.m)end;
-7:last_cycle();
-  op_writelong(aa.d + 1, regs.a.h);
-}
-
-sta_idpx(0x81) {
-1:dp = op_readpc();
-2:cpu_c2();
-3:cpu_io();
-4:aa.l = op_readdp(dp + regs.x.w);
-5:aa.h = op_readdp(dp + regs.x.w + 1);
-6:if(regs.p.m)last_cycle();
-  op_writedbr(aa.w,     regs.a.l);
-  if(regs.p.m)end;
-7:last_cycle();
-  op_writedbr(aa.w + 1, regs.a.h);
-}
-
-sta_idpy(0x91) {
-1:dp = op_readpc();
-2:cpu_c2();
-3:aa.l = op_readdp(dp);
-4:aa.h = op_readdp(dp + 1);
-5:cpu_io();
-6:if(regs.p.m)last_cycle();
-  op_writedbr(aa.w + regs.y.w,     regs.a.l);
-  if(regs.p.m)end;
-7:last_cycle();
-  op_writedbr(aa.w + regs.y.w + 1, regs.a.h);
-}
-
-sta_ildpy(0x97) {
-1:dp = op_readpc();
-2:cpu_c2();
-3:aa.l = op_readdp(dp);
-4:aa.h = op_readdp(dp + 1);
-5:aa.b = op_readdp(dp + 2);
-6:if(regs.p.m)last_cycle();
-  op_writelong(aa.d + regs.y.w,     regs.a.l);
-  if(regs.p.m)end;
-7:last_cycle();
-  op_writelong(aa.d + regs.y.w + 1, regs.a.h);
-}
-
-sta_sr(0x83) {
-1:sp = op_readpc();
-2:cpu_io();
-3:if(regs.p.m)last_cycle();
-  op_writesp(sp,     regs.a.l);
-  if(regs.p.m)end;
-4:last_cycle();
-  op_writesp(sp + 1, regs.a.h);
-}
-
-sta_isry(0x93) {
-1:sp = op_readpc();
-2:cpu_io();
-3:aa.l = op_readsp(sp);
-4:aa.h = op_readsp(sp + 1);
-5:cpu_io();
-6:if(regs.p.m)last_cycle();
-  op_writedbr(aa.w + regs.y.w,     regs.a.l);
-  if(regs.p.m)end;
-7:last_cycle();
-  op_writedbr(aa.w + regs.y.w + 1, regs.a.h);
-}
@@ -1,582 +0,0 @@
-void bCPU::op_sta_addr() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    aa.l = op_readpc();
-    } break;
-  case 2: {
-    aa.h = op_readpc();
-    } break;
-  case 3: {
-    if(regs.p.m)last_cycle();
-    op_writedbr(aa.w,     regs.a.w);
-    if(regs.p.m)status.cycle_pos = 0;
-    } break;
-  case 4: {
-    last_cycle();
-    op_writedbr(aa.w + 1, regs.a.w >> 8);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_stx_addr() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    aa.l = op_readpc();
-    } break;
-  case 2: {
-    aa.h = op_readpc();
-    } break;
-  case 3: {
-    if(regs.p.x)last_cycle();
-    op_writedbr(aa.w,     regs.x.w);
-    if(regs.p.x)status.cycle_pos = 0;
-    } break;
-  case 4: {
-    last_cycle();
-    op_writedbr(aa.w + 1, regs.x.w >> 8);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_sty_addr() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    aa.l = op_readpc();
-    } break;
-  case 2: {
-    aa.h = op_readpc();
-    } break;
-  case 3: {
-    if(regs.p.x)last_cycle();
-    op_writedbr(aa.w,     regs.y.w);
-    if(regs.p.x)status.cycle_pos = 0;
-    } break;
-  case 4: {
-    last_cycle();
-    op_writedbr(aa.w + 1, regs.y.w >> 8);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_stz_addr() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    aa.l = op_readpc();
-    } break;
-  case 2: {
-    aa.h = op_readpc();
-    } break;
-  case 3: {
-    if(regs.p.m)last_cycle();
-    op_writedbr(aa.w,     0x0000);
-    if(regs.p.m)status.cycle_pos = 0;
-    } break;
-  case 4: {
-    last_cycle();
-    op_writedbr(aa.w + 1, 0x0000 >> 8);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_sta_addrx() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    aa.l = op_readpc();
-    } break;
-  case 2: {
-    aa.h = op_readpc();
-    } break;
-  case 3: {
-    cpu_c4(aa.w, aa.w + regs.x.w);
-    } break;
-  case 4: {
-    if(regs.p.m)last_cycle();
-    op_writedbr(aa.w + regs.x.w,     regs.a.w);
-    if(regs.p.m)status.cycle_pos = 0;
-    } break;
-  case 5: {
-    last_cycle();
-    op_writedbr(aa.w + regs.x.w + 1, regs.a.w >> 8);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_stz_addrx() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    aa.l = op_readpc();
-    } break;
-  case 2: {
-    aa.h = op_readpc();
-    } break;
-  case 3: {
-    cpu_c4(aa.w, aa.w + regs.x.w);
-    } break;
-  case 4: {
-    if(regs.p.m)last_cycle();
-    op_writedbr(aa.w + regs.x.w,     0x0000);
-    if(regs.p.m)status.cycle_pos = 0;
-    } break;
-  case 5: {
-    last_cycle();
-    op_writedbr(aa.w + regs.x.w + 1, 0x0000 >> 8);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_sta_addry() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    aa.l = op_readpc();
-    } break;
-  case 2: {
-    aa.h = op_readpc();
-    } break;
-  case 3: {
-    cpu_c4(aa.w, aa.w + regs.y.w);
-    } break;
-  case 4: {
-    if(regs.p.m)last_cycle();
-    op_writedbr(aa.w + regs.y.w,     regs.a.l);
-    if(regs.p.m)status.cycle_pos = 0;
-    } break;
-  case 5: {
-    last_cycle();
-    op_writedbr(aa.w + regs.y.w + 1, regs.a.h);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_sta_long() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    aa.l = op_readpc();
-    } break;
-  case 2: {
-    aa.h = op_readpc();
-    } break;
-  case 3: {
-    aa.b = op_readpc();
-    } break;
-  case 4: {
-    if(regs.p.m)last_cycle();
-    op_writelong(aa.d,     regs.a.l);
-    if(regs.p.m)status.cycle_pos = 0;
-    } break;
-  case 5: {
-    last_cycle();
-    op_writelong(aa.d + 1, regs.a.h);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_sta_longx() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    aa.l = op_readpc();
-    } break;
-  case 2: {
-    aa.h = op_readpc();
-    } break;
-  case 3: {
-    aa.b = op_readpc();
-    } break;
-  case 4: {
-    if(regs.p.m)last_cycle();
-    op_writelong(aa.d + regs.x.w,     regs.a.l);
-    if(regs.p.m)status.cycle_pos = 0;
-    } break;
-  case 5: {
-    last_cycle();
-    op_writelong(aa.d + regs.x.w + 1, regs.a.h);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_sta_dp() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp = op_readpc();
-    } break;
-  case 2: {
-    cpu_c2();
-    } break;
-  case 3: {
-    if(regs.p.m)last_cycle();
-    op_writedp(dp,     regs.a.w);
-    if(regs.p.m)status.cycle_pos = 0;
-    } break;
-  case 4: {
-    last_cycle();
-    op_writedp(dp + 1, regs.a.w >> 8);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_stx_dp() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp = op_readpc();
-    } break;
-  case 2: {
-    cpu_c2();
-    } break;
-  case 3: {
-    if(regs.p.x)last_cycle();
-    op_writedp(dp,     regs.x.w);
-    if(regs.p.x)status.cycle_pos = 0;
-    } break;
-  case 4: {
-    last_cycle();
-    op_writedp(dp + 1, regs.x.w >> 8);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_sty_dp() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp = op_readpc();
-    } break;
-  case 2: {
-    cpu_c2();
-    } break;
-  case 3: {
-    if(regs.p.x)last_cycle();
-    op_writedp(dp,     regs.y.w);
-    if(regs.p.x)status.cycle_pos = 0;
-    } break;
-  case 4: {
-    last_cycle();
-    op_writedp(dp + 1, regs.y.w >> 8);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_stz_dp() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp = op_readpc();
-    } break;
-  case 2: {
-    cpu_c2();
-    } break;
-  case 3: {
-    if(regs.p.m)last_cycle();
-    op_writedp(dp,     0x0000);
-    if(regs.p.m)status.cycle_pos = 0;
-    } break;
-  case 4: {
-    last_cycle();
-    op_writedp(dp + 1, 0x0000 >> 8);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_sta_dpx() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp = op_readpc();
-    } break;
-  case 2: {
-    cpu_c2();
-    } break;
-  case 3: {
-    cpu_io();
-    } break;
-  case 4: {
-    if(regs.p.m)last_cycle();
-    op_writedp(dp + regs.x.w,     regs.a.w);
-    if(regs.p.m)status.cycle_pos = 0;
-    } break;
-  case 5: {
-    last_cycle();
-    op_writedp(dp + regs.x.w + 1, regs.a.w >> 8);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_sty_dpx() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp = op_readpc();
-    } break;
-  case 2: {
-    cpu_c2();
-    } break;
-  case 3: {
-    cpu_io();
-    } break;
-  case 4: {
-    if(regs.p.x)last_cycle();
-    op_writedp(dp + regs.x.w,     regs.y.w);
-    if(regs.p.x)status.cycle_pos = 0;
-    } break;
-  case 5: {
-    last_cycle();
-    op_writedp(dp + regs.x.w + 1, regs.y.w >> 8);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_stz_dpx() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp = op_readpc();
-    } break;
-  case 2: {
-    cpu_c2();
-    } break;
-  case 3: {
-    cpu_io();
-    } break;
-  case 4: {
-    if(regs.p.m)last_cycle();
-    op_writedp(dp + regs.x.w,     0x0000);
-    if(regs.p.m)status.cycle_pos = 0;
-    } break;
-  case 5: {
-    last_cycle();
-    op_writedp(dp + regs.x.w + 1, 0x0000 >> 8);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_stx_dpy() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp = op_readpc();
-    } break;
-  case 2: {
-    cpu_c2();
-    } break;
-  case 3: {
-    cpu_io();
-    } break;
-  case 4: {
-    if(regs.p.x)last_cycle();
-    op_writedp(dp + regs.y.w,     regs.x.l);
-    if(regs.p.x)status.cycle_pos = 0;
-    } break;
-  case 5: {
-    last_cycle();
-    op_writedp(dp + regs.y.w + 1, regs.x.h);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_sta_idp() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp = op_readpc();
-    } break;
-  case 2: {
-    cpu_c2();
-    } break;
-  case 3: {
-    aa.l = op_readdp(dp);
-    } break;
-  case 4: {
-    aa.h = op_readdp(dp + 1);
-    } break;
-  case 5: {
-    if(regs.p.m)last_cycle();
-    op_writedbr(aa.w,     regs.a.l);
-    if(regs.p.m)status.cycle_pos = 0;
-    } break;
-  case 6: {
-    last_cycle();
-    op_writedbr(aa.w + 1, regs.a.h);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_sta_ildp() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp = op_readpc();
-    } break;
-  case 2: {
-    cpu_c2();
-    } break;
-  case 3: {
-    aa.l = op_readdp(dp);
-    } break;
-  case 4: {
-    aa.h = op_readdp(dp + 1);
-    } break;
-  case 5: {
-    aa.b = op_readdp(dp + 2);
-    } break;
-  case 6: {
-    if(regs.p.m)last_cycle();
-    op_writelong(aa.d,     regs.a.l);
-    if(regs.p.m)status.cycle_pos = 0;
-    } break;
-  case 7: {
-    last_cycle();
-    op_writelong(aa.d + 1, regs.a.h);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_sta_idpx() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp = op_readpc();
-    } break;
-  case 2: {
-    cpu_c2();
-    } break;
-  case 3: {
-    cpu_io();
-    } break;
-  case 4: {
-    aa.l = op_readdp(dp + regs.x.w);
-    } break;
-  case 5: {
-    aa.h = op_readdp(dp + regs.x.w + 1);
-    } break;
-  case 6: {
-    if(regs.p.m)last_cycle();
-    op_writedbr(aa.w,     regs.a.l);
-    if(regs.p.m)status.cycle_pos = 0;
-    } break;
-  case 7: {
-    last_cycle();
-    op_writedbr(aa.w + 1, regs.a.h);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_sta_idpy() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp = op_readpc();
-    } break;
-  case 2: {
-    cpu_c2();
-    } break;
-  case 3: {
-    aa.l = op_readdp(dp);
-    } break;
-  case 4: {
-    aa.h = op_readdp(dp + 1);
-    } break;
-  case 5: {
-    cpu_c4(aa.w, aa.w + regs.y.w);
-    } break;
-  case 6: {
-    if(regs.p.m)last_cycle();
-    op_writedbr(aa.w + regs.y.w,     regs.a.l);
-    if(regs.p.m)status.cycle_pos = 0;
-    } break;
-  case 7: {
-    last_cycle();
-    op_writedbr(aa.w + regs.y.w + 1, regs.a.h);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_sta_ildpy() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    dp = op_readpc();
-    } break;
-  case 2: {
-    cpu_c2();
-    } break;
-  case 3: {
-    aa.l = op_readdp(dp);
-    } break;
-  case 4: {
-    aa.h = op_readdp(dp + 1);
-    } break;
-  case 5: {
-    aa.b = op_readdp(dp + 2);
-    } break;
-  case 6: {
-    if(regs.p.m)last_cycle();
-    op_writelong(aa.d + regs.y.w,     regs.a.l);
-    if(regs.p.m)status.cycle_pos = 0;
-    } break;
-  case 7: {
-    last_cycle();
-    op_writelong(aa.d + regs.y.w + 1, regs.a.h);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_sta_sr() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    sp = op_readpc();
-    } break;
-  case 2: {
-    cpu_io();
-    } break;
-  case 3: {
-    if(regs.p.m)last_cycle();
-    op_writesp(sp,     regs.a.l);
-    if(regs.p.m)status.cycle_pos = 0;
-    } break;
-  case 4: {
-    last_cycle();
-    op_writesp(sp + 1, regs.a.h);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
-void bCPU::op_sta_isry() {
-  switch(status.cycle_pos++) {
-  case 1: {
-    sp = op_readpc();
-    } break;
-  case 2: {
-    cpu_io();
-    } break;
-  case 3: {
-    aa.l = op_readsp(sp);
-    } break;
-  case 4: {
-    aa.h = op_readsp(sp + 1);
-    } break;
-  case 5: {
-    cpu_io();
-    } break;
-  case 6: {
-    if(regs.p.m)last_cycle();
-    op_writedbr(aa.w + regs.y.w,     regs.a.l);
-    if(regs.p.m)status.cycle_pos = 0;
-    } break;
-  case 7: {
-    last_cycle();
-    op_writedbr(aa.w + regs.y.w + 1, regs.a.h);
-    status.cycle_pos = 0;
-    } break;
-  }
-}
-
@@ -1,377 +0,0 @@
-//op_read
-inline void bCPU::op_adc_b() {
-int32 r = regs.a.l + rd.l + regs.p.c;
-  if(regs.p.d) {
-  uint8 n0 = (regs.a.l     ) & 15;
-  uint8 n1 = (regs.a.l >> 4) & 15;
-    n0 += ((rd.l) & 15) + regs.p.c;
-    if(n0 > 9) {
-      n0 -= 10;
-      n0 &= 15;
-      n1++;
-    }
-    n1 += ((rd.l >> 4) & 15);
-    if(n1 > 9) {
-      n1 -= 10;
-      n1 &= 15;
-      regs.p.c = 1;
-    } else {
-      regs.p.c = 0;
-    }
-    r = (n1 << 4) | (n0);
-  } else {
-    r = regs.a.l + rd.l + regs.p.c;
-    regs.p.c = (r > 0xff);
-  }
-  regs.p.n = !!(r & 0x80);
-  regs.p.v = !!(~(regs.a.l ^ rd.l) & (regs.a.l ^ r) & 0x80);
-  regs.p.z = ((uint8)r == 0);
-  regs.a.l = r;
-}
-
-inline void bCPU::op_adc_w() {
-int32 r;
-  if(regs.p.d) {
-  uint8 n0 = (regs.a.w      ) & 15;
-  uint8 n1 = (regs.a.w >>  4) & 15;
-  uint8 n2 = (regs.a.w >>  8) & 15;
-  uint8 n3 = (regs.a.w >> 12) & 15;
-    n0 += ((rd.w) & 15) + regs.p.c;
-    if(n0 > 9) {
-      n0 -= 10;
-      n0 &= 15;
-      n1++;
-    }
-    n1 += ((rd.w >> 4) & 15);
-    if(n1 > 9) {
-      n1 -= 10;
-      n1 &= 15;
-      n2++;
-    }
-    n2 += ((rd.w >> 8) & 15);
-    if(n2 > 9) {
-      n2 -= 10;
-      n2 &= 15;
-      n3++;
-    }
-    n3 += ((rd.w >> 12) & 15);
-    if(n3 > 9) {
-      n3 -= 10;
-      n3 &= 15;
-      regs.p.c = 1;
-    } else {
-      regs.p.c = 0;
-    }
-    r = (n3 << 12) | (n2 << 8) | (n1 << 4) | (n0);
-  } else {
-    r = regs.a.w + rd.w + regs.p.c;
-    regs.p.c = (r > 0xffff);
-  }
-  regs.p.n = !!(r & 0x8000);
-  regs.p.v = !!(~(regs.a.w ^ rd.w) & (regs.a.w ^ r) & 0x8000);
-  regs.p.z = ((uint16)r == 0);
-  regs.a.w = r;
-}
-
-inline void bCPU::op_and_b() {
-  regs.a.l &= rd.l;
-  regs.p.n = !!(regs.a.l & 0x80);
-  regs.p.z = (regs.a.l == 0);
-}
-
-inline void bCPU::op_and_w() {
-  regs.a.w &= rd.w;
-  regs.p.n = !!(regs.a.w & 0x8000);
-  regs.p.z = (regs.a.w == 0);
-}
-
-inline void bCPU::op_bit_b() {
-  regs.p.n = !!(rd.l & 0x80);
-  regs.p.v = !!(rd.l & 0x40);
-  regs.p.z = ((rd.l & regs.a.l) == 0);
-}
-
-inline void bCPU::op_bit_w() {
-  regs.p.n = !!(rd.w & 0x8000);
-  regs.p.v = !!(rd.w & 0x4000);
-  regs.p.z = ((rd.w & regs.a.w) == 0);
-}
-
-inline void bCPU::op_cmp_b() {
-int32 r = regs.a.l - rd.l;
-  regs.p.n = !!(r & 0x80);
-  regs.p.z = ((uint8)r == 0);
-  regs.p.c = (r >= 0);
-}
-
-inline void bCPU::op_cmp_w() {
-int32 r = regs.a.w - rd.w;
-  regs.p.n = !!(r & 0x8000);
-  regs.p.z = ((uint16)r == 0);
-  regs.p.c = (r >= 0);
-}
-
-inline void bCPU::op_cpx_b() {
-int32 r = regs.x.l - rd.l;
-  regs.p.n = !!(r & 0x80);
-  regs.p.z = ((uint8)r == 0);
-  regs.p.c = (r >= 0);
-}
-
-inline void bCPU::op_cpx_w() {
-int32 r = regs.x.w - rd.w;
-  regs.p.n = !!(r & 0x8000);
-  regs.p.z = ((uint16)r == 0);
-  regs.p.c = (r >= 0);
-}
-
-inline void bCPU::op_cpy_b() {
-int32 r = regs.y.l - rd.l;
-  regs.p.n = !!(r & 0x80);
-  regs.p.z = ((uint8)r == 0);
-  regs.p.c = (r >= 0);
-}
-
-inline void bCPU::op_cpy_w() {
-int32 r = regs.y.w - rd.w;
-  regs.p.n = !!(r & 0x8000);
-  regs.p.z = ((uint16)r == 0);
-  regs.p.c = (r >= 0);
-}
-
-inline void bCPU::op_eor_b() {
-  regs.a.l ^= rd.l;
-  regs.p.n = !!(regs.a.l & 0x80);
-  regs.p.z = (regs.a.l == 0);
-}
-
-inline void bCPU::op_eor_w() {
-  regs.a.w ^= rd.w;
-  regs.p.n = !!(regs.a.w & 0x8000);
-  regs.p.z = (regs.a.w == 0);
-}
-
-inline void bCPU::op_lda_b() {
-  regs.a.l = rd.l;
-  regs.p.n = !!(regs.a.l & 0x80);
-  regs.p.z = (regs.a.l == 0);
-}
-
-inline void bCPU::op_lda_w() {
-  regs.a.w = rd.w;
-  regs.p.n = !!(regs.a.w & 0x8000);
-  regs.p.z = (regs.a.w == 0);
-}
-
-inline void bCPU::op_ldx_b() {
-  regs.x.l = rd.l;
-  regs.p.n = !!(regs.x.l & 0x80);
-  regs.p.z = (regs.x.l == 0);
-}
-
-inline void bCPU::op_ldx_w() {
-  regs.x.w = rd.w;
-  regs.p.n = !!(regs.x.w & 0x8000);
-  regs.p.z = (regs.x.w == 0);
-}
-
-inline void bCPU::op_ldy_b() {
-  regs.y.l = rd.l;
-  regs.p.n = !!(regs.y.l & 0x80);
-  regs.p.z = (regs.y.l == 0);
-}
-
-inline void bCPU::op_ldy_w() {
-  regs.y.w = rd.w;
-  regs.p.n = !!(regs.y.w & 0x8000);
-  regs.p.z = (regs.y.w == 0);
-}
-
-inline void bCPU::op_ora_b() {
-  regs.a.l |= rd.l;
-  regs.p.n = !!(regs.a.l & 0x80);
-  regs.p.z = (regs.a.l == 0);
-}
-
-inline void bCPU::op_ora_w() {
-  regs.a.w |= rd.w;
-  regs.p.n = !!(regs.a.w & 0x8000);
-  regs.p.z = (regs.a.w == 0);
-}
-
-inline void bCPU::op_sbc_b() {
-int32 r;
-  if(regs.p.d) {
-  uint8 n0 = (regs.a.l     ) & 15;
-  uint8 n1 = (regs.a.l >> 4) & 15;
-    n0 -= ((rd.l     ) & 15) + !regs.p.c;
-    n1 -= ((rd.l >> 4) & 15);
-    if(n0 > 9) {
-      n0 += 10;
-      n1--;
-    }
-    if(n1 > 9) {
-      n1 += 10;
-      regs.p.c = 0;
-    } else {
-      regs.p.c = 1;
-    }
-    r = (n1 << 4) | (n0);
-  } else {
-    r = regs.a.l - rd.l - !regs.p.c;
-    regs.p.c = (r >= 0);
-  }
-  regs.p.n = !!(r & 0x80);
-  regs.p.v = !!((regs.a.l ^ rd.l) & (regs.a.l ^ r) & 0x80);
-  regs.p.z = ((uint8)r == 0);
-  regs.a.l = r;
-}
-
-inline void bCPU::op_sbc_w() {
-int32 r;
-  if(regs.p.d) {
-  uint8 n0 = (regs.a.w      ) & 15;
-  uint8 n1 = (regs.a.w >>  4) & 15;
-  uint8 n2 = (regs.a.w >>  8) & 15;
-  uint8 n3 = (regs.a.w >> 12) & 15;
-    n0 -= ((rd.w      ) & 15) + !regs.p.c;
-    n1 -= ((rd.w >>  4) & 15);
-    n2 -= ((rd.w >>  8) & 15);
-    n3 -= ((rd.w >> 12) & 15);
-    if(n0 > 9) {
-      n0 += 10;
-      n1--;
-    }
-    if(n1 > 9) {
-      n1 += 10;
-      n2--;
-    }
-    if(n2 > 9) {
-      n2 += 10;
-      n3--;
-    }
-    if(n3 > 9) {
-      n3 += 10;
-      regs.p.c = 0;
-    } else {
-      regs.p.c = 1;
-    }
-    r = (n3 << 12) | (n2 << 8) | (n1 << 4) | (n0);
-  } else {
-    r = regs.a.w - rd.w - !regs.p.c;
-    regs.p.c = (r >= 0);
-  }
-  regs.p.n = !!(r & 0x8000);
-  regs.p.v = !!((regs.a.w ^ rd.w) & (regs.a.w ^ r) & 0x8000);
-  regs.p.z = ((uint16)r == 0);
-  regs.a.w = r;
-}
-
-//op_rmw
-inline void bCPU::op_inc_b() {
-  rd.l++;
-  regs.p.n = !!(rd.l & 0x80);
-  regs.p.z = (rd.l == 0);
-}
-
-inline void bCPU::op_inc_w() {
-  rd.w++;
-  regs.p.n = !!(rd.w & 0x8000);
-  regs.p.z = (rd.w == 0);
-}
-
-inline void bCPU::op_dec_b() {
-  rd.l--;
-  regs.p.n = !!(rd.l & 0x80);
-  regs.p.z = (rd.l == 0);
-}
-
-inline void bCPU::op_dec_w() {
-  rd.w--;
-  regs.p.n = !!(rd.w & 0x8000);
-  regs.p.z = (rd.w == 0);
-}
-
-inline void bCPU::op_asl_b() {
-  regs.p.c = !!(rd.l & 0x80);
-  rd.l <<= 1;
-  regs.p.n = !!(rd.l & 0x80);
-  regs.p.z = (rd.l == 0);
-}
-
-inline void bCPU::op_asl_w() {
-  regs.p.c = !!(rd.w & 0x8000);
-  rd.w <<= 1;
-  regs.p.n = !!(rd.w & 0x8000);
-  regs.p.z = (rd.w == 0);
-}
-
-inline void bCPU::op_lsr_b() {
-  regs.p.c = rd.l & 1;
-  rd.l >>= 1;
-  regs.p.n = !!(rd.l & 0x80);
-  regs.p.z = (rd.l == 0);
-}
-
-inline void bCPU::op_lsr_w() {
-  regs.p.c = rd.w & 1;
-  rd.w >>= 1;
-  regs.p.n = !!(rd.w & 0x8000);
-  regs.p.z = (rd.w == 0);
-}
-
-inline void bCPU::op_rol_b() {
-uint16 c = regs.p.c;
-  regs.p.c = !!(rd.l & 0x80);
-  rd.l <<= 1;
-  rd.l |= c;
-  regs.p.n = !!(rd.l & 0x80);
-  regs.p.z = (rd.l == 0);
-}
-
-inline void bCPU::op_rol_w() {
-uint16 c = regs.p.c;
-  regs.p.c = !!(rd.w & 0x8000);
-  rd.w <<= 1;
-  rd.w |= c;
-  regs.p.n = !!(rd.w & 0x8000);
-  regs.p.z = (rd.w == 0);
-}
-
-inline void bCPU::op_ror_b() {
-uint16 c = (regs.p.c)?0x80:0;
-  regs.p.c = rd.l & 1;
-  rd.l >>= 1;
-  rd.l |= c;
-  regs.p.n = !!(rd.l & 0x80);
-  regs.p.z = (rd.l == 0);
-}
-
-inline void bCPU::op_ror_w() {
-uint16 c = (regs.p.c)?0x8000:0;
-  regs.p.c = rd.w & 1;
-  rd.w >>= 1;
-  rd.w |= c;
-  regs.p.n = !!(rd.w & 0x8000);
-  regs.p.z = (rd.w == 0);
-}
-
-inline void bCPU::op_trb_b() {
-  regs.p.z = ((rd.l & regs.a.l) == 0);
-  rd.l &= ~regs.a.l;
-}
-
-inline void bCPU::op_trb_w() {
-  regs.p.z = ((rd.w & regs.a.w) == 0);
-  rd.w &= ~regs.a.w;
-}
-
-inline void bCPU::op_tsb_b() {
-  regs.p.z = ((rd.l & regs.a.l) == 0);
-  rd.l |= regs.a.l;
-}
-
-inline void bCPU::op_tsb_w() {
-  regs.p.z = ((rd.w & regs.a.w) == 0);
-  rd.w |= regs.a.w;
-}
@@ -1,256 +0,0 @@
-optbl[0x69] = &bCPU::op_adc_const;
-optbl[0x29] = &bCPU::op_and_const;
-optbl[0xc9] = &bCPU::op_cmp_const;
-optbl[0xe0] = &bCPU::op_cpx_const;
-optbl[0xc0] = &bCPU::op_cpy_const;
-optbl[0x49] = &bCPU::op_eor_const;
-optbl[0xa9] = &bCPU::op_lda_const;
-optbl[0xa2] = &bCPU::op_ldx_const;
-optbl[0xa0] = &bCPU::op_ldy_const;
-optbl[0x09] = &bCPU::op_ora_const;
-optbl[0xe9] = &bCPU::op_sbc_const;
-optbl[0x6d] = &bCPU::op_adc_addr;
-optbl[0x2d] = &bCPU::op_and_addr;
-optbl[0x2c] = &bCPU::op_bit_addr;
-optbl[0xcd] = &bCPU::op_cmp_addr;
-optbl[0xec] = &bCPU::op_cpx_addr;
-optbl[0xcc] = &bCPU::op_cpy_addr;
-optbl[0x4d] = &bCPU::op_eor_addr;
-optbl[0xad] = &bCPU::op_lda_addr;
-optbl[0xae] = &bCPU::op_ldx_addr;
-optbl[0xac] = &bCPU::op_ldy_addr;
-optbl[0x0d] = &bCPU::op_ora_addr;
-optbl[0xed] = &bCPU::op_sbc_addr;
-optbl[0x7d] = &bCPU::op_adc_addrx;
-optbl[0x3d] = &bCPU::op_and_addrx;
-optbl[0x3c] = &bCPU::op_bit_addrx;
-optbl[0xdd] = &bCPU::op_cmp_addrx;
-optbl[0x5d] = &bCPU::op_eor_addrx;
-optbl[0xbd] = &bCPU::op_lda_addrx;
-optbl[0xbc] = &bCPU::op_ldy_addrx;
-optbl[0x1d] = &bCPU::op_ora_addrx;
-optbl[0xfd] = &bCPU::op_sbc_addrx;
-optbl[0x79] = &bCPU::op_adc_addry;
-optbl[0x39] = &bCPU::op_and_addry;
-optbl[0xd9] = &bCPU::op_cmp_addry;
-optbl[0x59] = &bCPU::op_eor_addry;
-optbl[0xb9] = &bCPU::op_lda_addry;
-optbl[0xbe] = &bCPU::op_ldx_addry;
-optbl[0x19] = &bCPU::op_ora_addry;
-optbl[0xf9] = &bCPU::op_sbc_addry;
-optbl[0x6f] = &bCPU::op_adc_long;
-optbl[0x2f] = &bCPU::op_and_long;
-optbl[0xcf] = &bCPU::op_cmp_long;
-optbl[0x4f] = &bCPU::op_eor_long;
-optbl[0xaf] = &bCPU::op_lda_long;
-optbl[0x0f] = &bCPU::op_ora_long;
-optbl[0xef] = &bCPU::op_sbc_long;
-optbl[0x7f] = &bCPU::op_adc_longx;
-optbl[0x3f] = &bCPU::op_and_longx;
-optbl[0xdf] = &bCPU::op_cmp_longx;
-optbl[0x5f] = &bCPU::op_eor_longx;
-optbl[0xbf] = &bCPU::op_lda_longx;
-optbl[0x1f] = &bCPU::op_ora_longx;
-optbl[0xff] = &bCPU::op_sbc_longx;
-optbl[0x65] = &bCPU::op_adc_dp;
-optbl[0x25] = &bCPU::op_and_dp;
-optbl[0x24] = &bCPU::op_bit_dp;
-optbl[0xc5] = &bCPU::op_cmp_dp;
-optbl[0xe4] = &bCPU::op_cpx_dp;
-optbl[0xc4] = &bCPU::op_cpy_dp;
-optbl[0x45] = &bCPU::op_eor_dp;
-optbl[0xa5] = &bCPU::op_lda_dp;
-optbl[0xa6] = &bCPU::op_ldx_dp;
-optbl[0xa4] = &bCPU::op_ldy_dp;
-optbl[0x05] = &bCPU::op_ora_dp;
-optbl[0xe5] = &bCPU::op_sbc_dp;
-optbl[0x75] = &bCPU::op_adc_dpx;
-optbl[0x35] = &bCPU::op_and_dpx;
-optbl[0x34] = &bCPU::op_bit_dpx;
-optbl[0xd5] = &bCPU::op_cmp_dpx;
-optbl[0x55] = &bCPU::op_eor_dpx;
-optbl[0xb5] = &bCPU::op_lda_dpx;
-optbl[0xb4] = &bCPU::op_ldy_dpx;
-optbl[0x15] = &bCPU::op_ora_dpx;
-optbl[0xf5] = &bCPU::op_sbc_dpx;
-optbl[0xb6] = &bCPU::op_ldx_dpy;
-optbl[0x72] = &bCPU::op_adc_idp;
-optbl[0x32] = &bCPU::op_and_idp;
-optbl[0xd2] = &bCPU::op_cmp_idp;
-optbl[0x52] = &bCPU::op_eor_idp;
-optbl[0xb2] = &bCPU::op_lda_idp;
-optbl[0x12] = &bCPU::op_ora_idp;
-optbl[0xf2] = &bCPU::op_sbc_idp;
-optbl[0x61] = &bCPU::op_adc_idpx;
-optbl[0x21] = &bCPU::op_and_idpx;
-optbl[0xc1] = &bCPU::op_cmp_idpx;
-optbl[0x41] = &bCPU::op_eor_idpx;
-optbl[0xa1] = &bCPU::op_lda_idpx;
-optbl[0x01] = &bCPU::op_ora_idpx;
-optbl[0xe1] = &bCPU::op_sbc_idpx;
-optbl[0x71] = &bCPU::op_adc_idpy;
-optbl[0x31] = &bCPU::op_and_idpy;
-optbl[0xd1] = &bCPU::op_cmp_idpy;
-optbl[0x51] = &bCPU::op_eor_idpy;
-optbl[0xb1] = &bCPU::op_lda_idpy;
-optbl[0x11] = &bCPU::op_ora_idpy;
-optbl[0xf1] = &bCPU::op_sbc_idpy;
-optbl[0x67] = &bCPU::op_adc_ildp;
-optbl[0x27] = &bCPU::op_and_ildp;
-optbl[0xc7] = &bCPU::op_cmp_ildp;
-optbl[0x47] = &bCPU::op_eor_ildp;
-optbl[0xa7] = &bCPU::op_lda_ildp;
-optbl[0x07] = &bCPU::op_ora_ildp;
-optbl[0xe7] = &bCPU::op_sbc_ildp;
-optbl[0x77] = &bCPU::op_adc_ildpy;
-optbl[0x37] = &bCPU::op_and_ildpy;
-optbl[0xd7] = &bCPU::op_cmp_ildpy;
-optbl[0x57] = &bCPU::op_eor_ildpy;
-optbl[0xb7] = &bCPU::op_lda_ildpy;
-optbl[0x17] = &bCPU::op_ora_ildpy;
-optbl[0xf7] = &bCPU::op_sbc_ildpy;
-optbl[0x63] = &bCPU::op_adc_sr;
-optbl[0x23] = &bCPU::op_and_sr;
-optbl[0xc3] = &bCPU::op_cmp_sr;
-optbl[0x43] = &bCPU::op_eor_sr;
-optbl[0xa3] = &bCPU::op_lda_sr;
-optbl[0x03] = &bCPU::op_ora_sr;
-optbl[0xe3] = &bCPU::op_sbc_sr;
-optbl[0x73] = &bCPU::op_adc_isry;
-optbl[0x33] = &bCPU::op_and_isry;
-optbl[0xd3] = &bCPU::op_cmp_isry;
-optbl[0x53] = &bCPU::op_eor_isry;
-optbl[0xb3] = &bCPU::op_lda_isry;
-optbl[0x13] = &bCPU::op_ora_isry;
-optbl[0xf3] = &bCPU::op_sbc_isry;
-optbl[0x89] = &bCPU::op_bit_const;
-optbl[0x1a] = &bCPU::op_inc;
-optbl[0xe8] = &bCPU::op_inx;
-optbl[0xc8] = &bCPU::op_iny;
-optbl[0x3a] = &bCPU::op_dec;
-optbl[0xca] = &bCPU::op_dex;
-optbl[0x88] = &bCPU::op_dey;
-optbl[0x0a] = &bCPU::op_asl;
-optbl[0x4a] = &bCPU::op_lsr;
-optbl[0x2a] = &bCPU::op_rol;
-optbl[0x6a] = &bCPU::op_ror;
-optbl[0xee] = &bCPU::op_inc_addr;
-optbl[0xce] = &bCPU::op_dec_addr;
-optbl[0x0e] = &bCPU::op_asl_addr;
-optbl[0x4e] = &bCPU::op_lsr_addr;
-optbl[0x2e] = &bCPU::op_rol_addr;
-optbl[0x6e] = &bCPU::op_ror_addr;
-optbl[0x1c] = &bCPU::op_trb_addr;
-optbl[0x0c] = &bCPU::op_tsb_addr;
-optbl[0xfe] = &bCPU::op_inc_addrx;
-optbl[0xde] = &bCPU::op_dec_addrx;
-optbl[0x1e] = &bCPU::op_asl_addrx;
-optbl[0x5e] = &bCPU::op_lsr_addrx;
-optbl[0x3e] = &bCPU::op_rol_addrx;
-optbl[0x7e] = &bCPU::op_ror_addrx;
-optbl[0xe6] = &bCPU::op_inc_dp;
-optbl[0xc6] = &bCPU::op_dec_dp;
-optbl[0x06] = &bCPU::op_asl_dp;
-optbl[0x46] = &bCPU::op_lsr_dp;
-optbl[0x26] = &bCPU::op_rol_dp;
-optbl[0x66] = &bCPU::op_ror_dp;
-optbl[0x14] = &bCPU::op_trb_dp;
-optbl[0x04] = &bCPU::op_tsb_dp;
-optbl[0xf6] = &bCPU::op_inc_dpx;
-optbl[0xd6] = &bCPU::op_dec_dpx;
-optbl[0x16] = &bCPU::op_asl_dpx;
-optbl[0x56] = &bCPU::op_lsr_dpx;
-optbl[0x36] = &bCPU::op_rol_dpx;
-optbl[0x76] = &bCPU::op_ror_dpx;
-optbl[0x8d] = &bCPU::op_sta_addr;
-optbl[0x8e] = &bCPU::op_stx_addr;
-optbl[0x8c] = &bCPU::op_sty_addr;
-optbl[0x9c] = &bCPU::op_stz_addr;
-optbl[0x9d] = &bCPU::op_sta_addrx;
-optbl[0x9e] = &bCPU::op_stz_addrx;
-optbl[0x99] = &bCPU::op_sta_addry;
-optbl[0x8f] = &bCPU::op_sta_long;
-optbl[0x9f] = &bCPU::op_sta_longx;
-optbl[0x85] = &bCPU::op_sta_dp;
-optbl[0x86] = &bCPU::op_stx_dp;
-optbl[0x84] = &bCPU::op_sty_dp;
-optbl[0x64] = &bCPU::op_stz_dp;
-optbl[0x95] = &bCPU::op_sta_dpx;
-optbl[0x94] = &bCPU::op_sty_dpx;
-optbl[0x74] = &bCPU::op_stz_dpx;
-optbl[0x96] = &bCPU::op_stx_dpy;
-optbl[0x92] = &bCPU::op_sta_idp;
-optbl[0x87] = &bCPU::op_sta_ildp;
-optbl[0x81] = &bCPU::op_sta_idpx;
-optbl[0x91] = &bCPU::op_sta_idpy;
-optbl[0x97] = &bCPU::op_sta_ildpy;
-optbl[0x83] = &bCPU::op_sta_sr;
-optbl[0x93] = &bCPU::op_sta_isry;
-optbl[0x90] = &bCPU::op_bcc;
-optbl[0xb0] = &bCPU::op_bcs;
-optbl[0xd0] = &bCPU::op_bne;
-optbl[0xf0] = &bCPU::op_beq;
-optbl[0x10] = &bCPU::op_bpl;
-optbl[0x30] = &bCPU::op_bmi;
-optbl[0x50] = &bCPU::op_bvc;
-optbl[0x70] = &bCPU::op_bvs;
-optbl[0x80] = &bCPU::op_bra;
-optbl[0x82] = &bCPU::op_brl;
-optbl[0x4c] = &bCPU::op_jmp_addr;
-optbl[0x5c] = &bCPU::op_jmp_long;
-optbl[0x6c] = &bCPU::op_jmp_iaddr;
-optbl[0x7c] = &bCPU::op_jmp_iaddrx;
-optbl[0xdc] = &bCPU::op_jmp_iladdr;
-optbl[0x20] = &bCPU::op_jsr_addr;
-optbl[0x22] = &bCPU::op_jsr_long;
-optbl[0xfc] = &bCPU::op_jsr_iaddrx;
-optbl[0x40] = &bCPU::op_rti;
-optbl[0x60] = &bCPU::op_rts;
-optbl[0x6b] = &bCPU::op_rtl;
-optbl[0xea] = &bCPU::op_nop;
-optbl[0x42] = &bCPU::op_wdm;
-optbl[0xeb] = &bCPU::op_xba;
-optbl[0x54] = &bCPU::op_mvn;
-optbl[0x44] = &bCPU::op_mvp;
-optbl[0x00] = &bCPU::op_brk;
-optbl[0x02] = &bCPU::op_cop;
-optbl[0xdb] = &bCPU::op_stp;
-optbl[0xcb] = &bCPU::op_wai;
-optbl[0xfb] = &bCPU::op_xce;
-optbl[0x18] = &bCPU::op_clc;
-optbl[0xd8] = &bCPU::op_cld;
-optbl[0x58] = &bCPU::op_cli;
-optbl[0xb8] = &bCPU::op_clv;
-optbl[0x38] = &bCPU::op_sec;
-optbl[0xf8] = &bCPU::op_sed;
-optbl[0x78] = &bCPU::op_sei;
-optbl[0xc2] = &bCPU::op_rep;
-optbl[0xe2] = &bCPU::op_sep;
-optbl[0xaa] = &bCPU::op_tax;
-optbl[0xa8] = &bCPU::op_tay;
-optbl[0x8a] = &bCPU::op_txa;
-optbl[0x9b] = &bCPU::op_txy;
-optbl[0x98] = &bCPU::op_tya;
-optbl[0xbb] = &bCPU::op_tyx;
-optbl[0x5b] = &bCPU::op_tcd;
-optbl[0x1b] = &bCPU::op_tcs;
-optbl[0x7b] = &bCPU::op_tdc;
-optbl[0x3b] = &bCPU::op_tsc;
-optbl[0xba] = &bCPU::op_tsx;
-optbl[0x9a] = &bCPU::op_txs;
-optbl[0x48] = &bCPU::op_pha;
-optbl[0xda] = &bCPU::op_phx;
-optbl[0x5a] = &bCPU::op_phy;
-optbl[0x0b] = &bCPU::op_phd;
-optbl[0x8b] = &bCPU::op_phb;
-optbl[0x4b] = &bCPU::op_phk;
-optbl[0x08] = &bCPU::op_php;
-optbl[0x68] = &bCPU::op_pla;
-optbl[0xfa] = &bCPU::op_plx;
-optbl[0x7a] = &bCPU::op_ply;
-optbl[0x2b] = &bCPU::op_pld;
-optbl[0xab] = &bCPU::op_plb;
-optbl[0x28] = &bCPU::op_plp;
-optbl[0xf4] = &bCPU::op_pea;
-optbl[0xd4] = &bCPU::op_pei;
-optbl[0x62] = &bCPU::op_per;
@@ -1,260 +0,0 @@
-/* used by both DMA and HDMA
- * prevents transfer across same bus (a->a or b->b)
- */
-void bCPU::dma_transfer_byte(bool direction, uint8 bbus, uint32 abus) {
-uint8 r;
-  if(direction == 0) {
-  //read from address bus a, write to address bus b
-
-  //DMA address bus a cannot read from or write to the following addresses:
-  //$[00-3f|80-bf]:21[00-ff] <address bus b>
-  //$[00-3f|80-bf]:43[00-7f] <DMA control registers>
-  //$[00-3f|80-bf]:420b      <DMA enable register>
-  //$[00-3f|80-bf]:420c      <HDMA enable register>
-    if((abus & 0x40ff00) == 0x2100 || (abus & 0x40ff80) == 0x4300 ||
-       (abus & 0x40ffff) == 0x420b || (abus & 0x40ffff) == 0x420c) {
-    //these invalid reads will return open bus
-      r = r_cpu->regs.mdr;
-    } else {
-      r = r_mem->read(abus);
-    }
-
-    r_mem->write(0x2100 | bbus, r);
-  } else {
-  //read from address bus b, write to address bus a
-
-  //block invalid writes, see comments above
-    r = r_mem->read(0x2100 | bbus);
-    if((abus & 0x40ff00) == 0x2100 || (abus & 0x40ff80) == 0x4300 ||
-       (abus & 0x40ffff) == 0x420b || (abus & 0x40ffff) == 0x420c)return;
-    r_mem->write(abus, r);
-  }
-}
-
-uint8 bCPU::dma_bbus(uint8 i, uint8 index) {
-  switch(channel[i].xfermode) {
-  default:
-  case 0: return (channel[i].destaddr);                      break; //0
-  case 1: return (channel[i].destaddr + (index & 1));        break; //0,1
-  case 2: return (channel[i].destaddr);                      break; //0,0
-  case 3: return (channel[i].destaddr + ((index >> 1) & 1)); break; //0,0,1,1
-  case 4: return (channel[i].destaddr + (index & 3));        break; //0,1,2,3
-  case 5: return (channel[i].destaddr + (index & 1));        break; //0,1,0,1
-  case 6: return (channel[i].destaddr);                      break; //0,0     [2]
-  case 7: return (channel[i].destaddr + ((index >> 1) & 1)); break; //0,0,1,1 [3]
-  }
-}
-
-void bCPU::dma_add_cycles(uint32 cycles) {
-  status.dma_cycle_count += cycles;
-}
-
-void bCPU::hdma_add_cycles(uint32 cycles) {
-  if(run_state.dma) {
-    status.dma_cycle_count += cycles;
-  }
-  status.hdma_cycle_count += cycles;
-}
-
-uint32 bCPU::dma_addr(uint8 i) {
-uint32 r;
-  r = (channel[i].srcbank << 16) | (channel[i].srcaddr);
-
-  if(channel[i].fixedxfer == false) {
-    channel[i].srcaddr += channel[i].incmode;
-  }
-
-  return r;
-}
-
-void bCPU::dma_cputommio(uint8 i, uint8 bbus) {
-  if(cartridge.info.sdd1 == true && sdd1->dma_active() == true) {
-    r_mem->write(0x2100 | bbus, sdd1->dma_read());
-  } else {
-    dma_transfer_byte(0, bbus, dma_addr(i));
-  }
-
-  add_cycles(8);
-  channel[i].xfersize--;
-}
-
-void bCPU::dma_mmiotocpu(uint8 i, uint8 bbus) {
-  dma_transfer_byte(1, bbus, dma_addr(i));
-
-  add_cycles(8);
-  channel[i].xfersize--;
-}
-
-void bCPU::dma_write(uint8 i, uint8 index) {
-  if(channel[i].direction == 0) {
-    dma_cputommio(i, index);
-  } else {
-    dma_mmiotocpu(i, index);
-  }
-}
-
-void bCPU::dma_run() {
-  for(int i = 0; i < 8; i++) {
-    if(channel[i].dma_enabled == false)continue;
-
-  //first byte transferred?
-    if(cartridge.info.sdd1 == true && channel[i].read_index == 0) {
-      sdd1->dma_begin(i, (channel[i].srcbank << 16) | (channel[i].srcaddr),
-        channel[i].xfersize);
-    }
-
-    dma_write(i, dma_bbus(i, channel[i].read_index++));
-    dma_add_cycles(8);
-
-    if(channel[i].xfersize == 0) {
-      channel[i].dma_enabled = false;
-    }
-
-    return;
-  }
-
-  status.dma_state = DMASTATE_CPUSYNC;
-}
-
-uint32 bCPU::hdma_addr(uint8 i) {
-  return (channel[i].srcbank << 16) | (channel[i].hdma_addr++);
-}
-
-uint32 bCPU::hdma_iaddr(uint8 i) {
-  return (channel[i].hdma_ibank << 16) | (channel[i].hdma_iaddr++);
-}
-
-void bCPU::hdma_update(uint8 i) {
-  channel[i].hdma_line_counter = r_mem->read(hdma_addr(i));
-  add_cycles(8);
-  hdma_add_cycles(8);
-
-  if(channel[i].hdma_indirect) {
-    channel[i].hdma_iaddr = r_mem->read(hdma_addr(i)) << 8;
-    add_cycles(8);
-    hdma_add_cycles(8);
-  }
-
-  if(channel[i].hdma_line_counter == 0) {
-    channel[i].hdma_completed   = true;
-    channel[i].hdma_do_transfer = false;
-    return;
-  }
-
-  channel[i].hdma_do_transfer = true;
-
-  if(channel[i].hdma_indirect) {
-    channel[i].hdma_iaddr >>= 8;
-    channel[i].hdma_iaddr  |= r_mem->read(hdma_addr(i)) << 8;
-    add_cycles(8);
-    hdma_add_cycles(8);
-  }
-}
-
-void bCPU::hdma_run() {
-static uint8 hdma_xferlen[8] = { 1, 2, 2, 4, 4, 4, 2, 4 };
-  for(int i = 0; i < 8; i++) {
-    if(!channel[i].hdma_enabled || channel[i].hdma_completed)continue;
-
-    if(channel[i].hdma_do_transfer) {
-    int xferlen = hdma_xferlen[channel[i].xfermode];
-      for(channel[i].read_index = 0; channel[i].read_index < xferlen; channel[i].read_index++) {
-        if(bool(config::cpu.hdma_enable) == true) {
-          dma_transfer_byte(channel[i].direction, dma_bbus(i, channel[i].read_index),
-            channel[i].hdma_indirect ? hdma_iaddr(i) : hdma_addr(i));
-        }
-        add_cycles(8);
-        hdma_add_cycles(8);
-      }
-    }
-
-    channel[i].hdma_line_counter--;
-    channel[i].hdma_do_transfer = bool(channel[i].hdma_line_counter & 0x80);
-    if((channel[i].hdma_line_counter & 0x7f) == 0) {
-      hdma_update(i);
-    }
-  }
-}
-
-void bCPU::hdma_init() {
-  for(int i = 0; i < 8; i++) {
-    if(!channel[i].hdma_enabled)continue;
-
-    channel[i].hdma_addr = channel[i].srcaddr;
-    hdma_update(i);
-  }
-}
-
-uint8 bCPU::hdma_enabled_channels() {
-int r = 0;
-  for(int i = 0; i < 8; i++) {
-    if(channel[i].hdma_enabled)r++;
-  }
-  return r;
-}
-
-uint8 bCPU::hdma_active_channels() {
-int r = 0;
-  for(int i = 0; i < 8; i++) {
-    if(channel[i].hdma_enabled && !channel[i].hdma_completed)r++;
-  }
-  return r;
-}
-
-/* hdmainit_activate()
- * hdma_activate()
- *
- * Functions are called by CPU timing routine
- * when an HDMA event (init or run) occurs.
- */
-
-void bCPU::hdmainit_activate() {
-  for(int i = 0; i < 8; i++) {
-    channel[i].hdma_completed   = false;
-    channel[i].hdma_do_transfer = false;
-  }
-
-  if(hdma_enabled_channels() != 0) {
-    status.hdma_state = HDMASTATE_IDMASYNC;
-    run_state.hdma = true;
-  }
-}
-
-void bCPU::hdma_activate() {
-  if(hdma_active_channels() != 0) {
-    status.hdma_state = HDMASTATE_DMASYNC;
-    run_state.hdma = true;
-  }
-}
-
-void bCPU::dma_reset() {
-  status.dma_state        = DMASTATE_CPUSYNC;
-  status.hdma_state       = HDMASTATE_CPUSYNC;
-  status.dma_cycle_count  = 0;
-  status.hdma_cycle_count = 0;
-
-  for(int i = 0; i < 8; i++) {
-    channel[i].read_index        = 0;
-    channel[i].dma_enabled       = false;
-    channel[i].hdma_enabled      = false;
-    channel[i].dmap              = 0xff;
-    channel[i].direction         = 1;
-    channel[i].hdma_indirect     = 1;
-    channel[i].incmode           = -1;
-    channel[i].fixedxfer         = 1;
-    channel[i].xfermode          = 7;
-    channel[i].destaddr          = 0xff;
-    channel[i].srcaddr           = 0xffff;
-    channel[i].srcbank           = 0xff;
-    channel[i].xfersize          = 0xffff;
-  //xfersize and hdma_iaddr are of union { uint16 };
-  //channel[i].hdma_iaddr        = 0xffff;
-    channel[i].hdma_ibank        = 0xff;
-    channel[i].hdma_addr         = 0xffff;
-    channel[i].hdma_line_counter = 0xff;
-    channel[i].hdma_unknown      = 0xff;
-
-    channel[i].hdma_completed    = false;
-    channel[i].hdma_do_transfer  = false;
-  }
-}
@@ -1,61 +0,0 @@
-struct {
-  uint32 read_index; //set to 0 at beginning of DMA/HDMA
-
-//$420b
-  bool   dma_enabled;
-//$420c
-  bool   hdma_enabled;
-//$43x0
-  uint8  dmap;
-  bool   direction;
-  bool   hdma_indirect;
-  int8   incmode;
-  bool   fixedxfer;
-  uint8  xfermode;
-//$43x1
-  uint8  destaddr;
-//$43x2-$43x3
-  uint16 srcaddr;
-//$43x4
-  uint8  srcbank;
-//$43x5-$43x6
-  union {
-    uint16 xfersize;
-    uint16 hdma_iaddr;
-  };
-//$43x7
-  uint8  hdma_ibank;
-//$43x8-$43x9
-  uint16 hdma_addr;
-//$43xa
-  uint8  hdma_line_counter;
-//$43xb/$43xf
-  uint8  hdma_unknown;
-
-//hdma-specific
-  bool   hdma_completed; //for this frame
-  bool   hdma_do_transfer;
-
-  uint8  hdma_current_channel;
-  uint8  hdma_current_pos;
-} channel[8];
-
-  inline void   dma_transfer_byte(bool direction, uint8 bbus, uint32 abus);
-  inline uint8  dma_bbus(uint8 i, uint8 index);
-  inline void   dma_add_cycles(uint32 cycles);
-  inline void   hdma_add_cycles(uint32 cycles);
-  inline void   dma_run();
-  inline void   hdma_run();
-  inline void   hdma_init();
-  inline void   hdma_update(uint8 i);
-  inline uint8  hdma_enabled_channels();
-  inline uint8  hdma_active_channels();
-  inline void   hdmainit_activate();
-  inline void   hdma_activate();
-  inline void   dma_cputommio(uint8 i, uint8 index);
-  inline void   dma_mmiotocpu(uint8 i, uint8 index);
-  inline void   dma_write(uint8 i, uint8 index);
-  inline uint32 dma_addr(uint8 i);
-  inline uint32 hdma_addr(uint8 i);
-  inline uint32 hdma_iaddr(uint8 i);
-  inline void   dma_reset();
@@ -1,40 +0,0 @@
-uint8 bCPU::port_read(uint8 port) {
-  return apu_port[port & 3];
-}
-
-void bCPU::port_write(uint8 port, uint8 value) {
-  apu_port[port & 3] = value;
-}
-
-/* The next 3 functions control bus timing for the CPU.
- * cpu_io is an I/O cycle, and always 6 clock cycles long.
- * mem_read / mem_write indicate memory access bus cycle,
- * they are either 6, 8, or 12 bus cycles long, depending
- * both on location and the $420d.d0 FastROM enable bit.
- */
-
-void bCPU::cpu_io() {
-  status.cycle_count = 6;
-  pre_exec_cycle();
-  add_cycles(6);
-  cycle_edge();
-}
-
-uint8 bCPU::mem_read(uint32 addr) {
-  status.cycle_count = r_mem->speed(addr);
-  pre_exec_cycle();
-  add_cycles(status.cycle_count - 4);
-  regs.mdr = r_mem->read(addr);
-  add_cycles(4);
-  cycle_edge();
-  return regs.mdr;
-}
-
-void bCPU::mem_write(uint32 addr, uint8 value) {
-  status.cycle_count = r_mem->speed(addr);
-  pre_exec_cycle();
-  add_cycles(status.cycle_count);
-  regs.mdr = value;
-  r_mem->write(addr, value);
-  cycle_edge();
-}
@@ -1,27 +0,0 @@
-uint8 apu_port[4];
-  inline uint8  port_read (uint8 port);
-  inline void   port_write(uint8 port, uint8 value);
-
-  inline void   cpu_io();
-  inline uint8  mem_read(uint32 addr);
-  inline void   mem_write(uint32 addr, uint8 value);
-
-/*****
- * helper memory addressing functions used by CPU core
- *****/
-  uint8  op_readpc   ()                         { return mem_read((regs.pc.b << 16) + regs.pc.w++); }
-  uint8  op_readstack()                         { (regs.e) ? regs.s.l++ : regs.s.w++; return mem_read(regs.s.w); }
-  uint8  op_readaddr (uint32 addr)              { return mem_read(uclip<16>(addr)); }
-  uint8  op_readlong (uint32 addr)              { return mem_read(uclip<24>(addr)); }
-  uint8  op_readdbr  (uint32 addr)              { return mem_read(uclip<24>((regs.db << 16) + addr)); }
-  uint8  op_readpbr  (uint32 addr)              { return mem_read((regs.pc.b << 16) + uclip<16>(addr)); }
-  uint8  op_readdp   (uint32 addr)              { return mem_read(uclip<16>(regs.d + uclip<16>(addr))); }
-  uint8  op_readsp   (uint32 addr)              { return mem_read(uclip<16>(regs.s + uclip<16>(addr))); }
-
-  void   op_writestack(uint8  data)             { mem_write(regs.s.w, data); (regs.e) ? regs.s.l-- : regs.s.w--; }
-  void   op_writeaddr (uint32 addr, uint8 data) { mem_write(uclip<16>(addr), data); }
-  void   op_writelong (uint32 addr, uint8 data) { mem_write(uclip<24>(addr), data); }
-  void   op_writedbr  (uint32 addr, uint8 data) { mem_write(uclip<24>((regs.db << 16) + addr), data); }
-  void   op_writepbr  (uint32 addr, uint8 data) { mem_write((regs.pc.b << 16) + uclip<16>(addr), data); }
-  void   op_writedp   (uint32 addr, uint8 data) { mem_write(uclip<16>(regs.d + uclip<16>(addr)), data); }
-  void   op_writesp   (uint32 addr, uint8 data) { mem_write(uclip<16>(regs.s + uclip<16>(addr)), data); }
@@ -1,338 +0,0 @@
-/* Notes about PAL timing:
- * As I do not have PAL hardware to run timing tests on, I've
- * had to guess on a lot of things. Below is how I've arrived
- * at various calculations:
- *
- * NTSC timing crystal: ~21477272hz
- * PAL  timing crystal: ~21281370hz
- * NTSC ~60fps, PAL ~50fps
- * NTSC ~262 lines/frame, PAL ~312 lines/frame
- * NTSC 21477272 / (262 * 60) = ~1366 cycles/line
- * PAL  21281370 / (312 * 50) = ~1364 cycles/line
- *
- * As the cycles/line are very close between the two systems,
- * I have left the known NTSC anomalies intact for PAL timing.
- * In reality, some of these may not exist, and some may be
- * slightly different.
- *
- * [known]
- * - DRAM refresh occurs at about the same time every
- * scanline on PAL units (per Overload).
- * [unknown]
- * - Are dots 323/327 still 2 cycles longer than the
- * other dots?
- * - Is scanline 240 on non-interlace odd frames still
- * 4 cycles short?
- */
-
-uint16 bCPU::vcounter() { return time.v; }
-uint16 bCPU::hclock()  { return time.hc; }
-
-bool   bCPU::interlace()        { return time.interlace; }
-bool   bCPU::interlace_field()  { return time.interlace_field; }
-bool   bCPU::overscan()         { return time.overscan; }
-uint16 bCPU::region_scanlines() { return time.region_scanlines; }
-
-void   bCPU::set_interlace(bool r) { time.interlace = r; update_interrupts(); }
-void   bCPU::set_overscan (bool r) { time.overscan  = r; update_interrupts(); }
-
-uint8  bCPU::dma_counter() { return (time.dma_counter + time.hc) & 6; }
-
-uint16 bCPU::hcounter() {
-  if(time.v == 240 && time.interlace == false && time.interlace_field == 1) {
-    return time.hc >> 2;
-  }
-  return (time.hc - ((time.hc > 1292) << 1) - ((time.hc > 1310) << 1)) >> 2;
-}
-
-bool bCPU::nmi_trigger_pos_match(uint32 offset) {
-uint16 v  = overscan() ? 240 : 225;
-uint16 hc = 2 + offset;
-  return (time.v == v && time.hc == hc);
-}
-
-bool bCPU::irq_trigger_pos_match(uint32 offset) {
-uint16 v  = status.virq_pos;
-uint16 hc = (status.hirq_enabled) ? status.hirq_pos : 0;
-uint16 vlimit = region_scanlines() >> 1;
-
-//positions that can never be latched
-//region_scanlines() = 525/NTSC, 625/PAL
-//PAL results are unverified on hardware
-  if(v == 240 && hc == 339 && interlace() == false && interlace_field() == 1)return false;
-  if(v == (vlimit - 1) && hc == 339 && interlace() == false)return false;
-  if(v == vlimit && interlace() == false)return false;
-  if(v == vlimit && hc == 339)return false;
-  if(v  > vlimit)return false;
-  if(hc > 339)return false;
-
-  hc  = (hc != 0) ? ((hc << 2) + 14) : 10;
-  hc += offset;
-  if(hc >= time.line_cycles) {
-    hc -= time.line_cycles;
-    if(++v >= time.frame_lines) {
-      v = 0;
-    }
-  }
-
-  if((status.virq_enabled == true && time.v == v) || status.virq_enabled == false) {
-    return (time.hc == hc);
-  }
-
-  return false;
-}
-
-void bCPU::update_nmi() {
-  if(time.v == (overscan() ? 240 : 225)) {
-    time.nmi_read_trigger_pos = 2;
-    time.nmi_line_trigger_pos = 6;
-  } else {
-    time.nmi_read_trigger_pos = -64;
-    time.nmi_line_trigger_pos = -64;
-  }
-}
-
-void bCPU::update_irq() {
-int vpos = status.virq_pos;
-int hpos = (status.hirq_enabled) ? status.hirq_pos : 0;
-int vlimit = region_scanlines() >> 1;
-
-//positions that can never be latched
-//region_scanlines() = 262/NTSC, 312/PAL
-//PAL results are unverified on hardware
-  if(vpos == 240 && hpos == 339 && interlace() == false && interlace_field() == 1)goto _nolatch;
-  if(vpos == (vlimit - 1) && hpos == 339 && interlace() == false)goto _nolatch;
-  if(vpos == vlimit && interlace() == false)goto _nolatch;
-  if(vpos == vlimit && hpos == 339)goto _nolatch;
-  if(vpos  > vlimit)goto _nolatch;
-  if(hpos  > 339)goto _nolatch;
-
-  hpos = (hpos != 0) ? ((hpos << 2) + 14) : 10;
-  if(hpos >= time.line_cycles) {
-    hpos -= time.line_cycles;
-    if(++vpos >= time.frame_lines) {
-      vpos = 0;
-    }
-  }
-
-  if((status.virq_enabled == true && time.v == vpos) || status.virq_enabled == false) {
-    time.irq_read_trigger_pos = hpos;
-  } else {
-    time.irq_read_trigger_pos = -64;
-  }
-
-  hpos += 4;
-  if(hpos >= time.line_cycles) {
-    hpos -= time.line_cycles;
-    if(++vpos >= time.frame_lines) {
-      vpos = 0;
-    }
-  }
-
-  if((status.virq_enabled == true && time.v == vpos) || status.virq_enabled == false) {
-    time.irq_line_trigger_pos = hpos;
-  } else {
-    time.irq_line_trigger_pos = -64;
-  }
-
-  return;
-
-_nolatch:
-  time.irq_read_trigger_pos = -64;
-  time.irq_line_trigger_pos = -64;
-}
-
-void bCPU::update_interrupts() {
-  update_nmi();
-  update_irq();
-}
-
-void bCPU::poll_interrupts(int cycles) {
-int16 hc, hc_end;
-  if(time.hc == 0) {
-    hc     = -1;
-    hc_end = cycles;
-  } else {
-    hc     = time.hc;
-    hc_end = time.hc + cycles;
-  }
-
-  if(hc < time.nmi_read_trigger_pos && time.nmi_read_trigger_pos <= hc_end) {
-  //nmi_read can go low even with NMI interrupts disabled in $4200.d7
-    time.nmi_read = 0;
-  }
-
-  if(hc < time.nmi_line_trigger_pos && time.nmi_line_trigger_pos <= hc_end) {
-    if(status.nmi_enabled == true) {
-      if(time.nmi_line == 1) {
-        time.nmi_transition = 1;
-      }
-      time.nmi_line = 0;
-    }
-  }
-
-  if(hc < time.irq_read_trigger_pos && time.irq_read_trigger_pos <= hc_end) {
-    if(status.virq_enabled == true || status.hirq_enabled == true) {
-      time.irq_read = 0;
-    }
-  }
-
-  if(hc < time.irq_line_trigger_pos && time.irq_line_trigger_pos <= hc_end) {
-    if(status.virq_enabled == true || status.hirq_enabled == true) {
-      time.irq_line = 0;
-      time.irq_transition = 1;
-    }
-  }
-}
-
-uint32 bCPU::clocks_executed() {
-uint32 r = status.cycles_executed;
-  status.cycles_executed = 0;
-  return r;
-}
-
-void bCPU::cycle_edge() {
-  if(time.line_rendered == false) {
-    if(time.hc >= 192) {
-      time.line_rendered = true;
-      r_ppu->render_scanline();
-    }
-  }
-
-  if(time.hdmainit_triggered == false) {
-    if(time.hc >= time.hdmainit_trigger_pos || time.v) {
-      time.hdmainit_triggered = true;
-      hdmainit_activate();
-    }
-  }
-
-  if(time.hdma_triggered == false) {
-  //hdma_triggered only set to false for v <= (overscan ? 239 : 224)
-    if(time.hc >= 1106) {
-      time.hdma_triggered = true;
-      hdma_activate();
-    }
-  }
-}
-
-void bCPU::add_cycles(int cycles) {
-  status.cycles_executed += cycles;
-  poll_interrupts(cycles);
-
-  if(time.hc + cycles >= time.line_cycles) {
-    cycles  = (time.hc + cycles) - time.line_cycles;
-    time.hc = 0;
-    scanline();
-    poll_interrupts(cycles);
-  }
-
-  time.hc += cycles;
-
-  if(time.dram_refreshed == false) {
-    if(time.hc >= time.dram_refresh_pos) {
-      time.dram_refreshed = true;
-      add_cycles(40);
-      return;
-    }
-  }
-}
-
-void bCPU::scanline() {
-  if(++time.v >= time.frame_lines) {
-    frame();
-  }
-
-  time.dma_counter += time.line_cycles;
-  if(time.v == 240 && time.interlace == false && time.interlace_field == 1) {
-    time.line_cycles = 1360;
-  } else {
-    time.line_cycles = 1364;
-  }
-  time.dram_refreshed = false;
-
-  time.line_rendered  =
-  time.hdma_triggered = (time.v <= (!overscan() ? 224 : 239)) ? false : true;
-
-  r_ppu->scanline();
-  snes->scanline();
-
-  update_interrupts();
-
-  if(vcounter() == (!overscan() ? 227 : 242) && status.auto_joypad_poll == true) {
-    snes->poll_input();
-  //When the SNES auto-polls the joypads, it writes 1, then 0 to
-  //$4016, then reads from each 16 times to get the joypad state
-  //information. As a result, the joypad read positions are set
-  //to 16 after such a poll. Position 16 is the controller
-  //connected status bit.
-    status.joypad1_read_pos = 16;
-    status.joypad2_read_pos = 16;
-  }
-}
-
-void bCPU::frame() {
-  time.nmi_read = 1;
-  time.nmi_line = 1;
-  time.nmi_transition = 0;
-
-  time.v = 0;
-  time.interlace_field ^= 1;
-  if(interlace() == true && interlace_field() == 0) {
-    time.frame_lines = (time.region_scanlines >> 1) + 1;
-  } else {
-    time.frame_lines = (time.region_scanlines >> 1);
-  }
-
-  if(cpu_version == 2) {
-    time.hdmainit_trigger_pos = 12 + dma_counter();
-  } else {
-    time.hdmainit_trigger_pos = 12 + 8 - dma_counter();
-  }
-  time.hdmainit_triggered = false;
-
-  r_ppu->frame();
-  snes->frame();
-}
-
-void bCPU::time_reset() {
-  time.v  = 0;
-  time.hc = 0;
-
-//upon SNES reset, start at scanline 0 non-interlace
-  time.interlace       = 0;
-  time.interlace_field = 0;
-  time.overscan        = false;
-  time.line_cycles     = 1364;
-
-  time.dram_refreshed   = false;
-  time.dram_refresh_pos = (cpu_version == 2) ? 538 : 530;
-
-  time.dma_counter = 0;
-
-//set at V=0,H=0
-  time.hdmainit_trigger_pos = 0;
-  time.hdmainit_triggered   = true;
-
-  time.hdma_triggered = false;
-
-  time.nmi_pending = false;
-  time.irq_pending = false;
-  time.nmi_line = time.nmi_read = 1;
-  time.irq_line = time.irq_read = 1;
-
-  time.nmi_transition = 0;
-  time.irq_transition = 0;
-
-  update_interrupts();
-
-  switch(region) {
-  case NTSC:
-    time.region_scanlines = 525;
-    break;
-  case PAL:
-    time.region_scanlines = 625;
-    break;
-  }
-
-  time.frame_lines = time.region_scanlines >> 1;
-}
@@ -1,74 +0,0 @@
-struct {
-  uint16 v, hc;
-
-  bool   interlace, interlace_field, overscan;
-  uint16 line_cycles, frame_lines;
-
-  bool   line_rendered;
-
-  bool   dram_refreshed;
-  uint16 dram_refresh_pos;
-
-  uint8  dma_counter;
-
-  uint16 hdmainit_trigger_pos;
-  bool   hdmainit_triggered;
-
-  bool   hdma_triggered;
-
-  uint16 region_scanlines;
-
-//nmi_pending, irq_pending are used by last_cycle()
-//nmi_line = /NMI, nmi_read = $4210.7
-//irq_line = /IRQ, irq_read = $4211.7
-  bool   nmi_pending, nmi_line, nmi_read;
-  bool   irq_pending, irq_line, irq_read;
-
-//NMI is edge-sensitive, meaning it triggers when /NMI
-//transitions from high to low. This value is set to 1
-//when that happens, and cleared after the nmi_test()
-//routine acknowledges it and invokes the NMI interrupt
-  bool   nmi_transition;
-
-//IRQ is level-sensitive, so it does not need to keep
-//track of transitions from high to low. IRQs will
-//continue to fire as long as /IRQ stays low.
-//However, if a write to $4200 forces IRQs high at the
-//exact same clock cycle that /IRQ goes low, the /IRQ
-//will still occur. Hence the need for this variable.
-  bool   irq_transition;
-
-//position is relative to time.hc, set at start of each scanline
-//-64 means no trigger point on this scanline
-//$4210/$4211 status bits get set before /NMI and /IRQ go low,
-//hence the need for two variables for each.
-  int32  nmi_read_trigger_pos, nmi_line_trigger_pos;
-  int32  irq_read_trigger_pos, irq_line_trigger_pos;
-} time;
-
-  inline uint16 vcounter();
-  inline uint16 hcounter();
-  inline uint16 hclock();
-  inline bool   interlace();
-  inline bool   interlace_field();
-  inline bool   overscan();
-  inline uint16 region_scanlines();
-
-  inline bool   nmi_trigger_pos_match(uint32 offset);
-  inline bool   irq_trigger_pos_match(uint32 offset);
-
-  inline void   update_nmi();
-  inline void   update_irq();
-  inline void   update_interrupts();
-  inline void   poll_interrupts(int cycles);
-
-  inline void   set_interlace(bool r);
-  inline void   set_overscan (bool r);
-
-  inline uint8  dma_counter();
-
-  inline void   cycle_edge();
-  inline void   add_cycles(int cycles);
-  inline void   scanline();
-  inline void   frame();
-  inline void   time_reset();
@@ -1,8 +1,10 @@
-#include "../base.h"
+#include "../base.h"
+#define CPU_CPP
+
 #include "dcpu.cpp"

 CPU::CPU() {
-  cpu_version = 1;
+  cpu_version = 2;
 }

 CPU::~CPU() {
@@ -2,83 +2,78 @@

 class CPU : public MMIO {
 public:
-//CPU version number
-//* 1 and 2 are known
-//* reported by $4210
-//* affects DRAM refresh behavior
-uint8 cpu_version;
+  virtual void enter() = 0;

-//timing
+  //CPU version number
+  //* 1 and 2 are known
+  //* reported by $4210
+  //* affects DRAM refresh behavior
+  uint8 cpu_version;
+
+  //timing
  virtual uint16 vcounter() = 0;
  virtual uint16 hcounter() = 0;
-  virtual uint16 hclock() = 0;
-  virtual bool   interlace() = 0;
-  virtual bool   interlace_field() = 0;
-  virtual bool   overscan() = 0;
-  virtual uint16 region_scanlines() = 0;
-  virtual void   set_interlace(bool r) = 0;
-  virtual void   set_overscan (bool r) = 0;
-
-CPURegs regs;
-  virtual uint8 port_read (uint8 port) = 0;
-  virtual void  port_write(uint8 port, uint8 value) = 0;
+  virtual uint16 hdot() = 0;

+  virtual uint8 pio() = 0;
+  virtual bool joylatch() = 0;
+  virtual uint8 port_read(uint8 port) = 0;
+  virtual void port_write(uint8 port, uint8 value) = 0;
+
+  CPURegs regs;
  enum {
    FLAG_N = 0x80, FLAG_V = 0x40,
    FLAG_M = 0x20, FLAG_X = 0x10,
    FLAG_D = 0x08, FLAG_I = 0x04,
    FLAG_Z = 0x02, FLAG_C = 0x01
  };
-  virtual uint8  pio_status() = 0;
-  virtual void   main() {}
-  virtual void   run() = 0;
-  virtual uint32 clocks_executed() = 0;
-  virtual void   scanline() = 0;
-  virtual void   frame() = 0;
-  virtual void   power() = 0;
-  virtual void   reset() = 0;
+
+  virtual void scanline() = 0;
+  virtual void frame() = 0;
+  virtual void power() = 0;
+  virtual void reset() = 0;

-/*****
- * in opcode-based CPU emulators, the main emulation routine
- * will only be able to call the disassemble_opcode() function
- * on clean opcode edges. but with cycle-based CPU emulators,
- * the CPU may be in the middle of executing an opcode when the
- * emulator (e.g. debugger) wants to disassemble an opcode. this
- * would mean that important registers may not reflect what they
- * did at the start of the opcode (especially regs.pc), so in
- * cycle-based emulators, this function should be overridden to
- * reflect whether or not an opcode has only been partially
- * executed. if not, the debugger should abort attempts to skip,
- * disable, or disassemble the current opcode.
- *****/
+  /*****
+   * in opcode-based CPU emulators, the main emulation routine
+   * will only be able to call the disassemble_opcode() function
+   * on clean opcode edges. but with cycle-based CPU emulators,
+   * the CPU may be in the middle of executing an opcode when the
+   * emulator (e.g. debugger) wants to disassemble an opcode. this
+   * would mean that important registers may not reflect what they
+   * did at the start of the opcode (especially regs.pc), so in
+   * cycle-based emulators, this function should be overridden to
+   * reflect whether or not an opcode has only been partially
+   * executed. if not, the debugger should abort attempts to skip,
+   * disable, or disassemble the current opcode.
+   *****/
  virtual bool in_opcode() { return false; }

-/*****
- * opcode disassembler
- *****/
-enum {
-  OPTYPE_DP = 0,    //dp
-  OPTYPE_DPX,       //dp,x
-  OPTYPE_DPY,       //dp,y
-  OPTYPE_IDP,       //(dp)
-  OPTYPE_IDPX,      //(dp,x)
-  OPTYPE_IDPY,      //(dp),y
-  OPTYPE_ILDP,      //[dp]
-  OPTYPE_ILDPY,     //[dp],y
-  OPTYPE_ADDR,      //addr
-  OPTYPE_ADDRX,     //addr,x
-  OPTYPE_ADDRY,     //addr,y
-  OPTYPE_IADDRX,    //(addr,x)
-  OPTYPE_ILADDR,    //[addr]
-  OPTYPE_LONG,      //long
-  OPTYPE_LONGX,     //long, x
-  OPTYPE_SR,        //sr,s
-  OPTYPE_ISRY,      //(sr,s),y
-  OPTYPE_ADDR_PC,   //pbr:addr
-  OPTYPE_IADDR_PC,  //pbr:(addr)
-  OPTYPE_RELB,      //relb
-  OPTYPE_RELW,      //relw
-};
+  /*****
+   * opcode disassembler
+   *****/
+  enum {
+    OPTYPE_DP = 0,    //dp
+    OPTYPE_DPX,       //dp,x
+    OPTYPE_DPY,       //dp,y
+    OPTYPE_IDP,       //(dp)
+    OPTYPE_IDPX,      //(dp,x)
+    OPTYPE_IDPY,      //(dp),y
+    OPTYPE_ILDP,      //[dp]
+    OPTYPE_ILDPY,     //[dp],y
+    OPTYPE_ADDR,      //addr
+    OPTYPE_ADDRX,     //addr,x
+    OPTYPE_ADDRY,     //addr,y
+    OPTYPE_IADDRX,    //(addr,x)
+    OPTYPE_ILADDR,    //[addr]
+    OPTYPE_LONG,      //long
+    OPTYPE_LONGX,     //long, x
+    OPTYPE_SR,        //sr,s
+    OPTYPE_ISRY,      //(sr,s),y
+    OPTYPE_ADDR_PC,   //pbr:addr
+    OPTYPE_IADDR_PC,  //pbr:(addr)
+    OPTYPE_RELB,      //relb
+    OPTYPE_RELW,      //relw
+  };

  void   disassemble_opcode(char *output);
  uint8  dreadb(uint32 addr);
				`@@ -0,0 +1 @@`
				`@make platform=win compiler=mingw32-gcc clean`