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Refactoring the RISCV architecture to Auto-Sync on LLVM (#2756)

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- Updated to LLVM-18
- Operands have now read/write access information
- Previously only the basic extensions and the compressed ISA was supported, now every extension supported by LLVM-18 also available (e.g. vector, crypto, ...)
- Changed register names
  * FP Regs: Instead of `RISCV_REG_F<n>_32` and `RISCV_REG_F<n>_64`, they're named `RISCV_REG_F<n>_F`
  and `RISCV_REG_F<n>_D` for n in `0..31`
- Added register names
  * Vector registes and combinations thereof `RISCV_REG_V<n>[_V<n_i>]*`, examples
    * `RISCV_REG_V21`
    * `RISCV_REG_V9_V10`
    * `RISCV_REG_V3_V4_V5`
    * etc... up to 8-register combinations
  * Half-percision (16-bit) FP registers `RISCV_REG_F<n>_H` for n in `0..31`
- Changed instruction names
  * Instructions ending in `_AQ_RL` now end in `_AQRL`
- Added instruction names: massive amount, see `include/capstone/riscv.h`
- Added `dimm` and `csr` fields inside the union data of `cs_riscv_op`, with corresponding `riscv_op_type`
  * `dimm` is used for instructions with FP immediates
  * `csr` is used for instructions with CSR systrem registes
- Added ISA flags to turn ISA extensions on and off
This commit is contained in:
مصطفي محمود كمال الدين
2026-02-01 11:53:24 +00:00
committed by GitHub
parent 484857da5d
commit ec6428f92d
424 changed files with 316880 additions and 14808 deletions
Download Patch File Download Diff File Expand all files Collapse all files
CMakeLists.txt
+17 -4
View File
@@ -599,25 +599,38 @@ endif()
if(CAPSTONE_RISCV_SUPPORT)
add_definitions(-DCAPSTONE_HAS_RISCV)
set(SOURCES_RISCV
arch/RISCV/RISCVBaseInfo.c
arch/RISCV/RISCVDisassembler.c
arch/RISCV/RISCVDisassemblerExtension.c
arch/RISCV/RISCVInstPrinter.c
arch/RISCV/RISCVMapping.c
arch/RISCV/RISCVModule.c
)
set(HEADERS_RISCV
arch/RISCV/RISCVBaseInfo.h
arch/RISCV/RISCVDisassembler.h
arch/RISCV/RISCVDisassemblerExtension.h
arch/RISCV/RISCVInstPrinter.h
arch/RISCV/RISCVMapping.h
arch/RISCV/RISCVModule.h
arch/RISCV/RISCVLinkage.h
arch/RISCV/RISCVGenAsmWriter.inc
arch/RISCV/RISCVGenCSAliasMnemMap.inc
arch/RISCV/RISCVGenCSFeatureName.inc
arch/RISCV/RISCVGenCSMappingInsn.inc
arch/RISCV/RISCVGenCSMappingInsnName.inc
arch/RISCV/RISCVGenCSMappingInsnOp.inc
arch/RISCV/RISCVGenCSOpGroup.inc
arch/RISCV/RISCVGenCSSystemOperandsEnum.inc
arch/RISCV/RISCVGenDisassemblerTables.inc
arch/RISCV/RISCVGenInsnNameMaps.inc
arch/RISCV/RISCVGenInstrInfo.inc
arch/RISCV/RISCVGenRegisterInfo.inc
arch/RISCV/RISCVGenSubtargetInfo.inc
arch/RISCV/RISCVMappingInsn.inc
arch/RISCV/RISCVMappingInsnOp.inc
arch/RISCV/RISCVGenSystemOperands.inc
arch/RISCV/RISCVGenCompressedInstructionsInfo.inc
arch/RISCV/RISCVGenCSAliasEnum.inc
arch/RISCV/RISCVGenCSFeatureEnum.inc
arch/RISCV/RISCVGenCSInsnEnum.inc
arch/RISCV/RISCVGenCSRegEnum.inc
)
endif()
MCInstPrinter.c
+5
View File
@@ -11,6 +11,7 @@ extern bool Mips_getFeatureBits(unsigned int mode, unsigned int feature);
extern bool AArch64_getFeatureBits(unsigned int mode, unsigned int feature);
extern bool TriCore_getFeatureBits(unsigned int mode, unsigned int feature);
extern bool Sparc_getFeatureBits(unsigned int mode, unsigned int feature);
extern bool RISCV_getFeatureBits(unsigned int mode, unsigned int feature);
static bool testFeatureBits(const MCInst *MI, uint32_t Value)
{
@@ -42,6 +43,10 @@ static bool testFeatureBits(const MCInst *MI, uint32_t Value)
#ifdef CAPSTONE_HAS_SPARC
case CS_ARCH_SPARC:
return Sparc_getFeatureBits(MI->csh->mode, Value);
#endif
#ifdef CAPSTONE_HAS_RISCV
case CS_ARCH_RISCV:
return RISCV_getFeatureBits(MI->csh->mode, Value);
#endif
}
}
Mapping.c
+28
View File
@@ -359,6 +359,34 @@ DEFINE_get_detail_op(bpf, BPF, BPF);
DEFINE_get_detail_op(arc, ARC, ARC);
DEFINE_get_detail_op(sparc, Sparc, SPARC);
/// Returns the operand at detail->arch.operands[index]
/// Or NULL if detail is not set or the index would be out of bounds.
#define DEFINE_get_detail_op_at(arch, ARCH, ARCH_UPPER) \
cs_##arch##_op *ARCH##_get_detail_op_at(MCInst *MI, int index) \
{ \
if (!MI->flat_insn->detail) \
return NULL; \
if (index < 0 || index >= NUM_##ARCH_UPPER##_OPS) { \
return NULL; \
} \
return &MI->flat_insn->detail->arch.operands[index]; \
}
DEFINE_get_detail_op_at(arm, ARM, ARM);
DEFINE_get_detail_op_at(ppc, PPC, PPC);
DEFINE_get_detail_op_at(tricore, TriCore, TRICORE);
DEFINE_get_detail_op_at(aarch64, AArch64, AARCH64);
DEFINE_get_detail_op_at(alpha, Alpha, ALPHA);
DEFINE_get_detail_op_at(hppa, HPPA, HPPA);
DEFINE_get_detail_op_at(loongarch, LoongArch, LOONGARCH);
DEFINE_get_detail_op_at(mips, Mips, MIPS);
DEFINE_get_detail_op_at(riscv, RISCV, RISCV);
DEFINE_get_detail_op_at(systemz, SystemZ, SYSTEMZ);
DEFINE_get_detail_op_at(xtensa, Xtensa, XTENSA);
DEFINE_get_detail_op_at(bpf, BPF, BPF);
DEFINE_get_detail_op_at(arc, ARC, ARC);
DEFINE_get_detail_op_at(sparc, Sparc, SPARC);
/// Returns true if for this architecture the
/// alias operands should be filled.
/// TODO: Replace this with a proper option.
Mapping.h
+21 -3
View File
@@ -21,9 +21,9 @@ typedef struct insn_map {
unsigned short mapid; // The Capstone instruction id
#ifndef CAPSTONE_DIET
uint16_t regs_use[MAX_IMPL_R_REGS]; ///< list of implicit registers used by
///< this instruction
///< this instruction
uint16_t regs_mod[MAX_IMPL_W_REGS]; ///< list of implicit registers modified
///< by this instruction
///< by this instruction
unsigned char groups
[MAX_NUM_GROUPS]; ///< list of group this instruction belong to
bool branch; // branch instruction?
@@ -48,7 +48,7 @@ unsigned short insn_find(const insn_map *m, unsigned int max, unsigned int id,
unsigned int find_cs_id(unsigned MC_Opcode, const insn_map *imap,
unsigned imap_size);
#define MAX_NO_DATA_TYPES 16
#define MAX_NO_DATA_TYPES 32
///< A LLVM<->CS Mapping entry of an MCOperand.
typedef struct {
@@ -147,6 +147,24 @@ DECL_get_detail_op(bpf, BPF);
DECL_get_detail_op(arc, ARC);
DECL_get_detail_op(sparc, Sparc);
#define DECL_get_detail_op_at(arch, ARCH) \
cs_##arch##_op *ARCH##_get_detail_op_at(MCInst *MI, int offset);
DECL_get_detail_op_at(arm, ARM);
DECL_get_detail_op_at(ppc, PPC);
DECL_get_detail_op_at(tricore, TriCore);
DECL_get_detail_op_at(aarch64, AArch64);
DECL_get_detail_op_at(alpha, Alpha);
DECL_get_detail_op_at(hppa, HPPA);
DECL_get_detail_op_at(loongarch, LoongArch);
DECL_get_detail_op_at(mips, Mips);
DECL_get_detail_op_at(riscv, RISCV);
DECL_get_detail_op_at(systemz, SystemZ);
DECL_get_detail_op_at(xtensa, Xtensa);
DECL_get_detail_op_at(bpf, BPF);
DECL_get_detail_op_at(arc, ARC);
DECL_get_detail_op_at(sparc, Sparc);
/// Increments the detail->arch.op_count by one.
#define DEFINE_inc_detail_op_count(arch, ARCH) \
static inline void ARCH##_inc_op_count(MCInst *MI) \
MathExtras.h
+11
View File
@@ -62,6 +62,17 @@ static inline bool isIntN(unsigned N, int64_t x)
(-(INT64_C(1) << (N - 1)) <= x && x < (INT64_C(1) << (N - 1)));
}
/// isShiftedIntN - Checks if a signed integer is an N bit number shifted left by S.
static inline bool isShiftedIntN(unsigned N, unsigned S, int64_t x)
{
return isIntN(N + S, x) && (x % (UINT64_C(1) << S) == 0);
}
static inline bool isShiftedUIntN(unsigned N, unsigned S, uint64_t x)
{
return isUIntN(N + S, x) && (x % (UINT64_C(1) << S) == 0);
}
/// isMask_32 - This function returns true if the argument is a sequence of ones
/// starting at the least significant bit with the remainder zero (32 bit
/// version). Ex. isMask_32(0x0000FFFFU) == true.
SStream.c
+7
View File
@@ -510,6 +510,13 @@ void printFloat(SStream *ss, float val)
SStream_concat(ss, "%e", val);
}
void printfFloat(SStream *ss, const char *fmt, float val)
{
assert(ss);
SSTREAM_RETURN_IF_CLOSED(ss);
SStream_concat(ss, fmt, val);
}
void printFloatBang(SStream *ss, float val)
{
assert(ss);
SStream.h
+2
View File
@@ -94,6 +94,8 @@ void printInt32BangDec(SStream *O, int32_t val);
void printFloat(SStream *O, float val);
void printfFloat(SStream *ss, const char *fmt, float val);
void printFloatBang(SStream *O, float val);
void printExpr(SStream *O, uint64_t val);
arch/RISCV/RISCVBaseInfo.c
+139
View File
@@ -0,0 +1,139 @@
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* By Nguyen Anh Quynh <[email protected]>, 2013-2022, */
/* Rot127 <[email protected]> 2022-2023 */
/* Automatically translated source file from LLVM. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Only small edits allowed. */
/* For multiple similar edits, please create a Patch for the translator. */
/* Capstone's C++ file translator: */
/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
//===-- RISCVBaseInfo.cpp - Top level definitions for RISC-V MC -----------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file contains small standalone enum definitions for the RISC-V target
// useful for the compiler back-end and the MC libraries.
//
//===----------------------------------------------------------------------===//
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <capstone/platform.h>
#include "RISCVBaseInfo.h"
#define CONCAT(a, b) CONCAT_(a, b)
#define CONCAT_(a, b) a##_##b
typedef struct {
unsigned value;
bool isFractional;
} VLMULDecodeResult;
VLMULDecodeResult decodeVLMUL(RISCVII_VLMUL VLMUL)
{
switch (VLMUL) {
default:
CS_ASSERT(0 && "Unexpected LMUL value!");
case RISCVII_LMUL_1:
case RISCVII_LMUL_2:
case RISCVII_LMUL_4:
case RISCVII_LMUL_8: {
VLMULDecodeResult result = { .value = 1 << (unsigned)(VLMUL),
.isFractional = false };
return result;
}
case RISCVII_LMUL_F2:
case RISCVII_LMUL_F4:
case RISCVII_LMUL_F8: {
VLMULDecodeResult result = { .value = 1 << (8 -
(unsigned)(VLMUL)),
.isFractional = true };
return result;
}
}
}
void printVType(unsigned VType, SStream *OS)
{
unsigned Sew = RISCVVType_getSEW(VType);
SStream_concat(OS, "%s", "e");
printUInt64(OS, Sew);
unsigned LMul;
bool Fractional;
VLMULDecodeResult result = decodeVLMUL(RISCVVType_getVLMUL(VType));
LMul = result.value;
Fractional = result.isFractional;
if (Fractional)
SStream_concat0(OS, ", mf");
else
SStream_concat0(OS, ", m");
printUInt64(OS, LMul);
if (RISCVVType_isTailAgnostic(VType))
SStream_concat0(OS, ", ta");
else
SStream_concat0(OS, ", tu");
if (RISCVVType_isMaskAgnostic(VType))
SStream_concat0(OS, ", ma");
else
SStream_concat0(OS, ", mu");
}
typedef struct {
uint8_t first;
uint8_t second;
} LoadFP32ImmArrElement;
// Lookup table for fli.s for entries 2-31.
static const LoadFP32ImmArrElement LoadFP32ImmArr[] = {
{ 0x6f, 0x00 }, { 0x70, 0x00 }, { 0x77, 0x00 }, { 0x78, 0x00 },
{ 0x7b, 0x00 }, { 0x7c, 0x00 }, { 0x7d, 0x00 }, { 0x7d, 0x01 },
{ 0x7d, 0x02 }, { 0x7d, 0x03 }, { 0x7e, 0x00 }, { 0x7e, 0x01 },
{ 0x7e, 0x02 }, { 0x7e, 0x03 }, { 0x7f, 0x00 }, { 0x7f, 0x01 },
{ 0x7f, 0x02 }, { 0x7f, 0x03 }, { 0x80, 0x00 }, { 0x80, 0x01 },
{ 0x80, 0x02 }, { 0x81, 0x00 }, { 0x82, 0x00 }, { 0x83, 0x00 },
{ 0x86, 0x00 }, { 0x87, 0x00 }, { 0x8e, 0x00 }, { 0x8f, 0x00 },
{ 0xff, 0x00 }, { 0xff, 0x02 },
};
float getFPImm(unsigned Imm)
{
CS_ASSERT(Imm != 1 && Imm != 30 && Imm != 31 &&
"Unsupported immediate");
CS_ASSERT((Imm == 0 || (Imm >= 2 && Imm < 30)) &&
"Unsupported immediate");
// Entry 0 is -1.0, the only negative value. Entry 16 is 1.0.
uint32_t Sign = 0;
if (Imm == 0) {
Sign = 0x01;
Imm = 16;
}
uint32_t Exp = LoadFP32ImmArr[Imm - 2].first;
uint32_t Mantissa = LoadFP32ImmArr[Imm - 2].second;
uint32_t I = Sign << 31 | Exp << 23 | Mantissa << 21;
float result;
memcpy(&result, &I, sizeof(float));
return result;
}
void RISCVZC_printSpimm(int64_t Spimm, SStream *OS)
{
printInt32(OS, Spimm);
}
// namespace llvm
arch/RISCV/RISCVBaseInfo.h
+245 -53
View File
@@ -1,64 +1,126 @@
//===-- RISCVBaseInfo.h - Top level definitions for RISCV MC ----*- C++ -*-===//
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* By Nguyen Anh Quynh <[email protected]>, 2013-2022, */
/* Rot127 <[email protected]> 2022-2023 */
/* Automatically translated source file from LLVM. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Only small edits allowed. */
/* For multiple similar edits, please create a Patch for the translator. */
/* Capstone's C++ file translator: */
/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
//===-- RISCVBaseInfo.h - Top level definitions for RISC-V MC ---*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file contains small standalone enum definitions for the RISCV target
// This file contains small standalone enum definitions for the RISC-V target
// useful for the compiler back-end and the MC libraries.
//
//===----------------------------------------------------------------------===//
#ifndef CS_RISCVBASEINFO_H
#define CS_RISCVBASEINFO_H
#include "../../cs_priv.h"
#ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
#define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
//#include "RISCVMCTargetDesc.h"
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <capstone/platform.h>
#include "../../utils.h"
#define CONCAT(a, b) CONCAT_(a, b)
#define CONCAT_(a, b) a##_##b
// RISCVII - This namespace holds all of the target specific flags that
// instruction info tracks. All definitions must match RISCVInstrFormats.td.
enum {
IRISCVII_InstFormatPseudo = 0,
IRISCVII_InstFormatR = 1,
IRISCVII_InstFormatR4 = 2,
IRISCVII_InstFormatI = 3,
IRISCVII_InstFormatS = 4,
IRISCVII_InstFormatB = 5,
IRISCVII_InstFormatU = 6,
IRISCVII_InstFormatJ = 7,
IRISCVII_InstFormatCR = 8,
IRISCVII_InstFormatCI = 9,
IRISCVII_InstFormatCSS = 10,
IRISCVII_InstFormatCIW = 11,
IRISCVII_InstFormatCL = 12,
IRISCVII_InstFormatCS = 13,
IRISCVII_InstFormatCA = 14,
IRISCVII_InstFormatCB = 15,
IRISCVII_InstFormatCJ = 16,
IRISCVII_InstFormatOther = 17,
// CS namespace begin: RISCVII
IRISCVII_InstFormatMask = 31
// RISC-V Specific Machine Operand Flags
enum {
RISCVII_MO_None = 0,
RISCVII_MO_CALL = 1,
RISCVII_MO_LO = 3,
RISCVII_MO_HI = 4,
RISCVII_MO_PCREL_LO = 5,
RISCVII_MO_PCREL_HI = 6,
RISCVII_MO_GOT_HI = 7,
RISCVII_MO_TPREL_LO = 8,
RISCVII_MO_TPREL_HI = 9,
RISCVII_MO_TPREL_ADD = 10,
RISCVII_MO_TLS_GOT_HI = 11,
RISCVII_MO_TLS_GD_HI = 12,
RISCVII_MO_TLSDESC_HI = 13,
RISCVII_MO_TLSDESC_LOAD_LO = 14,
RISCVII_MO_TLSDESC_ADD_LO = 15,
RISCVII_MO_TLSDESC_CALL = 16,
// Used to differentiate between target-specific "direct" flags and "bitmask"
// flags. A machine operand can only have one "direct" flag, but can have
// multiple "bitmask" flags.
RISCVII_MO_DIRECT_FLAG_MASK = 31
};
enum {
RISCVII_MO_None,
RISCVII_MO_LO,
RISCVII_MO_HI,
RISCVII_MO_PCREL_HI,
};
typedef enum OperandType {
RISCVOp_OPERAND_FIRST_RISCV_IMM = MCOI_OPERAND_FIRST_TARGET,
RISCVOp_OPERAND_UIMM1 = RISCVOp_OPERAND_FIRST_RISCV_IMM,
RISCVOp_OPERAND_UIMM2,
RISCVOp_OPERAND_UIMM2_LSB0,
RISCVOp_OPERAND_UIMM3,
RISCVOp_OPERAND_UIMM4,
RISCVOp_OPERAND_UIMM5,
RISCVOp_OPERAND_UIMM6,
RISCVOp_OPERAND_UIMM7,
RISCVOp_OPERAND_UIMM7_LSB00,
RISCVOp_OPERAND_UIMM8_LSB00,
RISCVOp_OPERAND_UIMM8,
RISCVOp_OPERAND_UIMM8_LSB000,
RISCVOp_OPERAND_UIMM8_GE32,
RISCVOp_OPERAND_UIMM9_LSB000,
RISCVOp_OPERAND_UIMM10_LSB00_NONZERO,
RISCVOp_OPERAND_UIMM12,
RISCVOp_OPERAND_ZERO,
RISCVOp_OPERAND_SIMM5,
RISCVOp_OPERAND_SIMM5_PLUS1,
RISCVOp_OPERAND_SIMM6,
RISCVOp_OPERAND_SIMM6_NONZERO,
RISCVOp_OPERAND_SIMM10_LSB0000_NONZERO,
RISCVOp_OPERAND_SIMM12,
RISCVOp_OPERAND_SIMM12_LSB00000,
RISCVOp_OPERAND_UIMM20,
RISCVOp_OPERAND_UIMMLOG2XLEN,
RISCVOp_OPERAND_UIMMLOG2XLEN_NONZERO,
RISCVOp_OPERAND_CLUI_IMM,
RISCVOp_OPERAND_VTYPEI10,
RISCVOp_OPERAND_VTYPEI11,
RISCVOp_OPERAND_RVKRNUM,
RISCVOp_OPERAND_RVKRNUM_0_7,
RISCVOp_OPERAND_RVKRNUM_1_10,
RISCVOp_OPERAND_RVKRNUM_2_14,
OPERAND_LAST_RISCV_IMM = RISCVOp_OPERAND_RVKRNUM_2_14,
// Operand is either a register or uimm5, this is used by V extension pseudo
// instructions to represent a value that be passed as AVL to either vsetvli
// or vsetivli.
RISCVOp_OPERAND_AVL,
} RISCVOp_OperandType;
// Describes the predecessor/successor bits used in the FENCE instruction.
enum FenceField {
typedef enum FenceField {
RISCVFenceField_I = 8,
RISCVFenceField_O = 4,
RISCVFenceField_R = 2,
RISCVFenceField_W = 1
};
} RISCVFenceField_FenceField;
// Describes the supported floating point rounding mode encodings.
enum RoundingMode {
typedef enum RoundingMode {
RISCVFPRndMode_RNE = 0,
RISCVFPRndMode_RTZ = 1,
RISCVFPRndMode_RDN = 2,
@@ -66,9 +128,24 @@ enum RoundingMode {
RISCVFPRndMode_RMM = 4,
RISCVFPRndMode_DYN = 7,
RISCVFPRndMode_Invalid
};
} RISCVFPRndMode_RoundingMode;
inline static const char *roundingModeToString(enum RoundingMode RndMode)
inline static bool RISCVFPRndMode_isValidRoundingMode(unsigned Mode)
{
switch (Mode) {
default:
return false;
case RISCVFPRndMode_RNE:
case RISCVFPRndMode_RTZ:
case RISCVFPRndMode_RDN:
case RISCVFPRndMode_RUP:
case RISCVFPRndMode_RMM:
case RISCVFPRndMode_DYN:
return true;
}
}
inline static const char *RISCVFPRndMode_roundingModeToString(unsigned RndMode)
{
switch (RndMode) {
default:
@@ -88,19 +165,134 @@ inline static const char *roundingModeToString(enum RoundingMode RndMode)
}
}
inline static bool RISCVFPRndMode_isValidRoundingMode(unsigned Mode)
inline static bool RISCVVType_isTailAgnostic(unsigned VType)
{
switch (Mode) {
default:
return false;
case RISCVFPRndMode_RNE:
case RISCVFPRndMode_RTZ:
case RISCVFPRndMode_RDN:
case RISCVFPRndMode_RUP:
case RISCVFPRndMode_RMM:
case RISCVFPRndMode_DYN:
return true;
}
return VType & 0x40;
}
inline static bool RISCVVType_isMaskAgnostic(unsigned VType)
{
return VType & 0x80;
}
typedef enum RLISTENCODE {
RISCVZC_RLISTENCODE_RA = 4,
RISCVZC_RLISTENCODE_RA_S0,
RISCVZC_RLISTENCODE_RA_S0_S1,
RISCVZC_RLISTENCODE_RA_S0_S2,
RISCVZC_RLISTENCODE_RA_S0_S3,
RISCVZC_RLISTENCODE_RA_S0_S4,
RISCVZC_RLISTENCODE_RA_S0_S5,
RISCVZC_RLISTENCODE_RA_S0_S6,
RISCVZC_RLISTENCODE_RA_S0_S7,
RISCVZC_RLISTENCODE_RA_S0_S8,
RISCVZC_RLISTENCODE_RA_S0_S9,
// note - to include s10, s11 must also be included
RISCVZC_RLISTENCODE_RA_S0_S11,
RISCVZC_RLISTENCODE_INVALID_RLIST,
} RISCVZC_RLISTENCODE;
inline static unsigned RISCVZC_getStackAdjBase(unsigned RlistVal, bool IsRV64,
bool IsEABI)
{
CS_ASSERT(RlistVal != RISCVZC_RLISTENCODE_INVALID_RLIST &&
"{ra, s0-s10} is not supported, s11 must be included.");
if (IsEABI)
return 16;
if (!IsRV64) {
switch (RlistVal) {
case RISCVZC_RLISTENCODE_RA:
case RISCVZC_RLISTENCODE_RA_S0:
case RISCVZC_RLISTENCODE_RA_S0_S1:
case RISCVZC_RLISTENCODE_RA_S0_S2:
return 16;
case RISCVZC_RLISTENCODE_RA_S0_S3:
case RISCVZC_RLISTENCODE_RA_S0_S4:
case RISCVZC_RLISTENCODE_RA_S0_S5:
case RISCVZC_RLISTENCODE_RA_S0_S6:
return 32;
case RISCVZC_RLISTENCODE_RA_S0_S7:
case RISCVZC_RLISTENCODE_RA_S0_S8:
case RISCVZC_RLISTENCODE_RA_S0_S9:
return 48;
case RISCVZC_RLISTENCODE_RA_S0_S11:
return 64;
}
} else {
switch (RlistVal) {
case RISCVZC_RLISTENCODE_RA:
case RISCVZC_RLISTENCODE_RA_S0:
return 16;
case RISCVZC_RLISTENCODE_RA_S0_S1:
case RISCVZC_RLISTENCODE_RA_S0_S2:
return 32;
case RISCVZC_RLISTENCODE_RA_S0_S3:
case RISCVZC_RLISTENCODE_RA_S0_S4:
return 48;
case RISCVZC_RLISTENCODE_RA_S0_S5:
case RISCVZC_RLISTENCODE_RA_S0_S6:
return 64;
case RISCVZC_RLISTENCODE_RA_S0_S7:
case RISCVZC_RLISTENCODE_RA_S0_S8:
return 80;
case RISCVZC_RLISTENCODE_RA_S0_S9:
return 96;
case RISCVZC_RLISTENCODE_RA_S0_S11:
return 112;
}
}
CS_ASSERT(0 && "Unexpected RlistVal");
return 0; // unreachable
}
typedef enum VLMUL {
RISCVII_LMUL_1 = 0,
RISCVII_LMUL_2,
RISCVII_LMUL_4,
RISCVII_LMUL_8,
RISCVII_LMUL_RESERVED,
RISCVII_LMUL_F8,
RISCVII_LMUL_F4,
RISCVII_LMUL_F2
} RISCVII_VLMUL;
inline static RISCVII_VLMUL RISCVVType_getVLMUL(unsigned VType)
{
unsigned VLMUL = VType & 0x7;
return (RISCVII_VLMUL)(VLMUL);
}
inline static unsigned RISCVVType_decodeVSEW(unsigned VSEW)
{
CS_ASSERT(VSEW < 8 && "Unexpected VSEW value");
return 1 << (VSEW + 3);
}
inline static unsigned RISCVVType_getSEW(unsigned VType)
{
unsigned VSEW = (VType >> 3) & 0x7;
return RISCVVType_decodeVSEW(VSEW);
}
typedef struct {
unsigned raw_val;
} RegVal;
typedef struct SysReg {
const char *Name;
RegVal val1;
const char *AltName;
RegVal val2;
const char *DeprecatedName;
unsigned Encoding;
unsigned DummyFeatureArray[1];
bool isRV32Only;
} RISCV_SysReg;
void printVType(unsigned VType, SStream *OS);
float getFPImm(unsigned Imm);
void RISCVZC_printSpimm(int64_t Spimm, SStream *OS);
#endif
arch/RISCV/RISCVDisassembler.c
+646 -345
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File diff suppressed because it is too large Load Diff
arch/RISCV/RISCVDisassemblerExtension.c
+90
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@@ -0,0 +1,90 @@
#include "RISCVDisassemblerExtension.h"
#define GET_SUBTARGETINFO_ENUM
#include "RISCVGenSubtargetInfo.inc"
bool RISCV_getFeatureBits(unsigned int mode, unsigned int feature)
{
if (feature == RISCV_FeatureNoRVCHints) {
return false;
}
switch (feature) {
case RISCV_Feature32Bit:
return mode & CS_MODE_RISCV32;
case RISCV_Feature64Bit:
return mode & CS_MODE_RISCV64;
case RISCV_FeatureStdExtF:
case RISCV_FeatureStdExtD:
return mode & CS_MODE_RISCV_FD;
case RISCV_FeatureStdExtV:
return mode & CS_MODE_RISCV_V;
case RISCV_FeatureStdExtZfinx:
case RISCV_FeatureStdExtZdinx:
case RISCV_FeatureStdExtZhinx:
case RISCV_FeatureStdExtZhinxmin:
return mode & CS_MODE_RISCV_ZFINX;
case RISCV_FeatureStdExtC:
return mode & CS_MODE_RISCV_C;
case RISCV_FeatureStdExtZcmp:
case RISCV_FeatureStdExtZcmt:
case RISCV_FeatureStdExtZce:
return mode & CS_MODE_RISCV_ZCMP_ZCMT_ZCE;
case RISCV_FeatureStdExtZicfiss:
return mode & CS_MODE_RISCV_ZICFISS;
case RISCV_FeatureRVE:
return mode & CS_MODE_RISCV_E;
case RISCV_FeatureStdExtA:
return mode & CS_MODE_RISCV_A;
case RISCV_FeatureVendorXCVelw:
return mode & CS_MODE_RISCV_COREV;
case RISCV_FeatureVendorXSfvcp:
case RISCV_FeatureVendorXSfvfnrclipxfqf:
case RISCV_FeatureVendorXSfvfwmaccqqq:
case RISCV_FeatureVendorXSfvqmaccdod:
case RISCV_FeatureVendorXSfvqmaccqoq:
return mode & CS_MODE_RISCV_SIFIVE;
case RISCV_FeatureVendorXTHeadBa:
case RISCV_FeatureVendorXTHeadBb:
case RISCV_FeatureVendorXTHeadBs:
case RISCV_FeatureVendorXTHeadCmo:
case RISCV_FeatureVendorXTHeadCondMov:
case RISCV_FeatureVendorXTHeadFMemIdx:
case RISCV_FeatureVendorXTHeadMac:
case RISCV_FeatureVendorXTHeadMemIdx:
case RISCV_FeatureVendorXTHeadMemPair:
case RISCV_FeatureVendorXTHeadSync:
case RISCV_FeatureVendorXTHeadVdot:
return mode & CS_MODE_RISCV_THEAD;
case RISCV_FeatureStdExtZba:
return mode & CS_MODE_RISCV_ZBA;
case RISCV_FeatureStdExtZbb:
return mode & CS_MODE_RISCV_ZBB;
case RISCV_FeatureStdExtZbc:
return mode & CS_MODE_RISCV_ZBC;
case RISCV_FeatureStdExtZbkb:
return mode & CS_MODE_RISCV_ZBKB;
case RISCV_FeatureStdExtZbkc:
return mode & CS_MODE_RISCV_ZBKC;
case RISCV_FeatureStdExtZbkx:
return mode & CS_MODE_RISCV_ZBKX;
case RISCV_FeatureStdExtZbs:
return mode & CS_MODE_RISCV_ZBS;
default:
// support everything by default
return true;
}
}
arch/RISCV/RISCVDisassemblerExtension.h
+8
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@@ -0,0 +1,8 @@
#ifndef CS_RISCV_DISASSEMBLER_EXTENSION_H
#define CS_RISCV_DISASSEMBLER_EXTENSION_H
#include "../../cs_priv.h"
bool RISCV_getFeatureBits(unsigned int mode, unsigned int feature);
#endif // CS_RISCV_DISASSEMBLER_EXTENSION_H
arch/RISCV/RISCVGenAsmWriter.inc
+29038 -2127
View File
File diff suppressed because it is too large Load Diff
arch/RISCV/RISCVGenCSAliasEnum.inc
+99
View File
@@ -0,0 +1,99 @@
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <[email protected]>, 2013-2022, */
/* Rot127 <[email protected]> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
RISCV_INS_ALIAS_NOP, // Real instr.: RISCV_ADDI
RISCV_INS_ALIAS_LI, // Real instr.: RISCV_ADDI
RISCV_INS_ALIAS_MV, // Real instr.: RISCV_ADDI
RISCV_INS_ALIAS_NOT, // Real instr.: RISCV_XORI
RISCV_INS_ALIAS_NEG, // Real instr.: RISCV_SUB
RISCV_INS_ALIAS_NEGW, // Real instr.: RISCV_SUBW
RISCV_INS_ALIAS_SEXT_W, // Real instr.: RISCV_ADDIW
RISCV_INS_ALIAS_SEQZ, // Real instr.: RISCV_SLTIU
RISCV_INS_ALIAS_SNEZ, // Real instr.: RISCV_SLTU
RISCV_INS_ALIAS_SLTZ, // Real instr.: RISCV_SLT
RISCV_INS_ALIAS_SGTZ, // Real instr.: RISCV_SLT
RISCV_INS_ALIAS_BEQZ, // Real instr.: RISCV_BEQ
RISCV_INS_ALIAS_BNEZ, // Real instr.: RISCV_BNE
RISCV_INS_ALIAS_BLEZ, // Real instr.: RISCV_BGE
RISCV_INS_ALIAS_BGEZ, // Real instr.: RISCV_BGE
RISCV_INS_ALIAS_BLTZ, // Real instr.: RISCV_BLT
RISCV_INS_ALIAS_BGTZ, // Real instr.: RISCV_BLT
RISCV_INS_ALIAS_J, // Real instr.: RISCV_JAL
RISCV_INS_ALIAS_JAL, // Real instr.: RISCV_JAL
RISCV_INS_ALIAS_JR, // Real instr.: RISCV_JALR
RISCV_INS_ALIAS_JALR, // Real instr.: RISCV_JALR
RISCV_INS_ALIAS_RET, // Real instr.: RISCV_JALR
RISCV_INS_ALIAS_FENCE, // Real instr.: RISCV_FENCE
RISCV_INS_ALIAS_PAUSE, // Real instr.: RISCV_FENCE
RISCV_INS_ALIAS_RDINSTRET, // Real instr.: RISCV_CSRRS
RISCV_INS_ALIAS_RDCYCLE, // Real instr.: RISCV_CSRRS
RISCV_INS_ALIAS_RDTIME, // Real instr.: RISCV_CSRRS
RISCV_INS_ALIAS_RDINSTRETH, // Real instr.: RISCV_CSRRS
RISCV_INS_ALIAS_RDCYCLEH, // Real instr.: RISCV_CSRRS
RISCV_INS_ALIAS_RDTIMEH, // Real instr.: RISCV_CSRRS
RISCV_INS_ALIAS_CSRR, // Real instr.: RISCV_CSRRS
RISCV_INS_ALIAS_CSRW, // Real instr.: RISCV_CSRRW
RISCV_INS_ALIAS_CSRS, // Real instr.: RISCV_CSRRS
RISCV_INS_ALIAS_CSRC, // Real instr.: RISCV_CSRRC
RISCV_INS_ALIAS_CSRWI, // Real instr.: RISCV_CSRRWI
RISCV_INS_ALIAS_CSRSI, // Real instr.: RISCV_CSRRSI
RISCV_INS_ALIAS_CSRCI, // Real instr.: RISCV_CSRRCI
RISCV_INS_ALIAS_SFENCE_VMA, // Real instr.: RISCV_SFENCE_VMA
RISCV_INS_ALIAS_HFENCE_GVMA, // Real instr.: RISCV_HFENCE_GVMA
RISCV_INS_ALIAS_HFENCE_VVMA, // Real instr.: RISCV_HFENCE_VVMA
RISCV_INS_ALIAS_NTL_P1, // Real instr.: RISCV_ADD
RISCV_INS_ALIAS_NTL_PALL, // Real instr.: RISCV_ADD
RISCV_INS_ALIAS_NTL_S1, // Real instr.: RISCV_ADD
RISCV_INS_ALIAS_NTL_ALL, // Real instr.: RISCV_ADD
RISCV_INS_ALIAS_LPAD, // Real instr.: RISCV_AUIPC
RISCV_INS_ALIAS_FMV_S, // Real instr.: RISCV_FSGNJ_S
RISCV_INS_ALIAS_FABS_S, // Real instr.: RISCV_FSGNJX_S
RISCV_INS_ALIAS_FNEG_S, // Real instr.: RISCV_FSGNJN_S
RISCV_INS_ALIAS_FRCSR, // Real instr.: RISCV_CSRRS
RISCV_INS_ALIAS_FSCSR, // Real instr.: RISCV_CSRRW
RISCV_INS_ALIAS_FRRM, // Real instr.: RISCV_CSRRS
RISCV_INS_ALIAS_FSRM, // Real instr.: RISCV_CSRRW
RISCV_INS_ALIAS_FSRMI, // Real instr.: RISCV_CSRRWI
RISCV_INS_ALIAS_FRFLAGS, // Real instr.: RISCV_CSRRS
RISCV_INS_ALIAS_FSFLAGS, // Real instr.: RISCV_CSRRW
RISCV_INS_ALIAS_FSFLAGSI, // Real instr.: RISCV_CSRRWI
RISCV_INS_ALIAS_FMV_D, // Real instr.: RISCV_FSGNJ_D
RISCV_INS_ALIAS_FABS_D, // Real instr.: RISCV_FSGNJX_D
RISCV_INS_ALIAS_FNEG_D, // Real instr.: RISCV_FSGNJN_D
RISCV_INS_ALIAS_FMV_H, // Real instr.: RISCV_FSGNJ_H
RISCV_INS_ALIAS_FABS_H, // Real instr.: RISCV_FSGNJX_H
RISCV_INS_ALIAS_FNEG_H, // Real instr.: RISCV_FSGNJN_H
RISCV_INS_ALIAS_ZEXT_W, // Real instr.: RISCV_ADD_UW
RISCV_INS_ALIAS_VL1R_V, // Real instr.: RISCV_VL1RE8_V
RISCV_INS_ALIAS_VL2R_V, // Real instr.: RISCV_VL2RE8_V
RISCV_INS_ALIAS_VL4R_V, // Real instr.: RISCV_VL4RE8_V
RISCV_INS_ALIAS_VL8R_V, // Real instr.: RISCV_VL8RE8_V
RISCV_INS_ALIAS_VNEG_V, // Real instr.: RISCV_VRSUB_VX
RISCV_INS_ALIAS_VWCVT_X_X_V, // Real instr.: RISCV_VWADD_VX
RISCV_INS_ALIAS_VWCVTU_X_X_V, // Real instr.: RISCV_VWADDU_VX
RISCV_INS_ALIAS_VNOT_V, // Real instr.: RISCV_VXOR_VI
RISCV_INS_ALIAS_VNCVT_X_X_W, // Real instr.: RISCV_VNSRL_WX
RISCV_INS_ALIAS_VFNEG_V, // Real instr.: RISCV_VFSGNJN_VV
RISCV_INS_ALIAS_VFABS_V, // Real instr.: RISCV_VFSGNJX_VV
RISCV_INS_ALIAS_VMMV_M, // Real instr.: RISCV_VMAND_MM
RISCV_INS_ALIAS_VMCLR_M, // Real instr.: RISCV_VMXOR_MM
RISCV_INS_ALIAS_VMSET_M, // Real instr.: RISCV_VMXNOR_MM
RISCV_INS_ALIAS_VMNOT_M, // Real instr.: RISCV_VMNAND_MM
RISCV_INS_ALIAS_C_NTL_P1, // Real instr.: RISCV_C_ADD_HINT
RISCV_INS_ALIAS_C_NTL_PALL, // Real instr.: RISCV_C_ADD_HINT
RISCV_INS_ALIAS_C_NTL_S1, // Real instr.: RISCV_C_ADD_HINT
RISCV_INS_ALIAS_C_NTL_ALL, // Real instr.: RISCV_C_ADD_HINT
RISCV_INS_ALIAS_CV_MULS, // Real instr.: RISCV_CV_MULSN
RISCV_INS_ALIAS_CV_MULHHS, // Real instr.: RISCV_CV_MULHHSN
RISCV_INS_ALIAS_CV_MULU, // Real instr.: RISCV_CV_MULUN
RISCV_INS_ALIAS_CV_MULHHU, // Real instr.: RISCV_CV_MULHHUN
arch/RISCV/RISCVGenCSAliasMnemMap.inc
+99
View File
@@ -0,0 +1,99 @@
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <[email protected]>, 2013-2022, */
/* Rot127 <[email protected]> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
{ RISCV_INS_ALIAS_NOP, "nop" },
{ RISCV_INS_ALIAS_LI, "li" },
{ RISCV_INS_ALIAS_MV, "mv" },
{ RISCV_INS_ALIAS_NOT, "not" },
{ RISCV_INS_ALIAS_NEG, "neg" },
{ RISCV_INS_ALIAS_NEGW, "negw" },
{ RISCV_INS_ALIAS_SEXT_W, "sext_w" },
{ RISCV_INS_ALIAS_SEQZ, "seqz" },
{ RISCV_INS_ALIAS_SNEZ, "snez" },
{ RISCV_INS_ALIAS_SLTZ, "sltz" },
{ RISCV_INS_ALIAS_SGTZ, "sgtz" },
{ RISCV_INS_ALIAS_BEQZ, "beqz" },
{ RISCV_INS_ALIAS_BNEZ, "bnez" },
{ RISCV_INS_ALIAS_BLEZ, "blez" },
{ RISCV_INS_ALIAS_BGEZ, "bgez" },
{ RISCV_INS_ALIAS_BLTZ, "bltz" },
{ RISCV_INS_ALIAS_BGTZ, "bgtz" },
{ RISCV_INS_ALIAS_J, "j" },
{ RISCV_INS_ALIAS_JAL, "jal" },
{ RISCV_INS_ALIAS_JR, "jr" },
{ RISCV_INS_ALIAS_JALR, "jalr" },
{ RISCV_INS_ALIAS_RET, "ret" },
{ RISCV_INS_ALIAS_FENCE, "fence" },
{ RISCV_INS_ALIAS_PAUSE, "pause" },
{ RISCV_INS_ALIAS_RDINSTRET, "rdinstret" },
{ RISCV_INS_ALIAS_RDCYCLE, "rdcycle" },
{ RISCV_INS_ALIAS_RDTIME, "rdtime" },
{ RISCV_INS_ALIAS_RDINSTRETH, "rdinstreth" },
{ RISCV_INS_ALIAS_RDCYCLEH, "rdcycleh" },
{ RISCV_INS_ALIAS_RDTIMEH, "rdtimeh" },
{ RISCV_INS_ALIAS_CSRR, "csrr" },
{ RISCV_INS_ALIAS_CSRW, "csrw" },
{ RISCV_INS_ALIAS_CSRS, "csrs" },
{ RISCV_INS_ALIAS_CSRC, "csrc" },
{ RISCV_INS_ALIAS_CSRWI, "csrwi" },
{ RISCV_INS_ALIAS_CSRSI, "csrsi" },
{ RISCV_INS_ALIAS_CSRCI, "csrci" },
{ RISCV_INS_ALIAS_SFENCE_VMA, "sfence_vma" },
{ RISCV_INS_ALIAS_HFENCE_GVMA, "hfence_gvma" },
{ RISCV_INS_ALIAS_HFENCE_VVMA, "hfence_vvma" },
{ RISCV_INS_ALIAS_NTL_P1, "ntl_p1" },
{ RISCV_INS_ALIAS_NTL_PALL, "ntl_pall" },
{ RISCV_INS_ALIAS_NTL_S1, "ntl_s1" },
{ RISCV_INS_ALIAS_NTL_ALL, "ntl_all" },
{ RISCV_INS_ALIAS_LPAD, "lpad" },
{ RISCV_INS_ALIAS_FMV_S, "fmv_s" },
{ RISCV_INS_ALIAS_FABS_S, "fabs_s" },
{ RISCV_INS_ALIAS_FNEG_S, "fneg_s" },
{ RISCV_INS_ALIAS_FRCSR, "frcsr" },
{ RISCV_INS_ALIAS_FSCSR, "fscsr" },
{ RISCV_INS_ALIAS_FRRM, "frrm" },
{ RISCV_INS_ALIAS_FSRM, "fsrm" },
{ RISCV_INS_ALIAS_FSRMI, "fsrmi" },
{ RISCV_INS_ALIAS_FRFLAGS, "frflags" },
{ RISCV_INS_ALIAS_FSFLAGS, "fsflags" },
{ RISCV_INS_ALIAS_FSFLAGSI, "fsflagsi" },
{ RISCV_INS_ALIAS_FMV_D, "fmv_d" },
{ RISCV_INS_ALIAS_FABS_D, "fabs_d" },
{ RISCV_INS_ALIAS_FNEG_D, "fneg_d" },
{ RISCV_INS_ALIAS_FMV_H, "fmv_h" },
{ RISCV_INS_ALIAS_FABS_H, "fabs_h" },
{ RISCV_INS_ALIAS_FNEG_H, "fneg_h" },
{ RISCV_INS_ALIAS_ZEXT_W, "zext_w" },
{ RISCV_INS_ALIAS_VL1R_V, "vl1r_v" },
{ RISCV_INS_ALIAS_VL2R_V, "vl2r_v" },
{ RISCV_INS_ALIAS_VL4R_V, "vl4r_v" },
{ RISCV_INS_ALIAS_VL8R_V, "vl8r_v" },
{ RISCV_INS_ALIAS_VNEG_V, "vneg_v" },
{ RISCV_INS_ALIAS_VWCVT_X_X_V, "vwcvt_x_x_v" },
{ RISCV_INS_ALIAS_VWCVTU_X_X_V, "vwcvtu_x_x_v" },
{ RISCV_INS_ALIAS_VNOT_V, "vnot_v" },
{ RISCV_INS_ALIAS_VNCVT_X_X_W, "vncvt_x_x_w" },
{ RISCV_INS_ALIAS_VFNEG_V, "vfneg_v" },
{ RISCV_INS_ALIAS_VFABS_V, "vfabs_v" },
{ RISCV_INS_ALIAS_VMMV_M, "vmmv_m" },
{ RISCV_INS_ALIAS_VMCLR_M, "vmclr_m" },
{ RISCV_INS_ALIAS_VMSET_M, "vmset_m" },
{ RISCV_INS_ALIAS_VMNOT_M, "vmnot_m" },
{ RISCV_INS_ALIAS_C_NTL_P1, "c_ntl_p1" },
{ RISCV_INS_ALIAS_C_NTL_PALL, "c_ntl_pall" },
{ RISCV_INS_ALIAS_C_NTL_S1, "c_ntl_s1" },
{ RISCV_INS_ALIAS_C_NTL_ALL, "c_ntl_all" },
{ RISCV_INS_ALIAS_CV_MULS, "cv_muls" },
{ RISCV_INS_ALIAS_CV_MULHHS, "cv_mulhhs" },
{ RISCV_INS_ALIAS_CV_MULU, "cv_mulu" },
{ RISCV_INS_ALIAS_CV_MULHHU, "cv_mulhhu" },
arch/RISCV/RISCVGenCSFeatureEnum.inc
+113
View File
@@ -0,0 +1,113 @@
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <[email protected]>, 2013-2022, */
/* Rot127 <[email protected]> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
RISCV_FEATURE_HASSTDEXTI = 128,
RISCV_FEATURE_HASSTDEXTZICBOM,
RISCV_FEATURE_HASSTDEXTZICBOP,
RISCV_FEATURE_HASSTDEXTZICBOZ,
RISCV_FEATURE_HASSTDEXTZICSR,
RISCV_FEATURE_HASSTDEXTZICOND,
RISCV_FEATURE_HASSTDEXTZIFENCEI,
RISCV_FEATURE_HASSTDEXTZIHINTPAUSE,
RISCV_FEATURE_HASSTDEXTZIHINTNTL,
RISCV_FEATURE_HASSTDEXTZIMOP,
RISCV_FEATURE_HASSTDEXTZICFILP,
RISCV_FEATURE_HASSTDEXTZICFISS,
RISCV_FEATURE_HASSTDEXTM,
RISCV_FEATURE_HASSTDEXTMORZMMUL,
RISCV_FEATURE_HASSTDEXTA,
RISCV_FEATURE_HASSTDEXTZTSO,
RISCV_FEATURE_HASSTDEXTZACAS,
RISCV_FEATURE_HASSTDEXTZAWRS,
RISCV_FEATURE_HASSTDEXTF,
RISCV_FEATURE_HASSTDEXTD,
RISCV_FEATURE_HASSTDEXTZFHMIN,
RISCV_FEATURE_HASSTDEXTZFH,
RISCV_FEATURE_HASSTDEXTZFBFMIN,
RISCV_FEATURE_HASHALFFPLOADSTOREMOVE,
RISCV_FEATURE_HASSTDEXTZFA,
RISCV_FEATURE_HASSTDEXTZFINX,
RISCV_FEATURE_HASSTDEXTZDINX,
RISCV_FEATURE_HASSTDEXTZHINXMIN,
RISCV_FEATURE_HASSTDEXTZHINX,
RISCV_FEATURE_HASSTDEXTC,
RISCV_FEATURE_HASRVCHINTS,
RISCV_FEATURE_HASSTDEXTCORZCA,
RISCV_FEATURE_HASSTDEXTZCB,
RISCV_FEATURE_HASSTDEXTCORZCD,
RISCV_FEATURE_HASSTDEXTZCMP,
RISCV_FEATURE_HASSTDEXTZCMT,
RISCV_FEATURE_HASSTDEXTCORZCFORZCE,
RISCV_FEATURE_HASSTDEXTZCMOP,
RISCV_FEATURE_HASSTDEXTZBA,
RISCV_FEATURE_HASSTDEXTZBB,
RISCV_FEATURE_HASSTDEXTZBC,
RISCV_FEATURE_HASSTDEXTZBS,
RISCV_FEATURE_HASSTDEXTZBKB,
RISCV_FEATURE_HASSTDEXTZBKX,
RISCV_FEATURE_HASSTDEXTZBBORZBKB,
RISCV_FEATURE_HASSTDEXTZBKC,
RISCV_FEATURE_HASSTDEXTZBCORZBKC,
RISCV_FEATURE_HASSTDEXTZKND,
RISCV_FEATURE_HASSTDEXTZKNE,
RISCV_FEATURE_HASSTDEXTZKNDORZKNE,
RISCV_FEATURE_HASSTDEXTZKNH,
RISCV_FEATURE_HASSTDEXTZKSED,
RISCV_FEATURE_HASSTDEXTZKSH,
RISCV_FEATURE_HASSTDEXTZKR,
RISCV_FEATURE_HASSTDEXTZVFBFMIN,
RISCV_FEATURE_HASSTDEXTZVFBFWMA,
RISCV_FEATURE_HASSTDEXTZFHORZVFH,
RISCV_FEATURE_HASSTDEXTZVKB,
RISCV_FEATURE_HASSTDEXTZVBB,
RISCV_FEATURE_HASSTDEXTZVBC,
RISCV_FEATURE_HASSTDEXTZVKG,
RISCV_FEATURE_HASSTDEXTZVKNED,
RISCV_FEATURE_HASSTDEXTZVKNHA,
RISCV_FEATURE_HASSTDEXTZVKNHB,
RISCV_FEATURE_HASSTDEXTZVKNHAORZVKNHB,
RISCV_FEATURE_HASSTDEXTZVKSED,
RISCV_FEATURE_HASSTDEXTZVKSH,
RISCV_FEATURE_HASVINSTRUCTIONS,
RISCV_FEATURE_HASVINSTRUCTIONSI64,
RISCV_FEATURE_HASVINSTRUCTIONSANYF,
RISCV_FEATURE_HASVINSTRUCTIONSF16MINIMAL,
RISCV_FEATURE_HASSTDEXTH,
RISCV_FEATURE_HASSTDEXTSVINVAL,
RISCV_FEATURE_HASVENDORXVENTANACONDOPS,
RISCV_FEATURE_HASVENDORXTHEADBA,
RISCV_FEATURE_HASVENDORXTHEADBB,
RISCV_FEATURE_HASVENDORXTHEADBS,
RISCV_FEATURE_HASVENDORXTHEADCONDMOV,
RISCV_FEATURE_HASVENDORXTHEADCMO,
RISCV_FEATURE_HASVENDORXTHEADFMEMIDX,
RISCV_FEATURE_HASVENDORXTHEADMAC,
RISCV_FEATURE_HASVENDORXTHEADMEMIDX,
RISCV_FEATURE_HASVENDORXTHEADMEMPAIR,
RISCV_FEATURE_HASVENDORXTHEADSYNC,
RISCV_FEATURE_HASVENDORXTHEADVDOT,
RISCV_FEATURE_HASVENDORXSFVCP,
RISCV_FEATURE_HASVENDORXSFVQMACCDOD,
RISCV_FEATURE_HASVENDORXSFVQMACCQOQ,
RISCV_FEATURE_HASVENDORXSFVFWMACCQQQ,
RISCV_FEATURE_HASVENDORXSFVFNRCLIPXFQF,
RISCV_FEATURE_HASVENDORXCVELW,
RISCV_FEATURE_HASVENDORXCVBITMANIP,
RISCV_FEATURE_HASVENDORXCVMAC,
RISCV_FEATURE_HASVENDORXCVMEM,
RISCV_FEATURE_HASVENDORXCVALU,
RISCV_FEATURE_HASVENDORXCVSIMD,
RISCV_FEATURE_HASVENDORXCVBI,
RISCV_FEATURE_ISRV64,
RISCV_FEATURE_ISRV32,
RISCV_FEATURE_ISRVE,
arch/RISCV/RISCVGenCSFeatureName.inc
+113
View File
@@ -0,0 +1,113 @@
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <[email protected]>, 2013-2022, */
/* Rot127 <[email protected]> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
{ RISCV_FEATURE_HASSTDEXTI, "HasStdExtI" },
{ RISCV_FEATURE_HASSTDEXTZICBOM, "HasStdExtZicbom" },
{ RISCV_FEATURE_HASSTDEXTZICBOP, "HasStdExtZicbop" },
{ RISCV_FEATURE_HASSTDEXTZICBOZ, "HasStdExtZicboz" },
{ RISCV_FEATURE_HASSTDEXTZICSR, "HasStdExtZicsr" },
{ RISCV_FEATURE_HASSTDEXTZICOND, "HasStdExtZicond" },
{ RISCV_FEATURE_HASSTDEXTZIFENCEI, "HasStdExtZifencei" },
{ RISCV_FEATURE_HASSTDEXTZIHINTPAUSE, "HasStdExtZihintpause" },
{ RISCV_FEATURE_HASSTDEXTZIHINTNTL, "HasStdExtZihintntl" },
{ RISCV_FEATURE_HASSTDEXTZIMOP, "HasStdExtZimop" },
{ RISCV_FEATURE_HASSTDEXTZICFILP, "HasStdExtZicfilp" },
{ RISCV_FEATURE_HASSTDEXTZICFISS, "HasStdExtZicfiss" },
{ RISCV_FEATURE_HASSTDEXTM, "HasStdExtM" },
{ RISCV_FEATURE_HASSTDEXTMORZMMUL, "HasStdExtMOrZmmul" },
{ RISCV_FEATURE_HASSTDEXTA, "HasStdExtA" },
{ RISCV_FEATURE_HASSTDEXTZTSO, "HasStdExtZtso" },
{ RISCV_FEATURE_HASSTDEXTZACAS, "HasStdExtZacas" },
{ RISCV_FEATURE_HASSTDEXTZAWRS, "HasStdExtZawrs" },
{ RISCV_FEATURE_HASSTDEXTF, "HasStdExtF" },
{ RISCV_FEATURE_HASSTDEXTD, "HasStdExtD" },
{ RISCV_FEATURE_HASSTDEXTZFHMIN, "HasStdExtZfhmin" },
{ RISCV_FEATURE_HASSTDEXTZFH, "HasStdExtZfh" },
{ RISCV_FEATURE_HASSTDEXTZFBFMIN, "HasStdExtZfbfmin" },
{ RISCV_FEATURE_HASHALFFPLOADSTOREMOVE, "HasHalfFPLoadStoreMove" },
{ RISCV_FEATURE_HASSTDEXTZFA, "HasStdExtZfa" },
{ RISCV_FEATURE_HASSTDEXTZFINX, "HasStdExtZfinx" },
{ RISCV_FEATURE_HASSTDEXTZDINX, "HasStdExtZdinx" },
{ RISCV_FEATURE_HASSTDEXTZHINXMIN, "HasStdExtZhinxmin" },
{ RISCV_FEATURE_HASSTDEXTZHINX, "HasStdExtZhinx" },
{ RISCV_FEATURE_HASSTDEXTC, "HasStdExtC" },
{ RISCV_FEATURE_HASRVCHINTS, "HasRVCHints" },
{ RISCV_FEATURE_HASSTDEXTCORZCA, "HasStdExtCOrZca" },
{ RISCV_FEATURE_HASSTDEXTZCB, "HasStdExtZcb" },
{ RISCV_FEATURE_HASSTDEXTCORZCD, "HasStdExtCOrZcd" },
{ RISCV_FEATURE_HASSTDEXTZCMP, "HasStdExtZcmp" },
{ RISCV_FEATURE_HASSTDEXTZCMT, "HasStdExtZcmt" },
{ RISCV_FEATURE_HASSTDEXTCORZCFORZCE, "HasStdExtCOrZcfOrZce" },
{ RISCV_FEATURE_HASSTDEXTZCMOP, "HasStdExtZcmop" },
{ RISCV_FEATURE_HASSTDEXTZBA, "HasStdExtZba" },
{ RISCV_FEATURE_HASSTDEXTZBB, "HasStdExtZbb" },
{ RISCV_FEATURE_HASSTDEXTZBC, "HasStdExtZbc" },
{ RISCV_FEATURE_HASSTDEXTZBS, "HasStdExtZbs" },
{ RISCV_FEATURE_HASSTDEXTZBKB, "HasStdExtZbkb" },
{ RISCV_FEATURE_HASSTDEXTZBKX, "HasStdExtZbkx" },
{ RISCV_FEATURE_HASSTDEXTZBBORZBKB, "HasStdExtZbbOrZbkb" },
{ RISCV_FEATURE_HASSTDEXTZBKC, "HasStdExtZbkc" },
{ RISCV_FEATURE_HASSTDEXTZBCORZBKC, "HasStdExtZbcOrZbkc" },
{ RISCV_FEATURE_HASSTDEXTZKND, "HasStdExtZknd" },
{ RISCV_FEATURE_HASSTDEXTZKNE, "HasStdExtZkne" },
{ RISCV_FEATURE_HASSTDEXTZKNDORZKNE, "HasStdExtZkndOrZkne" },
{ RISCV_FEATURE_HASSTDEXTZKNH, "HasStdExtZknh" },
{ RISCV_FEATURE_HASSTDEXTZKSED, "HasStdExtZksed" },
{ RISCV_FEATURE_HASSTDEXTZKSH, "HasStdExtZksh" },
{ RISCV_FEATURE_HASSTDEXTZKR, "HasStdExtZkr" },
{ RISCV_FEATURE_HASSTDEXTZVFBFMIN, "HasStdExtZvfbfmin" },
{ RISCV_FEATURE_HASSTDEXTZVFBFWMA, "HasStdExtZvfbfwma" },
{ RISCV_FEATURE_HASSTDEXTZFHORZVFH, "HasStdExtZfhOrZvfh" },
{ RISCV_FEATURE_HASSTDEXTZVKB, "HasStdExtZvkb" },
{ RISCV_FEATURE_HASSTDEXTZVBB, "HasStdExtZvbb" },
{ RISCV_FEATURE_HASSTDEXTZVBC, "HasStdExtZvbc" },
{ RISCV_FEATURE_HASSTDEXTZVKG, "HasStdExtZvkg" },
{ RISCV_FEATURE_HASSTDEXTZVKNED, "HasStdExtZvkned" },
{ RISCV_FEATURE_HASSTDEXTZVKNHA, "HasStdExtZvknha" },
{ RISCV_FEATURE_HASSTDEXTZVKNHB, "HasStdExtZvknhb" },
{ RISCV_FEATURE_HASSTDEXTZVKNHAORZVKNHB, "HasStdExtZvknhaOrZvknhb" },
{ RISCV_FEATURE_HASSTDEXTZVKSED, "HasStdExtZvksed" },
{ RISCV_FEATURE_HASSTDEXTZVKSH, "HasStdExtZvksh" },
{ RISCV_FEATURE_HASVINSTRUCTIONS, "HasVInstructions" },
{ RISCV_FEATURE_HASVINSTRUCTIONSI64, "HasVInstructionsI64" },
{ RISCV_FEATURE_HASVINSTRUCTIONSANYF, "HasVInstructionsAnyF" },
{ RISCV_FEATURE_HASVINSTRUCTIONSF16MINIMAL, "HasVInstructionsF16Minimal" },
{ RISCV_FEATURE_HASSTDEXTH, "HasStdExtH" },
{ RISCV_FEATURE_HASSTDEXTSVINVAL, "HasStdExtSvinval" },
{ RISCV_FEATURE_HASVENDORXVENTANACONDOPS, "HasVendorXVentanaCondOps" },
{ RISCV_FEATURE_HASVENDORXTHEADBA, "HasVendorXTHeadBa" },
{ RISCV_FEATURE_HASVENDORXTHEADBB, "HasVendorXTHeadBb" },
{ RISCV_FEATURE_HASVENDORXTHEADBS, "HasVendorXTHeadBs" },
{ RISCV_FEATURE_HASVENDORXTHEADCONDMOV, "HasVendorXTHeadCondMov" },
{ RISCV_FEATURE_HASVENDORXTHEADCMO, "HasVendorXTHeadCmo" },
{ RISCV_FEATURE_HASVENDORXTHEADFMEMIDX, "HasVendorXTHeadFMemIdx" },
{ RISCV_FEATURE_HASVENDORXTHEADMAC, "HasVendorXTHeadMac" },
{ RISCV_FEATURE_HASVENDORXTHEADMEMIDX, "HasVendorXTHeadMemIdx" },
{ RISCV_FEATURE_HASVENDORXTHEADMEMPAIR, "HasVendorXTHeadMemPair" },
{ RISCV_FEATURE_HASVENDORXTHEADSYNC, "HasVendorXTHeadSync" },
{ RISCV_FEATURE_HASVENDORXTHEADVDOT, "HasVendorXTHeadVdot" },
{ RISCV_FEATURE_HASVENDORXSFVCP, "HasVendorXSfvcp" },
{ RISCV_FEATURE_HASVENDORXSFVQMACCDOD, "HasVendorXSfvqmaccdod" },
{ RISCV_FEATURE_HASVENDORXSFVQMACCQOQ, "HasVendorXSfvqmaccqoq" },
{ RISCV_FEATURE_HASVENDORXSFVFWMACCQQQ, "HasVendorXSfvfwmaccqqq" },
{ RISCV_FEATURE_HASVENDORXSFVFNRCLIPXFQF, "HasVendorXSfvfnrclipxfqf" },
{ RISCV_FEATURE_HASVENDORXCVELW, "HasVendorXCVelw" },
{ RISCV_FEATURE_HASVENDORXCVBITMANIP, "HasVendorXCVbitmanip" },
{ RISCV_FEATURE_HASVENDORXCVMAC, "HasVendorXCVmac" },
{ RISCV_FEATURE_HASVENDORXCVMEM, "HasVendorXCVmem" },
{ RISCV_FEATURE_HASVENDORXCVALU, "HasVendorXCValu" },
{ RISCV_FEATURE_HASVENDORXCVSIMD, "HasVendorXCVsimd" },
{ RISCV_FEATURE_HASVENDORXCVBI, "HasVendorXCVbi" },
{ RISCV_FEATURE_ISRV64, "IsRV64" },
{ RISCV_FEATURE_ISRV32, "IsRV32" },
{ RISCV_FEATURE_ISRVE, "IsRVE" },
arch/RISCV/RISCVGenCSInsnEnum.inc
+1688
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File diff suppressed because it is too large Load Diff
arch/RISCV/RISCVGenCSMappingInsn.inc
+93486
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File diff suppressed because it is too large Load Diff
arch/RISCV/RISCVGenCSMappingInsnName.inc
+1688
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File diff suppressed because it is too large Load Diff
arch/RISCV/RISCVGenCSMappingInsnOp.inc
+47133
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File diff suppressed because it is too large Load Diff
arch/RISCV/RISCVGenCSOpGroup.inc
+26
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@@ -0,0 +1,26 @@
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <[email protected]>, 2013-2022, */
/* Rot127 <[email protected]> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
RISCV_OP_GROUP_Operand = 0,
RISCV_OP_GROUP_BranchOperand = 1,
RISCV_OP_GROUP_VMaskReg = 2,
RISCV_OP_GROUP_VTypeI = 3,
RISCV_OP_GROUP_ZeroOffsetMemOp = 4,
RISCV_OP_GROUP_Rlist = 5,
RISCV_OP_GROUP_Spimm = 6,
RISCV_OP_GROUP_CSRSystemRegister = 7,
RISCV_OP_GROUP_RegReg = 8,
RISCV_OP_GROUP_FRMArg = 9,
RISCV_OP_GROUP_FRMArgLegacy = 10,
RISCV_OP_GROUP_FenceArg = 11,
RISCV_OP_GROUP_FPImmOperand = 12,
arch/RISCV/RISCVGenCSRegEnum.inc
+473
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@@ -0,0 +1,473 @@
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <[email protected]>, 2013-2022, */
/* Rot127 <[email protected]> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
RISCV_REG_INVALID = 0,
RISCV_REG_FFLAGS = 1,
RISCV_REG_FRM = 2,
RISCV_REG_SSP = 3,
RISCV_REG_VL = 4,
RISCV_REG_VLENB = 5,
RISCV_REG_VTYPE = 6,
RISCV_REG_VXRM = 7,
RISCV_REG_VXSAT = 8,
RISCV_REG_DUMMY_REG_PAIR_WITH_X0 = 9,
RISCV_REG_V0 = 10,
RISCV_REG_V1 = 11,
RISCV_REG_V2 = 12,
RISCV_REG_V3 = 13,
RISCV_REG_V4 = 14,
RISCV_REG_V5 = 15,
RISCV_REG_V6 = 16,
RISCV_REG_V7 = 17,
RISCV_REG_V8 = 18,
RISCV_REG_V9 = 19,
RISCV_REG_V10 = 20,
RISCV_REG_V11 = 21,
RISCV_REG_V12 = 22,
RISCV_REG_V13 = 23,
RISCV_REG_V14 = 24,
RISCV_REG_V15 = 25,
RISCV_REG_V16 = 26,
RISCV_REG_V17 = 27,
RISCV_REG_V18 = 28,
RISCV_REG_V19 = 29,
RISCV_REG_V20 = 30,
RISCV_REG_V21 = 31,
RISCV_REG_V22 = 32,
RISCV_REG_V23 = 33,
RISCV_REG_V24 = 34,
RISCV_REG_V25 = 35,
RISCV_REG_V26 = 36,
RISCV_REG_V27 = 37,
RISCV_REG_V28 = 38,
RISCV_REG_V29 = 39,
RISCV_REG_V30 = 40,
RISCV_REG_V31 = 41,
RISCV_REG_X0 = 42,
RISCV_REG_X1 = 43,
RISCV_REG_X2 = 44,
RISCV_REG_X3 = 45,
RISCV_REG_X4 = 46,
RISCV_REG_X5 = 47,
RISCV_REG_X6 = 48,
RISCV_REG_X7 = 49,
RISCV_REG_X8 = 50,
RISCV_REG_X9 = 51,
RISCV_REG_X10 = 52,
RISCV_REG_X11 = 53,
RISCV_REG_X12 = 54,
RISCV_REG_X13 = 55,
RISCV_REG_X14 = 56,
RISCV_REG_X15 = 57,
RISCV_REG_X16 = 58,
RISCV_REG_X17 = 59,
RISCV_REG_X18 = 60,
RISCV_REG_X19 = 61,
RISCV_REG_X20 = 62,
RISCV_REG_X21 = 63,
RISCV_REG_X22 = 64,
RISCV_REG_X23 = 65,
RISCV_REG_X24 = 66,
RISCV_REG_X25 = 67,
RISCV_REG_X26 = 68,
RISCV_REG_X27 = 69,
RISCV_REG_X28 = 70,
RISCV_REG_X29 = 71,
RISCV_REG_X30 = 72,
RISCV_REG_X31 = 73,
RISCV_REG_F0_D = 74,
RISCV_REG_F1_D = 75,
RISCV_REG_F2_D = 76,
RISCV_REG_F3_D = 77,
RISCV_REG_F4_D = 78,
RISCV_REG_F5_D = 79,
RISCV_REG_F6_D = 80,
RISCV_REG_F7_D = 81,
RISCV_REG_F8_D = 82,
RISCV_REG_F9_D = 83,
RISCV_REG_F10_D = 84,
RISCV_REG_F11_D = 85,
RISCV_REG_F12_D = 86,
RISCV_REG_F13_D = 87,
RISCV_REG_F14_D = 88,
RISCV_REG_F15_D = 89,
RISCV_REG_F16_D = 90,
RISCV_REG_F17_D = 91,
RISCV_REG_F18_D = 92,
RISCV_REG_F19_D = 93,
RISCV_REG_F20_D = 94,
RISCV_REG_F21_D = 95,
RISCV_REG_F22_D = 96,
RISCV_REG_F23_D = 97,
RISCV_REG_F24_D = 98,
RISCV_REG_F25_D = 99,
RISCV_REG_F26_D = 100,
RISCV_REG_F27_D = 101,
RISCV_REG_F28_D = 102,
RISCV_REG_F29_D = 103,
RISCV_REG_F30_D = 104,
RISCV_REG_F31_D = 105,
RISCV_REG_F0_F = 106,
RISCV_REG_F1_F = 107,
RISCV_REG_F2_F = 108,
RISCV_REG_F3_F = 109,
RISCV_REG_F4_F = 110,
RISCV_REG_F5_F = 111,
RISCV_REG_F6_F = 112,
RISCV_REG_F7_F = 113,
RISCV_REG_F8_F = 114,
RISCV_REG_F9_F = 115,
RISCV_REG_F10_F = 116,
RISCV_REG_F11_F = 117,
RISCV_REG_F12_F = 118,
RISCV_REG_F13_F = 119,
RISCV_REG_F14_F = 120,
RISCV_REG_F15_F = 121,
RISCV_REG_F16_F = 122,
RISCV_REG_F17_F = 123,
RISCV_REG_F18_F = 124,
RISCV_REG_F19_F = 125,
RISCV_REG_F20_F = 126,
RISCV_REG_F21_F = 127,
RISCV_REG_F22_F = 128,
RISCV_REG_F23_F = 129,
RISCV_REG_F24_F = 130,
RISCV_REG_F25_F = 131,
RISCV_REG_F26_F = 132,
RISCV_REG_F27_F = 133,
RISCV_REG_F28_F = 134,
RISCV_REG_F29_F = 135,
RISCV_REG_F30_F = 136,
RISCV_REG_F31_F = 137,
RISCV_REG_F0_H = 138,
RISCV_REG_F1_H = 139,
RISCV_REG_F2_H = 140,
RISCV_REG_F3_H = 141,
RISCV_REG_F4_H = 142,
RISCV_REG_F5_H = 143,
RISCV_REG_F6_H = 144,
RISCV_REG_F7_H = 145,
RISCV_REG_F8_H = 146,
RISCV_REG_F9_H = 147,
RISCV_REG_F10_H = 148,
RISCV_REG_F11_H = 149,
RISCV_REG_F12_H = 150,
RISCV_REG_F13_H = 151,
RISCV_REG_F14_H = 152,
RISCV_REG_F15_H = 153,
RISCV_REG_F16_H = 154,
RISCV_REG_F17_H = 155,
RISCV_REG_F18_H = 156,
RISCV_REG_F19_H = 157,
RISCV_REG_F20_H = 158,
RISCV_REG_F21_H = 159,
RISCV_REG_F22_H = 160,
RISCV_REG_F23_H = 161,
RISCV_REG_F24_H = 162,
RISCV_REG_F25_H = 163,
RISCV_REG_F26_H = 164,
RISCV_REG_F27_H = 165,
RISCV_REG_F28_H = 166,
RISCV_REG_F29_H = 167,
RISCV_REG_F30_H = 168,
RISCV_REG_F31_H = 169,
RISCV_REG_X0_PAIR = 170,
RISCV_REG_V0M2 = 171,
RISCV_REG_V0M4 = 172,
RISCV_REG_V0M8 = 173,
RISCV_REG_V2M2 = 174,
RISCV_REG_V4M2 = 175,
RISCV_REG_V4M4 = 176,
RISCV_REG_V6M2 = 177,
RISCV_REG_V8M2 = 178,
RISCV_REG_V8M4 = 179,
RISCV_REG_V8M8 = 180,
RISCV_REG_V10M2 = 181,
RISCV_REG_V12M2 = 182,
RISCV_REG_V12M4 = 183,
RISCV_REG_V14M2 = 184,
RISCV_REG_V16M2 = 185,
RISCV_REG_V16M4 = 186,
RISCV_REG_V16M8 = 187,
RISCV_REG_V18M2 = 188,
RISCV_REG_V20M2 = 189,
RISCV_REG_V20M4 = 190,
RISCV_REG_V22M2 = 191,
RISCV_REG_V24M2 = 192,
RISCV_REG_V24M4 = 193,
RISCV_REG_V24M8 = 194,
RISCV_REG_V26M2 = 195,
RISCV_REG_V28M2 = 196,
RISCV_REG_V28M4 = 197,
RISCV_REG_V30M2 = 198,
RISCV_REG_X2_X3 = 199,
RISCV_REG_X4_X5 = 200,
RISCV_REG_X6_X7 = 201,
RISCV_REG_X8_X9 = 202,
RISCV_REG_X10_X11 = 203,
RISCV_REG_X12_X13 = 204,
RISCV_REG_X14_X15 = 205,
RISCV_REG_X16_X17 = 206,
RISCV_REG_X18_X19 = 207,
RISCV_REG_X20_X21 = 208,
RISCV_REG_X22_X23 = 209,
RISCV_REG_X24_X25 = 210,
RISCV_REG_X26_X27 = 211,
RISCV_REG_X28_X29 = 212,
RISCV_REG_X30_X31 = 213,
RISCV_REG_V1_V2 = 214,
RISCV_REG_V2_V3 = 215,
RISCV_REG_V3_V4 = 216,
RISCV_REG_V4_V5 = 217,
RISCV_REG_V5_V6 = 218,
RISCV_REG_V6_V7 = 219,
RISCV_REG_V7_V8 = 220,
RISCV_REG_V8_V9 = 221,
RISCV_REG_V9_V10 = 222,
RISCV_REG_V10_V11 = 223,
RISCV_REG_V11_V12 = 224,
RISCV_REG_V12_V13 = 225,
RISCV_REG_V13_V14 = 226,
RISCV_REG_V14_V15 = 227,
RISCV_REG_V15_V16 = 228,
RISCV_REG_V16_V17 = 229,
RISCV_REG_V17_V18 = 230,
RISCV_REG_V18_V19 = 231,
RISCV_REG_V19_V20 = 232,
RISCV_REG_V20_V21 = 233,
RISCV_REG_V21_V22 = 234,
RISCV_REG_V22_V23 = 235,
RISCV_REG_V23_V24 = 236,
RISCV_REG_V24_V25 = 237,
RISCV_REG_V25_V26 = 238,
RISCV_REG_V26_V27 = 239,
RISCV_REG_V27_V28 = 240,
RISCV_REG_V28_V29 = 241,
RISCV_REG_V29_V30 = 242,
RISCV_REG_V30_V31 = 243,
RISCV_REG_V0_V1 = 244,
RISCV_REG_V2M2_V4M2 = 245,
RISCV_REG_V4M2_V6M2 = 246,
RISCV_REG_V6M2_V8M2 = 247,
RISCV_REG_V8M2_V10M2 = 248,
RISCV_REG_V10M2_V12M2 = 249,
RISCV_REG_V12M2_V14M2 = 250,
RISCV_REG_V14M2_V16M2 = 251,
RISCV_REG_V16M2_V18M2 = 252,
RISCV_REG_V18M2_V20M2 = 253,
RISCV_REG_V20M2_V22M2 = 254,
RISCV_REG_V22M2_V24M2 = 255,
RISCV_REG_V24M2_V26M2 = 256,
RISCV_REG_V26M2_V28M2 = 257,
RISCV_REG_V28M2_V30M2 = 258,
RISCV_REG_V0M2_V2M2 = 259,
RISCV_REG_V4M4_V8M4 = 260,
RISCV_REG_V8M4_V12M4 = 261,
RISCV_REG_V12M4_V16M4 = 262,
RISCV_REG_V16M4_V20M4 = 263,
RISCV_REG_V20M4_V24M4 = 264,
RISCV_REG_V24M4_V28M4 = 265,
RISCV_REG_V0M4_V4M4 = 266,
RISCV_REG_V1_V2_V3 = 267,
RISCV_REG_V2_V3_V4 = 268,
RISCV_REG_V3_V4_V5 = 269,
RISCV_REG_V4_V5_V6 = 270,
RISCV_REG_V5_V6_V7 = 271,
RISCV_REG_V6_V7_V8 = 272,
RISCV_REG_V7_V8_V9 = 273,
RISCV_REG_V8_V9_V10 = 274,
RISCV_REG_V9_V10_V11 = 275,
RISCV_REG_V10_V11_V12 = 276,
RISCV_REG_V11_V12_V13 = 277,
RISCV_REG_V12_V13_V14 = 278,
RISCV_REG_V13_V14_V15 = 279,
RISCV_REG_V14_V15_V16 = 280,
RISCV_REG_V15_V16_V17 = 281,
RISCV_REG_V16_V17_V18 = 282,
RISCV_REG_V17_V18_V19 = 283,
RISCV_REG_V18_V19_V20 = 284,
RISCV_REG_V19_V20_V21 = 285,
RISCV_REG_V20_V21_V22 = 286,
RISCV_REG_V21_V22_V23 = 287,
RISCV_REG_V22_V23_V24 = 288,
RISCV_REG_V23_V24_V25 = 289,
RISCV_REG_V24_V25_V26 = 290,
RISCV_REG_V25_V26_V27 = 291,
RISCV_REG_V26_V27_V28 = 292,
RISCV_REG_V27_V28_V29 = 293,
RISCV_REG_V28_V29_V30 = 294,
RISCV_REG_V29_V30_V31 = 295,
RISCV_REG_V0_V1_V2 = 296,
RISCV_REG_V2M2_V4M2_V6M2 = 297,
RISCV_REG_V4M2_V6M2_V8M2 = 298,
RISCV_REG_V6M2_V8M2_V10M2 = 299,
RISCV_REG_V8M2_V10M2_V12M2 = 300,
RISCV_REG_V10M2_V12M2_V14M2 = 301,
RISCV_REG_V12M2_V14M2_V16M2 = 302,
RISCV_REG_V14M2_V16M2_V18M2 = 303,
RISCV_REG_V16M2_V18M2_V20M2 = 304,
RISCV_REG_V18M2_V20M2_V22M2 = 305,
RISCV_REG_V20M2_V22M2_V24M2 = 306,
RISCV_REG_V22M2_V24M2_V26M2 = 307,
RISCV_REG_V24M2_V26M2_V28M2 = 308,
RISCV_REG_V26M2_V28M2_V30M2 = 309,
RISCV_REG_V0M2_V2M2_V4M2 = 310,
RISCV_REG_V1_V2_V3_V4 = 311,
RISCV_REG_V2_V3_V4_V5 = 312,
RISCV_REG_V3_V4_V5_V6 = 313,
RISCV_REG_V4_V5_V6_V7 = 314,
RISCV_REG_V5_V6_V7_V8 = 315,
RISCV_REG_V6_V7_V8_V9 = 316,
RISCV_REG_V7_V8_V9_V10 = 317,
RISCV_REG_V8_V9_V10_V11 = 318,
RISCV_REG_V9_V10_V11_V12 = 319,
RISCV_REG_V10_V11_V12_V13 = 320,
RISCV_REG_V11_V12_V13_V14 = 321,
RISCV_REG_V12_V13_V14_V15 = 322,
RISCV_REG_V13_V14_V15_V16 = 323,
RISCV_REG_V14_V15_V16_V17 = 324,
RISCV_REG_V15_V16_V17_V18 = 325,
RISCV_REG_V16_V17_V18_V19 = 326,
RISCV_REG_V17_V18_V19_V20 = 327,
RISCV_REG_V18_V19_V20_V21 = 328,
RISCV_REG_V19_V20_V21_V22 = 329,
RISCV_REG_V20_V21_V22_V23 = 330,
RISCV_REG_V21_V22_V23_V24 = 331,
RISCV_REG_V22_V23_V24_V25 = 332,
RISCV_REG_V23_V24_V25_V26 = 333,
RISCV_REG_V24_V25_V26_V27 = 334,
RISCV_REG_V25_V26_V27_V28 = 335,
RISCV_REG_V26_V27_V28_V29 = 336,
RISCV_REG_V27_V28_V29_V30 = 337,
RISCV_REG_V28_V29_V30_V31 = 338,
RISCV_REG_V0_V1_V2_V3 = 339,
RISCV_REG_V2M2_V4M2_V6M2_V8M2 = 340,
RISCV_REG_V4M2_V6M2_V8M2_V10M2 = 341,
RISCV_REG_V6M2_V8M2_V10M2_V12M2 = 342,
RISCV_REG_V8M2_V10M2_V12M2_V14M2 = 343,
RISCV_REG_V10M2_V12M2_V14M2_V16M2 = 344,
RISCV_REG_V12M2_V14M2_V16M2_V18M2 = 345,
RISCV_REG_V14M2_V16M2_V18M2_V20M2 = 346,
RISCV_REG_V16M2_V18M2_V20M2_V22M2 = 347,
RISCV_REG_V18M2_V20M2_V22M2_V24M2 = 348,
RISCV_REG_V20M2_V22M2_V24M2_V26M2 = 349,
RISCV_REG_V22M2_V24M2_V26M2_V28M2 = 350,
RISCV_REG_V24M2_V26M2_V28M2_V30M2 = 351,
RISCV_REG_V0M2_V2M2_V4M2_V6M2 = 352,
RISCV_REG_V1_V2_V3_V4_V5 = 353,
RISCV_REG_V2_V3_V4_V5_V6 = 354,
RISCV_REG_V3_V4_V5_V6_V7 = 355,
RISCV_REG_V4_V5_V6_V7_V8 = 356,
RISCV_REG_V5_V6_V7_V8_V9 = 357,
RISCV_REG_V6_V7_V8_V9_V10 = 358,
RISCV_REG_V7_V8_V9_V10_V11 = 359,
RISCV_REG_V8_V9_V10_V11_V12 = 360,
RISCV_REG_V9_V10_V11_V12_V13 = 361,
RISCV_REG_V10_V11_V12_V13_V14 = 362,
RISCV_REG_V11_V12_V13_V14_V15 = 363,
RISCV_REG_V12_V13_V14_V15_V16 = 364,
RISCV_REG_V13_V14_V15_V16_V17 = 365,
RISCV_REG_V14_V15_V16_V17_V18 = 366,
RISCV_REG_V15_V16_V17_V18_V19 = 367,
RISCV_REG_V16_V17_V18_V19_V20 = 368,
RISCV_REG_V17_V18_V19_V20_V21 = 369,
RISCV_REG_V18_V19_V20_V21_V22 = 370,
RISCV_REG_V19_V20_V21_V22_V23 = 371,
RISCV_REG_V20_V21_V22_V23_V24 = 372,
RISCV_REG_V21_V22_V23_V24_V25 = 373,
RISCV_REG_V22_V23_V24_V25_V26 = 374,
RISCV_REG_V23_V24_V25_V26_V27 = 375,
RISCV_REG_V24_V25_V26_V27_V28 = 376,
RISCV_REG_V25_V26_V27_V28_V29 = 377,
RISCV_REG_V26_V27_V28_V29_V30 = 378,
RISCV_REG_V27_V28_V29_V30_V31 = 379,
RISCV_REG_V0_V1_V2_V3_V4 = 380,
RISCV_REG_V1_V2_V3_V4_V5_V6 = 381,
RISCV_REG_V2_V3_V4_V5_V6_V7 = 382,
RISCV_REG_V3_V4_V5_V6_V7_V8 = 383,
RISCV_REG_V4_V5_V6_V7_V8_V9 = 384,
RISCV_REG_V5_V6_V7_V8_V9_V10 = 385,
RISCV_REG_V6_V7_V8_V9_V10_V11 = 386,
RISCV_REG_V7_V8_V9_V10_V11_V12 = 387,
RISCV_REG_V8_V9_V10_V11_V12_V13 = 388,
RISCV_REG_V9_V10_V11_V12_V13_V14 = 389,
RISCV_REG_V10_V11_V12_V13_V14_V15 = 390,
RISCV_REG_V11_V12_V13_V14_V15_V16 = 391,
RISCV_REG_V12_V13_V14_V15_V16_V17 = 392,
RISCV_REG_V13_V14_V15_V16_V17_V18 = 393,
RISCV_REG_V14_V15_V16_V17_V18_V19 = 394,
RISCV_REG_V15_V16_V17_V18_V19_V20 = 395,
RISCV_REG_V16_V17_V18_V19_V20_V21 = 396,
RISCV_REG_V17_V18_V19_V20_V21_V22 = 397,
RISCV_REG_V18_V19_V20_V21_V22_V23 = 398,
RISCV_REG_V19_V20_V21_V22_V23_V24 = 399,
RISCV_REG_V20_V21_V22_V23_V24_V25 = 400,
RISCV_REG_V21_V22_V23_V24_V25_V26 = 401,
RISCV_REG_V22_V23_V24_V25_V26_V27 = 402,
RISCV_REG_V23_V24_V25_V26_V27_V28 = 403,
RISCV_REG_V24_V25_V26_V27_V28_V29 = 404,
RISCV_REG_V25_V26_V27_V28_V29_V30 = 405,
RISCV_REG_V26_V27_V28_V29_V30_V31 = 406,
RISCV_REG_V0_V1_V2_V3_V4_V5 = 407,
RISCV_REG_V1_V2_V3_V4_V5_V6_V7 = 408,
RISCV_REG_V2_V3_V4_V5_V6_V7_V8 = 409,
RISCV_REG_V3_V4_V5_V6_V7_V8_V9 = 410,
RISCV_REG_V4_V5_V6_V7_V8_V9_V10 = 411,
RISCV_REG_V5_V6_V7_V8_V9_V10_V11 = 412,
RISCV_REG_V6_V7_V8_V9_V10_V11_V12 = 413,
RISCV_REG_V7_V8_V9_V10_V11_V12_V13 = 414,
RISCV_REG_V8_V9_V10_V11_V12_V13_V14 = 415,
RISCV_REG_V9_V10_V11_V12_V13_V14_V15 = 416,
RISCV_REG_V10_V11_V12_V13_V14_V15_V16 = 417,
RISCV_REG_V11_V12_V13_V14_V15_V16_V17 = 418,
RISCV_REG_V12_V13_V14_V15_V16_V17_V18 = 419,
RISCV_REG_V13_V14_V15_V16_V17_V18_V19 = 420,
RISCV_REG_V14_V15_V16_V17_V18_V19_V20 = 421,
RISCV_REG_V15_V16_V17_V18_V19_V20_V21 = 422,
RISCV_REG_V16_V17_V18_V19_V20_V21_V22 = 423,
RISCV_REG_V17_V18_V19_V20_V21_V22_V23 = 424,
RISCV_REG_V18_V19_V20_V21_V22_V23_V24 = 425,
RISCV_REG_V19_V20_V21_V22_V23_V24_V25 = 426,
RISCV_REG_V20_V21_V22_V23_V24_V25_V26 = 427,
RISCV_REG_V21_V22_V23_V24_V25_V26_V27 = 428,
RISCV_REG_V22_V23_V24_V25_V26_V27_V28 = 429,
RISCV_REG_V23_V24_V25_V26_V27_V28_V29 = 430,
RISCV_REG_V24_V25_V26_V27_V28_V29_V30 = 431,
RISCV_REG_V25_V26_V27_V28_V29_V30_V31 = 432,
RISCV_REG_V0_V1_V2_V3_V4_V5_V6 = 433,
RISCV_REG_V1_V2_V3_V4_V5_V6_V7_V8 = 434,
RISCV_REG_V2_V3_V4_V5_V6_V7_V8_V9 = 435,
RISCV_REG_V3_V4_V5_V6_V7_V8_V9_V10 = 436,
RISCV_REG_V4_V5_V6_V7_V8_V9_V10_V11 = 437,
RISCV_REG_V5_V6_V7_V8_V9_V10_V11_V12 = 438,
RISCV_REG_V6_V7_V8_V9_V10_V11_V12_V13 = 439,
RISCV_REG_V7_V8_V9_V10_V11_V12_V13_V14 = 440,
RISCV_REG_V8_V9_V10_V11_V12_V13_V14_V15 = 441,
RISCV_REG_V9_V10_V11_V12_V13_V14_V15_V16 = 442,
RISCV_REG_V10_V11_V12_V13_V14_V15_V16_V17 = 443,
RISCV_REG_V11_V12_V13_V14_V15_V16_V17_V18 = 444,
RISCV_REG_V12_V13_V14_V15_V16_V17_V18_V19 = 445,
RISCV_REG_V13_V14_V15_V16_V17_V18_V19_V20 = 446,
RISCV_REG_V14_V15_V16_V17_V18_V19_V20_V21 = 447,
RISCV_REG_V15_V16_V17_V18_V19_V20_V21_V22 = 448,
RISCV_REG_V16_V17_V18_V19_V20_V21_V22_V23 = 449,
RISCV_REG_V17_V18_V19_V20_V21_V22_V23_V24 = 450,
RISCV_REG_V18_V19_V20_V21_V22_V23_V24_V25 = 451,
RISCV_REG_V19_V20_V21_V22_V23_V24_V25_V26 = 452,
RISCV_REG_V20_V21_V22_V23_V24_V25_V26_V27 = 453,
RISCV_REG_V21_V22_V23_V24_V25_V26_V27_V28 = 454,
RISCV_REG_V22_V23_V24_V25_V26_V27_V28_V29 = 455,
RISCV_REG_V23_V24_V25_V26_V27_V28_V29_V30 = 456,
RISCV_REG_V24_V25_V26_V27_V28_V29_V30_V31 = 457,
RISCV_REG_V0_V1_V2_V3_V4_V5_V6_V7 = 458,
RISCV_REG_ENDING, // 459
arch/RISCV/RISCVGenCSSystemOperandsEnum.inc
+510
View File
@@ -0,0 +1,510 @@
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <[email protected]>, 2013-2022, */
/* Rot127 <[email protected]> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
#ifdef GET_ENUM_VALUES_RISCVMaskedPseudoInfo
#undef GET_ENUM_VALUES_RISCVMaskedPseudoInfo
#endif
#ifdef GET_ENUM_VALUES_RISCVOpcode
#undef GET_ENUM_VALUES_RISCVOpcode
RISCV_RISCVOPCODE_LOAD = 0x3,
RISCV_RISCVOPCODE_LOAD_FP = 0x7,
RISCV_RISCVOPCODE_CUSTOM_0 = 0xb,
RISCV_RISCVOPCODE_MISC_MEM = 0xf,
RISCV_RISCVOPCODE_OP_IMM = 0x13,
RISCV_RISCVOPCODE_AUIPC = 0x17,
RISCV_RISCVOPCODE_OP_IMM_32 = 0x1b,
RISCV_RISCVOPCODE_STORE = 0x23,
RISCV_RISCVOPCODE_STORE_FP = 0x27,
RISCV_RISCVOPCODE_CUSTOM_1 = 0x2b,
RISCV_RISCVOPCODE_AMO = 0x2f,
RISCV_RISCVOPCODE_OP = 0x33,
RISCV_RISCVOPCODE_LUI = 0x37,
RISCV_RISCVOPCODE_OP_32 = 0x3b,
RISCV_RISCVOPCODE_MADD = 0x43,
RISCV_RISCVOPCODE_MSUB = 0x47,
RISCV_RISCVOPCODE_NMSUB = 0x4b,
RISCV_RISCVOPCODE_NMADD = 0x4f,
RISCV_RISCVOPCODE_OP_FP = 0x53,
RISCV_RISCVOPCODE_OP_V = 0x57,
RISCV_RISCVOPCODE_CUSTOM_2 = 0x5b,
RISCV_RISCVOPCODE_BRANCH = 0x63,
RISCV_RISCVOPCODE_JALR = 0x67,
RISCV_RISCVOPCODE_JAL = 0x6f,
RISCV_RISCVOPCODE_SYSTEM = 0x73,
RISCV_RISCVOPCODE_OP_P = 0x77,
RISCV_RISCVOPCODE_CUSTOM_3 = 0x7b,
#endif
#ifdef GET_ENUM_VALUES_RISCVTuneInfo
#undef GET_ENUM_VALUES_RISCVTuneInfo
RISCV_RISCVTUNEINFO_GENERIC = 0x0,
RISCV_RISCVTUNEINFO_GENERIC-RV32 = 0x0,
RISCV_RISCVTUNEINFO_GENERIC-RV64 = 0x0,
#endif
#ifdef GET_ENUM_VALUES_RISCVVIntrinsicInfo
#undef GET_ENUM_VALUES_RISCVVIntrinsicInfo
#endif
#ifdef GET_ENUM_VALUES_PseudoInfo
#undef GET_ENUM_VALUES_PseudoInfo
#endif
#ifdef GET_ENUM_VALUES_VLEPseudo
#undef GET_ENUM_VALUES_VLEPseudo
#endif
#ifdef GET_ENUM_VALUES_VLSEGPseudo
#undef GET_ENUM_VALUES_VLSEGPseudo
#endif
#ifdef GET_ENUM_VALUES_VLXSEGPseudo
#undef GET_ENUM_VALUES_VLXSEGPseudo
#endif
#ifdef GET_ENUM_VALUES_VLX_VSXPseudo
#undef GET_ENUM_VALUES_VLX_VSXPseudo
#endif
#ifdef GET_ENUM_VALUES_PseudoInfo
#undef GET_ENUM_VALUES_PseudoInfo
#endif
#ifdef GET_ENUM_VALUES_VSEPseudo
#undef GET_ENUM_VALUES_VSEPseudo
#endif
#ifdef GET_ENUM_VALUES_VSSEGPseudo
#undef GET_ENUM_VALUES_VSSEGPseudo
#endif
#ifdef GET_ENUM_VALUES_VSXSEGPseudo
#undef GET_ENUM_VALUES_VSXSEGPseudo
#endif
#ifdef GET_ENUM_VALUES_VLX_VSXPseudo
#undef GET_ENUM_VALUES_VLX_VSXPseudo
#endif
#ifdef GET_ENUM_VALUES_SysReg
#undef GET_ENUM_VALUES_SysReg
RISCV_SYSREG_FFLAGS = 0x1,
RISCV_SYSREG_FRM = 0x2,
RISCV_SYSREG_FCSR = 0x3,
RISCV_SYSREG_VSTART = 0x8,
RISCV_SYSREG_VXSAT = 0x9,
RISCV_SYSREG_VXRM = 0xa,
RISCV_SYSREG_VCSR = 0xf,
RISCV_SYSREG_SEED = 0x15,
RISCV_SYSREG_JVT = 0x17,
RISCV_SYSREG_SSTATUS = 0x100,
RISCV_SYSREG_SIE = 0x104,
RISCV_SYSREG_STVEC = 0x105,
RISCV_SYSREG_SCOUNTEREN = 0x106,
RISCV_SYSREG_SENVCFG = 0x10a,
RISCV_SYSREG_SSTATEEN0 = 0x10c,
RISCV_SYSREG_SSTATEEN1 = 0x10d,
RISCV_SYSREG_SSTATEEN2 = 0x10e,
RISCV_SYSREG_SSTATEEN3 = 0x10f,
RISCV_SYSREG_SIEH = 0x114,
RISCV_SYSREG_SSCRATCH = 0x140,
RISCV_SYSREG_SEPC = 0x141,
RISCV_SYSREG_SCAUSE = 0x142,
RISCV_SYSREG_STVAL = 0x143,
RISCV_SYSREG_SIP = 0x144,
RISCV_SYSREG_STIMECMP = 0x14d,
RISCV_SYSREG_SISELECT = 0x150,
RISCV_SYSREG_SIREG = 0x151,
RISCV_SYSREG_SIPH = 0x154,
RISCV_SYSREG_STOPEI = 0x15c,
RISCV_SYSREG_STIMECMPH = 0x15d,
RISCV_SYSREG_SATP = 0x180,
RISCV_SYSREG_VSSTATUS = 0x200,
RISCV_SYSREG_VSIE = 0x204,
RISCV_SYSREG_VSTVEC = 0x205,
RISCV_SYSREG_VSIEH = 0x214,
RISCV_SYSREG_VSSCRATCH = 0x240,
RISCV_SYSREG_VSEPC = 0x241,
RISCV_SYSREG_VSCAUSE = 0x242,
RISCV_SYSREG_VSTVAL = 0x243,
RISCV_SYSREG_VSIP = 0x244,
RISCV_SYSREG_VSTIMECMP = 0x24d,
RISCV_SYSREG_VSISELECT = 0x250,
RISCV_SYSREG_VSIREG = 0x251,
RISCV_SYSREG_VSIPH = 0x254,
RISCV_SYSREG_VSTOPEI = 0x25c,
RISCV_SYSREG_VSTIMECMPH = 0x25d,
RISCV_SYSREG_VSATP = 0x280,
RISCV_SYSREG_MSTATUS = 0x300,
RISCV_SYSREG_MISA = 0x301,
RISCV_SYSREG_MEDELEG = 0x302,
RISCV_SYSREG_MIDELEG = 0x303,
RISCV_SYSREG_MIE = 0x304,
RISCV_SYSREG_MTVEC = 0x305,
RISCV_SYSREG_MCOUNTEREN = 0x306,
RISCV_SYSREG_MVIEN = 0x308,
RISCV_SYSREG_MVIP = 0x309,
RISCV_SYSREG_MENVCFG = 0x30a,
RISCV_SYSREG_MSTATEEN0 = 0x30c,
RISCV_SYSREG_MSTATEEN1 = 0x30d,
RISCV_SYSREG_MSTATEEN2 = 0x30e,
RISCV_SYSREG_MSTATEEN3 = 0x30f,
RISCV_SYSREG_MSTATUSH = 0x310,
RISCV_SYSREG_MIDELEGH = 0x313,
RISCV_SYSREG_MIEH = 0x314,
RISCV_SYSREG_MVIENH = 0x318,
RISCV_SYSREG_MVIPH = 0x319,
RISCV_SYSREG_MENVCFGH = 0x31a,
RISCV_SYSREG_MSTATEEN0H = 0x31c,
RISCV_SYSREG_MSTATEEN1H = 0x31d,
RISCV_SYSREG_MSTATEEN2H = 0x31e,
RISCV_SYSREG_MSTATEEN3H = 0x31f,
RISCV_SYSREG_MCOUNTINHIBIT = 0x320,
RISCV_SYSREG_MUCOUNTEREN = 0x320,
RISCV_SYSREG_MHPMEVENT3 = 0x323,
RISCV_SYSREG_MHPMEVENT4 = 0x324,
RISCV_SYSREG_MHPMEVENT5 = 0x325,
RISCV_SYSREG_MHPMEVENT6 = 0x326,
RISCV_SYSREG_MHPMEVENT7 = 0x327,
RISCV_SYSREG_MHPMEVENT8 = 0x328,
RISCV_SYSREG_MHPMEVENT9 = 0x329,
RISCV_SYSREG_MHPMEVENT10 = 0x32a,
RISCV_SYSREG_MHPMEVENT11 = 0x32b,
RISCV_SYSREG_MHPMEVENT12 = 0x32c,
RISCV_SYSREG_MHPMEVENT13 = 0x32d,
RISCV_SYSREG_MHPMEVENT14 = 0x32e,
RISCV_SYSREG_MHPMEVENT15 = 0x32f,
RISCV_SYSREG_MHPMEVENT16 = 0x330,
RISCV_SYSREG_MHPMEVENT17 = 0x331,
RISCV_SYSREG_MHPMEVENT18 = 0x332,
RISCV_SYSREG_MHPMEVENT19 = 0x333,
RISCV_SYSREG_MHPMEVENT20 = 0x334,
RISCV_SYSREG_MHPMEVENT21 = 0x335,
RISCV_SYSREG_MHPMEVENT22 = 0x336,
RISCV_SYSREG_MHPMEVENT23 = 0x337,
RISCV_SYSREG_MHPMEVENT24 = 0x338,
RISCV_SYSREG_MHPMEVENT25 = 0x339,
RISCV_SYSREG_MHPMEVENT26 = 0x33a,
RISCV_SYSREG_MHPMEVENT27 = 0x33b,
RISCV_SYSREG_MHPMEVENT28 = 0x33c,
RISCV_SYSREG_MHPMEVENT29 = 0x33d,
RISCV_SYSREG_MHPMEVENT30 = 0x33e,
RISCV_SYSREG_MHPMEVENT31 = 0x33f,
RISCV_SYSREG_MSCRATCH = 0x340,
RISCV_SYSREG_MEPC = 0x341,
RISCV_SYSREG_MCAUSE = 0x342,
RISCV_SYSREG_MTVAL = 0x343,
RISCV_SYSREG_MIP = 0x344,
RISCV_SYSREG_MTINST = 0x34a,
RISCV_SYSREG_MTVAL2 = 0x34b,
RISCV_SYSREG_MISELECT = 0x350,
RISCV_SYSREG_MIREG = 0x351,
RISCV_SYSREG_MIPH = 0x354,
RISCV_SYSREG_MTOPEI = 0x35c,
RISCV_SYSREG_PMPCFG0 = 0x3a0,
RISCV_SYSREG_PMPCFG1 = 0x3a1,
RISCV_SYSREG_PMPCFG2 = 0x3a2,
RISCV_SYSREG_PMPCFG3 = 0x3a3,
RISCV_SYSREG_PMPCFG4 = 0x3a4,
RISCV_SYSREG_PMPCFG5 = 0x3a5,
RISCV_SYSREG_PMPCFG6 = 0x3a6,
RISCV_SYSREG_PMPCFG7 = 0x3a7,
RISCV_SYSREG_PMPCFG8 = 0x3a8,
RISCV_SYSREG_PMPCFG9 = 0x3a9,
RISCV_SYSREG_PMPCFG10 = 0x3aa,
RISCV_SYSREG_PMPCFG11 = 0x3ab,
RISCV_SYSREG_PMPCFG12 = 0x3ac,
RISCV_SYSREG_PMPCFG13 = 0x3ad,
RISCV_SYSREG_PMPCFG14 = 0x3ae,
RISCV_SYSREG_PMPCFG15 = 0x3af,
RISCV_SYSREG_PMPADDR0 = 0x3b0,
RISCV_SYSREG_PMPADDR1 = 0x3b1,
RISCV_SYSREG_PMPADDR2 = 0x3b2,
RISCV_SYSREG_PMPADDR3 = 0x3b3,
RISCV_SYSREG_PMPADDR4 = 0x3b4,
RISCV_SYSREG_PMPADDR5 = 0x3b5,
RISCV_SYSREG_PMPADDR6 = 0x3b6,
RISCV_SYSREG_PMPADDR7 = 0x3b7,
RISCV_SYSREG_PMPADDR8 = 0x3b8,
RISCV_SYSREG_PMPADDR9 = 0x3b9,
RISCV_SYSREG_PMPADDR10 = 0x3ba,
RISCV_SYSREG_PMPADDR11 = 0x3bb,
RISCV_SYSREG_PMPADDR12 = 0x3bc,
RISCV_SYSREG_PMPADDR13 = 0x3bd,
RISCV_SYSREG_PMPADDR14 = 0x3be,
RISCV_SYSREG_PMPADDR15 = 0x3bf,
RISCV_SYSREG_PMPADDR16 = 0x3c0,
RISCV_SYSREG_PMPADDR17 = 0x3c1,
RISCV_SYSREG_PMPADDR18 = 0x3c2,
RISCV_SYSREG_PMPADDR19 = 0x3c3,
RISCV_SYSREG_PMPADDR20 = 0x3c4,
RISCV_SYSREG_PMPADDR21 = 0x3c5,
RISCV_SYSREG_PMPADDR22 = 0x3c6,
RISCV_SYSREG_PMPADDR23 = 0x3c7,
RISCV_SYSREG_PMPADDR24 = 0x3c8,
RISCV_SYSREG_PMPADDR25 = 0x3c9,
RISCV_SYSREG_PMPADDR26 = 0x3ca,
RISCV_SYSREG_PMPADDR27 = 0x3cb,
RISCV_SYSREG_PMPADDR28 = 0x3cc,
RISCV_SYSREG_PMPADDR29 = 0x3cd,
RISCV_SYSREG_PMPADDR30 = 0x3ce,
RISCV_SYSREG_PMPADDR31 = 0x3cf,
RISCV_SYSREG_PMPADDR32 = 0x3d0,
RISCV_SYSREG_PMPADDR33 = 0x3d1,
RISCV_SYSREG_PMPADDR34 = 0x3d2,
RISCV_SYSREG_PMPADDR35 = 0x3d3,
RISCV_SYSREG_PMPADDR36 = 0x3d4,
RISCV_SYSREG_PMPADDR37 = 0x3d5,
RISCV_SYSREG_PMPADDR38 = 0x3d6,
RISCV_SYSREG_PMPADDR39 = 0x3d7,
RISCV_SYSREG_PMPADDR40 = 0x3d8,
RISCV_SYSREG_PMPADDR41 = 0x3d9,
RISCV_SYSREG_PMPADDR42 = 0x3da,
RISCV_SYSREG_PMPADDR43 = 0x3db,
RISCV_SYSREG_PMPADDR44 = 0x3dc,
RISCV_SYSREG_PMPADDR45 = 0x3dd,
RISCV_SYSREG_PMPADDR46 = 0x3de,
RISCV_SYSREG_PMPADDR47 = 0x3df,
RISCV_SYSREG_PMPADDR48 = 0x3e0,
RISCV_SYSREG_PMPADDR49 = 0x3e1,
RISCV_SYSREG_PMPADDR50 = 0x3e2,
RISCV_SYSREG_PMPADDR51 = 0x3e3,
RISCV_SYSREG_PMPADDR52 = 0x3e4,
RISCV_SYSREG_PMPADDR53 = 0x3e5,
RISCV_SYSREG_PMPADDR54 = 0x3e6,
RISCV_SYSREG_PMPADDR55 = 0x3e7,
RISCV_SYSREG_PMPADDR56 = 0x3e8,
RISCV_SYSREG_PMPADDR57 = 0x3e9,
RISCV_SYSREG_PMPADDR58 = 0x3ea,
RISCV_SYSREG_PMPADDR59 = 0x3eb,
RISCV_SYSREG_PMPADDR60 = 0x3ec,
RISCV_SYSREG_PMPADDR61 = 0x3ed,
RISCV_SYSREG_PMPADDR62 = 0x3ee,
RISCV_SYSREG_PMPADDR63 = 0x3ef,
RISCV_SYSREG_SCONTEXT = 0x5a8,
RISCV_SYSREG_HSTATUS = 0x600,
RISCV_SYSREG_HEDELEG = 0x602,
RISCV_SYSREG_HIDELEG = 0x603,
RISCV_SYSREG_HIE = 0x604,
RISCV_SYSREG_HTIMEDELTA = 0x605,
RISCV_SYSREG_HCOUNTEREN = 0x606,
RISCV_SYSREG_HGEIE = 0x607,
RISCV_SYSREG_HVIEN = 0x608,
RISCV_SYSREG_HVICTL = 0x609,
RISCV_SYSREG_HENVCFG = 0x60a,
RISCV_SYSREG_HSTATEEN0 = 0x60c,
RISCV_SYSREG_HSTATEEN1 = 0x60d,
RISCV_SYSREG_HSTATEEN2 = 0x60e,
RISCV_SYSREG_HSTATEEN3 = 0x60f,
RISCV_SYSREG_HIDELEGH = 0x613,
RISCV_SYSREG_HTIMEDELTAH = 0x615,
RISCV_SYSREG_HVIENH = 0x618,
RISCV_SYSREG_HENVCFGH = 0x61a,
RISCV_SYSREG_HSTATEEN0H = 0x61c,
RISCV_SYSREG_HSTATEEN1H = 0x61d,
RISCV_SYSREG_HSTATEEN2H = 0x61e,
RISCV_SYSREG_HSTATEEN3H = 0x61f,
RISCV_SYSREG_HTVAL = 0x643,
RISCV_SYSREG_HIP = 0x644,
RISCV_SYSREG_HVIP = 0x645,
RISCV_SYSREG_HVIPRIO1 = 0x646,
RISCV_SYSREG_HVIPRIO2 = 0x647,
RISCV_SYSREG_HTINST = 0x64a,
RISCV_SYSREG_HVIPH = 0x655,
RISCV_SYSREG_HVIPRIO1H = 0x656,
RISCV_SYSREG_HVIPRIO2H = 0x657,
RISCV_SYSREG_HGATP = 0x680,
RISCV_SYSREG_HCONTEXT = 0x6a8,
RISCV_SYSREG_MHPMEVENT3H = 0x723,
RISCV_SYSREG_MHPMEVENT4H = 0x724,
RISCV_SYSREG_MHPMEVENT5H = 0x725,
RISCV_SYSREG_MHPMEVENT6H = 0x726,
RISCV_SYSREG_MHPMEVENT7H = 0x727,
RISCV_SYSREG_MHPMEVENT8H = 0x728,
RISCV_SYSREG_MHPMEVENT9H = 0x729,
RISCV_SYSREG_MHPMEVENT10H = 0x72a,
RISCV_SYSREG_MHPMEVENT11H = 0x72b,
RISCV_SYSREG_MHPMEVENT12H = 0x72c,
RISCV_SYSREG_MHPMEVENT13H = 0x72d,
RISCV_SYSREG_MHPMEVENT14H = 0x72e,
RISCV_SYSREG_MHPMEVENT15H = 0x72f,
RISCV_SYSREG_MHPMEVENT16H = 0x730,
RISCV_SYSREG_MHPMEVENT17H = 0x731,
RISCV_SYSREG_MHPMEVENT18H = 0x732,
RISCV_SYSREG_MHPMEVENT19H = 0x733,
RISCV_SYSREG_MHPMEVENT20H = 0x734,
RISCV_SYSREG_MHPMEVENT21H = 0x735,
RISCV_SYSREG_MHPMEVENT22H = 0x736,
RISCV_SYSREG_MHPMEVENT23H = 0x737,
RISCV_SYSREG_MHPMEVENT24H = 0x738,
RISCV_SYSREG_MHPMEVENT25H = 0x739,
RISCV_SYSREG_MHPMEVENT26H = 0x73a,
RISCV_SYSREG_MHPMEVENT27H = 0x73b,
RISCV_SYSREG_MHPMEVENT28H = 0x73c,
RISCV_SYSREG_MHPMEVENT29H = 0x73d,
RISCV_SYSREG_MHPMEVENT30H = 0x73e,
RISCV_SYSREG_MHPMEVENT31H = 0x73f,
RISCV_SYSREG_MSECCFG = 0x747,
RISCV_SYSREG_MSECCFGH = 0x757,
RISCV_SYSREG_TSELECT = 0x7a0,
RISCV_SYSREG_TDATA1 = 0x7a1,
RISCV_SYSREG_TDATA2 = 0x7a2,
RISCV_SYSREG_TDATA3 = 0x7a3,
RISCV_SYSREG_MCONTEXT = 0x7a8,
RISCV_SYSREG_DCSR = 0x7b0,
RISCV_SYSREG_DPC = 0x7b1,
RISCV_SYSREG_DSCRATCH0 = 0x7b2,
RISCV_SYSREG_DSCRATCH = 0x7b2,
RISCV_SYSREG_DSCRATCH1 = 0x7b3,
RISCV_SYSREG_MCYCLE = 0xb00,
RISCV_SYSREG_MINSTRET = 0xb02,
RISCV_SYSREG_MHPMCOUNTER3 = 0xb03,
RISCV_SYSREG_MHPMCOUNTER4 = 0xb04,
RISCV_SYSREG_MHPMCOUNTER5 = 0xb05,
RISCV_SYSREG_MHPMCOUNTER6 = 0xb06,
RISCV_SYSREG_MHPMCOUNTER7 = 0xb07,
RISCV_SYSREG_MHPMCOUNTER8 = 0xb08,
RISCV_SYSREG_MHPMCOUNTER9 = 0xb09,
RISCV_SYSREG_MHPMCOUNTER10 = 0xb0a,
RISCV_SYSREG_MHPMCOUNTER11 = 0xb0b,
RISCV_SYSREG_MHPMCOUNTER12 = 0xb0c,
RISCV_SYSREG_MHPMCOUNTER13 = 0xb0d,
RISCV_SYSREG_MHPMCOUNTER14 = 0xb0e,
RISCV_SYSREG_MHPMCOUNTER15 = 0xb0f,
RISCV_SYSREG_MHPMCOUNTER16 = 0xb10,
RISCV_SYSREG_MHPMCOUNTER17 = 0xb11,
RISCV_SYSREG_MHPMCOUNTER18 = 0xb12,
RISCV_SYSREG_MHPMCOUNTER19 = 0xb13,
RISCV_SYSREG_MHPMCOUNTER20 = 0xb14,
RISCV_SYSREG_MHPMCOUNTER21 = 0xb15,
RISCV_SYSREG_MHPMCOUNTER22 = 0xb16,
RISCV_SYSREG_MHPMCOUNTER23 = 0xb17,
RISCV_SYSREG_MHPMCOUNTER24 = 0xb18,
RISCV_SYSREG_MHPMCOUNTER25 = 0xb19,
RISCV_SYSREG_MHPMCOUNTER26 = 0xb1a,
RISCV_SYSREG_MHPMCOUNTER27 = 0xb1b,
RISCV_SYSREG_MHPMCOUNTER28 = 0xb1c,
RISCV_SYSREG_MHPMCOUNTER29 = 0xb1d,
RISCV_SYSREG_MHPMCOUNTER30 = 0xb1e,
RISCV_SYSREG_MHPMCOUNTER31 = 0xb1f,
RISCV_SYSREG_MCYCLEH = 0xb80,
RISCV_SYSREG_MINSTRETH = 0xb82,
RISCV_SYSREG_MHPMCOUNTER3H = 0xb83,
RISCV_SYSREG_MHPMCOUNTER4H = 0xb84,
RISCV_SYSREG_MHPMCOUNTER5H = 0xb85,
RISCV_SYSREG_MHPMCOUNTER6H = 0xb86,
RISCV_SYSREG_MHPMCOUNTER7H = 0xb87,
RISCV_SYSREG_MHPMCOUNTER8H = 0xb88,
RISCV_SYSREG_MHPMCOUNTER9H = 0xb89,
RISCV_SYSREG_MHPMCOUNTER10H = 0xb8a,
RISCV_SYSREG_MHPMCOUNTER11H = 0xb8b,
RISCV_SYSREG_MHPMCOUNTER12H = 0xb8c,
RISCV_SYSREG_MHPMCOUNTER13H = 0xb8d,
RISCV_SYSREG_MHPMCOUNTER14H = 0xb8e,
RISCV_SYSREG_MHPMCOUNTER15H = 0xb8f,
RISCV_SYSREG_MHPMCOUNTER16H = 0xb90,
RISCV_SYSREG_MHPMCOUNTER17H = 0xb91,
RISCV_SYSREG_MHPMCOUNTER18H = 0xb92,
RISCV_SYSREG_MHPMCOUNTER19H = 0xb93,
RISCV_SYSREG_MHPMCOUNTER20H = 0xb94,
RISCV_SYSREG_MHPMCOUNTER21H = 0xb95,
RISCV_SYSREG_MHPMCOUNTER22H = 0xb96,
RISCV_SYSREG_MHPMCOUNTER23H = 0xb97,
RISCV_SYSREG_MHPMCOUNTER24H = 0xb98,
RISCV_SYSREG_MHPMCOUNTER25H = 0xb99,
RISCV_SYSREG_MHPMCOUNTER26H = 0xb9a,
RISCV_SYSREG_MHPMCOUNTER27H = 0xb9b,
RISCV_SYSREG_MHPMCOUNTER28H = 0xb9c,
RISCV_SYSREG_MHPMCOUNTER29H = 0xb9d,
RISCV_SYSREG_MHPMCOUNTER30H = 0xb9e,
RISCV_SYSREG_MHPMCOUNTER31H = 0xb9f,
RISCV_SYSREG_CYCLE = 0xc00,
RISCV_SYSREG_TIME = 0xc01,
RISCV_SYSREG_INSTRET = 0xc02,
RISCV_SYSREG_HPMCOUNTER3 = 0xc03,
RISCV_SYSREG_HPMCOUNTER4 = 0xc04,
RISCV_SYSREG_HPMCOUNTER5 = 0xc05,
RISCV_SYSREG_HPMCOUNTER6 = 0xc06,
RISCV_SYSREG_HPMCOUNTER7 = 0xc07,
RISCV_SYSREG_HPMCOUNTER8 = 0xc08,
RISCV_SYSREG_HPMCOUNTER9 = 0xc09,
RISCV_SYSREG_HPMCOUNTER10 = 0xc0a,
RISCV_SYSREG_HPMCOUNTER11 = 0xc0b,
RISCV_SYSREG_HPMCOUNTER12 = 0xc0c,
RISCV_SYSREG_HPMCOUNTER13 = 0xc0d,
RISCV_SYSREG_HPMCOUNTER14 = 0xc0e,
RISCV_SYSREG_HPMCOUNTER15 = 0xc0f,
RISCV_SYSREG_HPMCOUNTER16 = 0xc10,
RISCV_SYSREG_HPMCOUNTER17 = 0xc11,
RISCV_SYSREG_HPMCOUNTER18 = 0xc12,
RISCV_SYSREG_HPMCOUNTER19 = 0xc13,
RISCV_SYSREG_HPMCOUNTER20 = 0xc14,
RISCV_SYSREG_HPMCOUNTER21 = 0xc15,
RISCV_SYSREG_HPMCOUNTER22 = 0xc16,
RISCV_SYSREG_HPMCOUNTER23 = 0xc17,
RISCV_SYSREG_HPMCOUNTER24 = 0xc18,
RISCV_SYSREG_HPMCOUNTER25 = 0xc19,
RISCV_SYSREG_HPMCOUNTER26 = 0xc1a,
RISCV_SYSREG_HPMCOUNTER27 = 0xc1b,
RISCV_SYSREG_HPMCOUNTER28 = 0xc1c,
RISCV_SYSREG_HPMCOUNTER29 = 0xc1d,
RISCV_SYSREG_HPMCOUNTER30 = 0xc1e,
RISCV_SYSREG_HPMCOUNTER31 = 0xc1f,
RISCV_SYSREG_VL = 0xc20,
RISCV_SYSREG_VTYPE = 0xc21,
RISCV_SYSREG_VLENB = 0xc22,
RISCV_SYSREG_CYCLEH = 0xc80,
RISCV_SYSREG_TIMEH = 0xc81,
RISCV_SYSREG_INSTRETH = 0xc82,
RISCV_SYSREG_HPMCOUNTER3H = 0xc83,
RISCV_SYSREG_HPMCOUNTER4H = 0xc84,
RISCV_SYSREG_HPMCOUNTER5H = 0xc85,
RISCV_SYSREG_HPMCOUNTER6H = 0xc86,
RISCV_SYSREG_HPMCOUNTER7H = 0xc87,
RISCV_SYSREG_HPMCOUNTER8H = 0xc88,
RISCV_SYSREG_HPMCOUNTER9H = 0xc89,
RISCV_SYSREG_HPMCOUNTER10H = 0xc8a,
RISCV_SYSREG_HPMCOUNTER11H = 0xc8b,
RISCV_SYSREG_HPMCOUNTER12H = 0xc8c,
RISCV_SYSREG_HPMCOUNTER13H = 0xc8d,
RISCV_SYSREG_HPMCOUNTER14H = 0xc8e,
RISCV_SYSREG_HPMCOUNTER15H = 0xc8f,
RISCV_SYSREG_HPMCOUNTER16H = 0xc90,
RISCV_SYSREG_HPMCOUNTER17H = 0xc91,
RISCV_SYSREG_HPMCOUNTER18H = 0xc92,
RISCV_SYSREG_HPMCOUNTER19H = 0xc93,
RISCV_SYSREG_HPMCOUNTER20H = 0xc94,
RISCV_SYSREG_HPMCOUNTER21H = 0xc95,
RISCV_SYSREG_HPMCOUNTER22H = 0xc96,
RISCV_SYSREG_HPMCOUNTER23H = 0xc97,
RISCV_SYSREG_HPMCOUNTER24H = 0xc98,
RISCV_SYSREG_HPMCOUNTER25H = 0xc99,
RISCV_SYSREG_HPMCOUNTER26H = 0xc9a,
RISCV_SYSREG_HPMCOUNTER27H = 0xc9b,
RISCV_SYSREG_HPMCOUNTER28H = 0xc9c,
RISCV_SYSREG_HPMCOUNTER29H = 0xc9d,
RISCV_SYSREG_HPMCOUNTER30H = 0xc9e,
RISCV_SYSREG_HPMCOUNTER31H = 0xc9f,
RISCV_SYSREG_SCOUNTOVF = 0xda0,
RISCV_SYSREG_STOPI = 0xdb0,
RISCV_SYSREG_HGEIP = 0xe12,
RISCV_SYSREG_VSTOPI = 0xeb0,
RISCV_SYSREG_MVENDORID = 0xf11,
RISCV_SYSREG_MARCHID = 0xf12,
RISCV_SYSREG_MIMPID = 0xf13,
RISCV_SYSREG_MHARTID = 0xf14,
RISCV_SYSREG_MCONFIGPTR = 0xf15,
RISCV_SYSREG_MTOPI = 0xfb0,
#endif
arch/RISCV/RISCVGenCompressedInstructionsInfo.inc
+3669
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File diff suppressed because it is too large Load Diff
arch/RISCV/RISCVGenDisassemblerTables.inc
+9085 -1513
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File diff suppressed because it is too large Load Diff
arch/RISCV/RISCVGenInsnNameMaps.inc
-275
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@@ -1,275 +0,0 @@
// This is auto-gen data for Capstone engine (www.capstone-engine.org)
// By Nguyen Anh Quynh <[email protected]>
{ RISCV_INS_ADD, "add" },
{ RISCV_INS_ADDI, "addi" },
{ RISCV_INS_ADDIW, "addiw" },
{ RISCV_INS_ADDW, "addw" },
{ RISCV_INS_AMOADD_D, "amoadd.d" },
{ RISCV_INS_AMOADD_D_AQ, "amoadd.d.aq" },
{ RISCV_INS_AMOADD_D_AQ_RL, "amoadd.d.aqrl" },
{ RISCV_INS_AMOADD_D_RL, "amoadd.d.rl" },
{ RISCV_INS_AMOADD_W, "amoadd.w" },
{ RISCV_INS_AMOADD_W_AQ, "amoadd.w.aq" },
{ RISCV_INS_AMOADD_W_AQ_RL, "amoadd.w.aqrl" },
{ RISCV_INS_AMOADD_W_RL, "amoadd.w.rl" },
{ RISCV_INS_AMOAND_D, "amoand.d" },
{ RISCV_INS_AMOAND_D_AQ, "amoand.d.aq" },
{ RISCV_INS_AMOAND_D_AQ_RL, "amoand.d.aqrl" },
{ RISCV_INS_AMOAND_D_RL, "amoand.d.rl" },
{ RISCV_INS_AMOAND_W, "amoand.w" },
{ RISCV_INS_AMOAND_W_AQ, "amoand.w.aq" },
{ RISCV_INS_AMOAND_W_AQ_RL, "amoand.w.aqrl" },
{ RISCV_INS_AMOAND_W_RL, "amoand.w.rl" },
{ RISCV_INS_AMOMAXU_D, "amomaxu.d" },
{ RISCV_INS_AMOMAXU_D_AQ, "amomaxu.d.aq" },
{ RISCV_INS_AMOMAXU_D_AQ_RL, "amomaxu.d.aqrl" },
{ RISCV_INS_AMOMAXU_D_RL, "amomaxu.d.rl" },
{ RISCV_INS_AMOMAXU_W, "amomaxu.w" },
{ RISCV_INS_AMOMAXU_W_AQ, "amomaxu.w.aq" },
{ RISCV_INS_AMOMAXU_W_AQ_RL, "amomaxu.w.aqrl" },
{ RISCV_INS_AMOMAXU_W_RL, "amomaxu.w.rl" },
{ RISCV_INS_AMOMAX_D, "amomax.d" },
{ RISCV_INS_AMOMAX_D_AQ, "amomax.d.aq" },
{ RISCV_INS_AMOMAX_D_AQ_RL, "amomax.d.aqrl" },
{ RISCV_INS_AMOMAX_D_RL, "amomax.d.rl" },
{ RISCV_INS_AMOMAX_W, "amomax.w" },
{ RISCV_INS_AMOMAX_W_AQ, "amomax.w.aq" },
{ RISCV_INS_AMOMAX_W_AQ_RL, "amomax.w.aqrl" },
{ RISCV_INS_AMOMAX_W_RL, "amomax.w.rl" },
{ RISCV_INS_AMOMINU_D, "amominu.d" },
{ RISCV_INS_AMOMINU_D_AQ, "amominu.d.aq" },
{ RISCV_INS_AMOMINU_D_AQ_RL, "amominu.d.aqrl" },
{ RISCV_INS_AMOMINU_D_RL, "amominu.d.rl" },
{ RISCV_INS_AMOMINU_W, "amominu.w" },
{ RISCV_INS_AMOMINU_W_AQ, "amominu.w.aq" },
{ RISCV_INS_AMOMINU_W_AQ_RL, "amominu.w.aqrl" },
{ RISCV_INS_AMOMINU_W_RL, "amominu.w.rl" },
{ RISCV_INS_AMOMIN_D, "amomin.d" },
{ RISCV_INS_AMOMIN_D_AQ, "amomin.d.aq" },
{ RISCV_INS_AMOMIN_D_AQ_RL, "amomin.d.aqrl" },
{ RISCV_INS_AMOMIN_D_RL, "amomin.d.rl" },
{ RISCV_INS_AMOMIN_W, "amomin.w" },
{ RISCV_INS_AMOMIN_W_AQ, "amomin.w.aq" },
{ RISCV_INS_AMOMIN_W_AQ_RL, "amomin.w.aqrl" },
{ RISCV_INS_AMOMIN_W_RL, "amomin.w.rl" },
{ RISCV_INS_AMOOR_D, "amoor.d" },
{ RISCV_INS_AMOOR_D_AQ, "amoor.d.aq" },
{ RISCV_INS_AMOOR_D_AQ_RL, "amoor.d.aqrl" },
{ RISCV_INS_AMOOR_D_RL, "amoor.d.rl" },
{ RISCV_INS_AMOOR_W, "amoor.w" },
{ RISCV_INS_AMOOR_W_AQ, "amoor.w.aq" },
{ RISCV_INS_AMOOR_W_AQ_RL, "amoor.w.aqrl" },
{ RISCV_INS_AMOOR_W_RL, "amoor.w.rl" },
{ RISCV_INS_AMOSWAP_D, "amoswap.d" },
{ RISCV_INS_AMOSWAP_D_AQ, "amoswap.d.aq" },
{ RISCV_INS_AMOSWAP_D_AQ_RL, "amoswap.d.aqrl" },
{ RISCV_INS_AMOSWAP_D_RL, "amoswap.d.rl" },
{ RISCV_INS_AMOSWAP_W, "amoswap.w" },
{ RISCV_INS_AMOSWAP_W_AQ, "amoswap.w.aq" },
{ RISCV_INS_AMOSWAP_W_AQ_RL, "amoswap.w.aqrl" },
{ RISCV_INS_AMOSWAP_W_RL, "amoswap.w.rl" },
{ RISCV_INS_AMOXOR_D, "amoxor.d" },
{ RISCV_INS_AMOXOR_D_AQ, "amoxor.d.aq" },
{ RISCV_INS_AMOXOR_D_AQ_RL, "amoxor.d.aqrl" },
{ RISCV_INS_AMOXOR_D_RL, "amoxor.d.rl" },
{ RISCV_INS_AMOXOR_W, "amoxor.w" },
{ RISCV_INS_AMOXOR_W_AQ, "amoxor.w.aq" },
{ RISCV_INS_AMOXOR_W_AQ_RL, "amoxor.w.aqrl" },
{ RISCV_INS_AMOXOR_W_RL, "amoxor.w.rl" },
{ RISCV_INS_AND, "and" },
{ RISCV_INS_ANDI, "andi" },
{ RISCV_INS_AUIPC, "auipc" },
{ RISCV_INS_BEQ, "beq" },
{ RISCV_INS_BGE, "bge" },
{ RISCV_INS_BGEU, "bgeu" },
{ RISCV_INS_BLT, "blt" },
{ RISCV_INS_BLTU, "bltu" },
{ RISCV_INS_BNE, "bne" },
{ RISCV_INS_CSRRC, "csrrc" },
{ RISCV_INS_CSRRCI, "csrrci" },
{ RISCV_INS_CSRRS, "csrrs" },
{ RISCV_INS_CSRRSI, "csrrsi" },
{ RISCV_INS_CSRRW, "csrrw" },
{ RISCV_INS_CSRRWI, "csrrwi" },
{ RISCV_INS_C_ADD, "c.add" },
{ RISCV_INS_C_ADDI, "c.addi" },
{ RISCV_INS_C_ADDI16SP, "c.addi16sp" },
{ RISCV_INS_C_ADDI4SPN, "c.addi4spn" },
{ RISCV_INS_C_ADDIW, "c.addiw" },
{ RISCV_INS_C_ADDW, "c.addw" },
{ RISCV_INS_C_AND, "c.and" },
{ RISCV_INS_C_ANDI, "c.andi" },
{ RISCV_INS_C_BEQZ, "c.beqz" },
{ RISCV_INS_C_BNEZ, "c.bnez" },
{ RISCV_INS_C_EBREAK, "c.ebreak" },
{ RISCV_INS_C_FLD, "c.fld" },
{ RISCV_INS_C_FLDSP, "c.fldsp" },
{ RISCV_INS_C_FLW, "c.flw" },
{ RISCV_INS_C_FLWSP, "c.flwsp" },
{ RISCV_INS_C_FSD, "c.fsd" },
{ RISCV_INS_C_FSDSP, "c.fsdsp" },
{ RISCV_INS_C_FSW, "c.fsw" },
{ RISCV_INS_C_FSWSP, "c.fswsp" },
{ RISCV_INS_C_J, "c.j" },
{ RISCV_INS_C_JAL, "c.jal" },
{ RISCV_INS_C_JALR, "c.jalr" },
{ RISCV_INS_C_JR, "c.jr" },
{ RISCV_INS_C_LD, "c.ld" },
{ RISCV_INS_C_LDSP, "c.ldsp" },
{ RISCV_INS_C_LI, "c.li" },
{ RISCV_INS_C_LUI, "c.lui" },
{ RISCV_INS_C_LW, "c.lw" },
{ RISCV_INS_C_LWSP, "c.lwsp" },
{ RISCV_INS_C_MV, "c.mv" },
{ RISCV_INS_C_NOP, "c.nop" },
{ RISCV_INS_C_OR, "c.or" },
{ RISCV_INS_C_SD, "c.sd" },
{ RISCV_INS_C_SDSP, "c.sdsp" },
{ RISCV_INS_C_SLLI, "c.slli" },
{ RISCV_INS_C_SRAI, "c.srai" },
{ RISCV_INS_C_SRLI, "c.srli" },
{ RISCV_INS_C_SUB, "c.sub" },
{ RISCV_INS_C_SUBW, "c.subw" },
{ RISCV_INS_C_SW, "c.sw" },
{ RISCV_INS_C_SWSP, "c.swsp" },
{ RISCV_INS_C_UNIMP, "c.unimp" },
{ RISCV_INS_C_XOR, "c.xor" },
{ RISCV_INS_DIV, "div" },
{ RISCV_INS_DIVU, "divu" },
{ RISCV_INS_DIVUW, "divuw" },
{ RISCV_INS_DIVW, "divw" },
{ RISCV_INS_EBREAK, "ebreak" },
{ RISCV_INS_ECALL, "ecall" },
{ RISCV_INS_FADD_D, "fadd.d" },
{ RISCV_INS_FADD_S, "fadd.s" },
{ RISCV_INS_FCLASS_D, "fclass.d" },
{ RISCV_INS_FCLASS_S, "fclass.s" },
{ RISCV_INS_FCVT_D_L, "fcvt.d.l" },
{ RISCV_INS_FCVT_D_LU, "fcvt.d.lu" },
{ RISCV_INS_FCVT_D_S, "fcvt.d.s" },
{ RISCV_INS_FCVT_D_W, "fcvt.d.w" },
{ RISCV_INS_FCVT_D_WU, "fcvt.d.wu" },
{ RISCV_INS_FCVT_LU_D, "fcvt.lu.d" },
{ RISCV_INS_FCVT_LU_S, "fcvt.lu.s" },
{ RISCV_INS_FCVT_L_D, "fcvt.l.d" },
{ RISCV_INS_FCVT_L_S, "fcvt.l.s" },
{ RISCV_INS_FCVT_S_D, "fcvt.s.d" },
{ RISCV_INS_FCVT_S_L, "fcvt.s.l" },
{ RISCV_INS_FCVT_S_LU, "fcvt.s.lu" },
{ RISCV_INS_FCVT_S_W, "fcvt.s.w" },
{ RISCV_INS_FCVT_S_WU, "fcvt.s.wu" },
{ RISCV_INS_FCVT_WU_D, "fcvt.wu.d" },
{ RISCV_INS_FCVT_WU_S, "fcvt.wu.s" },
{ RISCV_INS_FCVT_W_D, "fcvt.w.d" },
{ RISCV_INS_FCVT_W_S, "fcvt.w.s" },
{ RISCV_INS_FDIV_D, "fdiv.d" },
{ RISCV_INS_FDIV_S, "fdiv.s" },
{ RISCV_INS_FENCE, "fence" },
{ RISCV_INS_FENCE_I, "fence.i" },
{ RISCV_INS_FENCE_TSO, "fence.tso" },
{ RISCV_INS_FEQ_D, "feq.d" },
{ RISCV_INS_FEQ_S, "feq.s" },
{ RISCV_INS_FLD, "fld" },
{ RISCV_INS_FLE_D, "fle.d" },
{ RISCV_INS_FLE_S, "fle.s" },
{ RISCV_INS_FLT_D, "flt.d" },
{ RISCV_INS_FLT_S, "flt.s" },
{ RISCV_INS_FLW, "flw" },
{ RISCV_INS_FMADD_D, "fmadd.d" },
{ RISCV_INS_FMADD_S, "fmadd.s" },
{ RISCV_INS_FMAX_D, "fmax.d" },
{ RISCV_INS_FMAX_S, "fmax.s" },
{ RISCV_INS_FMIN_D, "fmin.d" },
{ RISCV_INS_FMIN_S, "fmin.s" },
{ RISCV_INS_FMSUB_D, "fmsub.d" },
{ RISCV_INS_FMSUB_S, "fmsub.s" },
{ RISCV_INS_FMUL_D, "fmul.d" },
{ RISCV_INS_FMUL_S, "fmul.s" },
{ RISCV_INS_FMV_D_X, "fmv.d.x" },
{ RISCV_INS_FMV_W_X, "fmv.w.x" },
{ RISCV_INS_FMV_X_D, "fmv.x.d" },
{ RISCV_INS_FMV_X_W, "fmv.x.w" },
{ RISCV_INS_FNMADD_D, "fnmadd.d" },
{ RISCV_INS_FNMADD_S, "fnmadd.s" },
{ RISCV_INS_FNMSUB_D, "fnmsub.d" },
{ RISCV_INS_FNMSUB_S, "fnmsub.s" },
{ RISCV_INS_FSD, "fsd" },
{ RISCV_INS_FSGNJN_D, "fsgnjn.d" },
{ RISCV_INS_FSGNJN_S, "fsgnjn.s" },
{ RISCV_INS_FSGNJX_D, "fsgnjx.d" },
{ RISCV_INS_FSGNJX_S, "fsgnjx.s" },
{ RISCV_INS_FSGNJ_D, "fsgnj.d" },
{ RISCV_INS_FSGNJ_S, "fsgnj.s" },
{ RISCV_INS_FSQRT_D, "fsqrt.d" },
{ RISCV_INS_FSQRT_S, "fsqrt.s" },
{ RISCV_INS_FSUB_D, "fsub.d" },
{ RISCV_INS_FSUB_S, "fsub.s" },
{ RISCV_INS_FSW, "fsw" },
{ RISCV_INS_JAL, "jal" },
{ RISCV_INS_JALR, "jalr" },
{ RISCV_INS_LB, "lb" },
{ RISCV_INS_LBU, "lbu" },
{ RISCV_INS_LD, "ld" },
{ RISCV_INS_LH, "lh" },
{ RISCV_INS_LHU, "lhu" },
{ RISCV_INS_LR_D, "lr.d" },
{ RISCV_INS_LR_D_AQ, "lr.d.aq" },
{ RISCV_INS_LR_D_AQ_RL, "lr.d.aqrl" },
{ RISCV_INS_LR_D_RL, "lr.d.rl" },
{ RISCV_INS_LR_W, "lr.w" },
{ RISCV_INS_LR_W_AQ, "lr.w.aq" },
{ RISCV_INS_LR_W_AQ_RL, "lr.w.aqrl" },
{ RISCV_INS_LR_W_RL, "lr.w.rl" },
{ RISCV_INS_LUI, "lui" },
{ RISCV_INS_LW, "lw" },
{ RISCV_INS_LWU, "lwu" },
{ RISCV_INS_MRET, "mret" },
{ RISCV_INS_MUL, "mul" },
{ RISCV_INS_MULH, "mulh" },
{ RISCV_INS_MULHSU, "mulhsu" },
{ RISCV_INS_MULHU, "mulhu" },
{ RISCV_INS_MULW, "mulw" },
{ RISCV_INS_OR, "or" },
{ RISCV_INS_ORI, "ori" },
{ RISCV_INS_REM, "rem" },
{ RISCV_INS_REMU, "remu" },
{ RISCV_INS_REMUW, "remuw" },
{ RISCV_INS_REMW, "remw" },
{ RISCV_INS_SB, "sb" },
{ RISCV_INS_SC_D, "sc.d" },
{ RISCV_INS_SC_D_AQ, "sc.d.aq" },
{ RISCV_INS_SC_D_AQ_RL, "sc.d.aqrl" },
{ RISCV_INS_SC_D_RL, "sc.d.rl" },
{ RISCV_INS_SC_W, "sc.w" },
{ RISCV_INS_SC_W_AQ, "sc.w.aq" },
{ RISCV_INS_SC_W_AQ_RL, "sc.w.aqrl" },
{ RISCV_INS_SC_W_RL, "sc.w.rl" },
{ RISCV_INS_SD, "sd" },
{ RISCV_INS_SFENCE_VMA, "sfence.vma" },
{ RISCV_INS_SH, "sh" },
{ RISCV_INS_SLL, "sll" },
{ RISCV_INS_SLLI, "slli" },
{ RISCV_INS_SLLIW, "slliw" },
{ RISCV_INS_SLLW, "sllw" },
{ RISCV_INS_SLT, "slt" },
{ RISCV_INS_SLTI, "slti" },
{ RISCV_INS_SLTIU, "sltiu" },
{ RISCV_INS_SLTU, "sltu" },
{ RISCV_INS_SRA, "sra" },
{ RISCV_INS_SRAI, "srai" },
{ RISCV_INS_SRAIW, "sraiw" },
{ RISCV_INS_SRAW, "sraw" },
{ RISCV_INS_SRET, "sret" },
{ RISCV_INS_SRL, "srl" },
{ RISCV_INS_SRLI, "srli" },
{ RISCV_INS_SRLIW, "srliw" },
{ RISCV_INS_SRLW, "srlw" },
{ RISCV_INS_SUB, "sub" },
{ RISCV_INS_SUBW, "subw" },
{ RISCV_INS_SW, "sw" },
{ RISCV_INS_UNIMP, "unimp" },
{ RISCV_INS_URET, "uret" },
{ RISCV_INS_WFI, "wfi" },
{ RISCV_INS_XOR, "xor" },
{ RISCV_INS_XORI, "xori" },
arch/RISCV/RISCVGenInstrInfo.inc
+27656 -447
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File diff suppressed because it is too large Load Diff
arch/RISCV/RISCVGenRegisterInfo.inc
+2650 -278
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File diff suppressed because it is too large Load Diff
arch/RISCV/RISCVGenSubtargetInfo.inc
+201 -23
View File
@@ -1,33 +1,211 @@
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|* *|
|* Subtarget Enumeration Source Fragment *|
|* *|
|* Automatically generated file, do not edit! *|
|* *|
\*===----------------------------------------------------------------------===*/
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <[email protected]>, 2013-2022, */
/* Rot127 <[email protected]> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* By Nguyen Anh Quynh <[email protected]>, 2013-2015 */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
#ifdef GET_SUBTARGETINFO_ENUM
#undef GET_SUBTARGETINFO_ENUM
/*
Make sure:
CS_MODE_RISCV64 = 0b11111
CS_MODE_RISCV32 = 0b11110
*/
enum {
RISCV_Feature64Bit = 1ULL << 0,
RISCV_FeatureStdExtA = 1ULL << 1,
RISCV_FeatureStdExtC = 1ULL << 2,
RISCV_FeatureStdExtD = 1ULL << 3,
RISCV_FeatureStdExtF = 1ULL << 4,
RISCV_FeatureStdExtM = 1ULL << 5,
RISCV_FeatureRelax = 1ULL << 6,
RISCV_Experimental = 0,
RISCV_Feature32Bit = 1,
RISCV_Feature64Bit = 2,
RISCV_FeatureFastUnalignedAccess = 3,
RISCV_FeatureForcedAtomics = 4,
RISCV_FeatureNoRVCHints = 5,
RISCV_FeaturePostRAScheduler = 6,
RISCV_FeatureRVE = 7,
RISCV_FeatureRelax = 8,
RISCV_FeatureReserveX1 = 9,
RISCV_FeatureReserveX2 = 10,
RISCV_FeatureReserveX3 = 11,
RISCV_FeatureReserveX4 = 12,
RISCV_FeatureReserveX5 = 13,
RISCV_FeatureReserveX6 = 14,
RISCV_FeatureReserveX7 = 15,
RISCV_FeatureReserveX8 = 16,
RISCV_FeatureReserveX9 = 17,
RISCV_FeatureReserveX10 = 18,
RISCV_FeatureReserveX11 = 19,
RISCV_FeatureReserveX12 = 20,
RISCV_FeatureReserveX13 = 21,
RISCV_FeatureReserveX14 = 22,
RISCV_FeatureReserveX15 = 23,
RISCV_FeatureReserveX16 = 24,
RISCV_FeatureReserveX17 = 25,
RISCV_FeatureReserveX18 = 26,
RISCV_FeatureReserveX19 = 27,
RISCV_FeatureReserveX20 = 28,
RISCV_FeatureReserveX21 = 29,
RISCV_FeatureReserveX22 = 30,
RISCV_FeatureReserveX23 = 31,
RISCV_FeatureReserveX24 = 32,
RISCV_FeatureReserveX25 = 33,
RISCV_FeatureReserveX26 = 34,
RISCV_FeatureReserveX27 = 35,
RISCV_FeatureReserveX28 = 36,
RISCV_FeatureReserveX29 = 37,
RISCV_FeatureReserveX30 = 38,
RISCV_FeatureReserveX31 = 39,
RISCV_FeatureSaveRestore = 40,
RISCV_FeatureStdExtA = 41,
RISCV_FeatureStdExtC = 42,
RISCV_FeatureStdExtD = 43,
RISCV_FeatureStdExtF = 44,
RISCV_FeatureStdExtH = 45,
RISCV_FeatureStdExtI = 46,
RISCV_FeatureStdExtM = 47,
RISCV_FeatureStdExtSmaia = 48,
RISCV_FeatureStdExtSmepmp = 49,
RISCV_FeatureStdExtSsaia = 50,
RISCV_FeatureStdExtSvinval = 51,
RISCV_FeatureStdExtSvnapot = 52,
RISCV_FeatureStdExtSvpbmt = 53,
RISCV_FeatureStdExtV = 54,
RISCV_FeatureStdExtZa64rs = 55,
RISCV_FeatureStdExtZa128rs = 56,
RISCV_FeatureStdExtZacas = 57,
RISCV_FeatureStdExtZawrs = 58,
RISCV_FeatureStdExtZba = 59,
RISCV_FeatureStdExtZbb = 60,
RISCV_FeatureStdExtZbc = 61,
RISCV_FeatureStdExtZbkb = 62,
RISCV_FeatureStdExtZbkc = 63,
RISCV_FeatureStdExtZbkx = 64,
RISCV_FeatureStdExtZbs = 65,
RISCV_FeatureStdExtZca = 66,
RISCV_FeatureStdExtZcb = 67,
RISCV_FeatureStdExtZcd = 68,
RISCV_FeatureStdExtZce = 69,
RISCV_FeatureStdExtZcf = 70,
RISCV_FeatureStdExtZcmop = 71,
RISCV_FeatureStdExtZcmp = 72,
RISCV_FeatureStdExtZcmt = 73,
RISCV_FeatureStdExtZdinx = 74,
RISCV_FeatureStdExtZfa = 75,
RISCV_FeatureStdExtZfbfmin = 76,
RISCV_FeatureStdExtZfh = 77,
RISCV_FeatureStdExtZfhmin = 78,
RISCV_FeatureStdExtZfinx = 79,
RISCV_FeatureStdExtZhinx = 80,
RISCV_FeatureStdExtZhinxmin = 81,
RISCV_FeatureStdExtZic64b = 82,
RISCV_FeatureStdExtZicbom = 83,
RISCV_FeatureStdExtZicbop = 84,
RISCV_FeatureStdExtZicboz = 85,
RISCV_FeatureStdExtZiccamoa = 86,
RISCV_FeatureStdExtZiccif = 87,
RISCV_FeatureStdExtZicclsm = 88,
RISCV_FeatureStdExtZiccrse = 89,
RISCV_FeatureStdExtZicfilp = 90,
RISCV_FeatureStdExtZicfiss = 91,
RISCV_FeatureStdExtZicntr = 92,
RISCV_FeatureStdExtZicond = 93,
RISCV_FeatureStdExtZicsr = 94,
RISCV_FeatureStdExtZifencei = 95,
RISCV_FeatureStdExtZihintntl = 96,
RISCV_FeatureStdExtZihintpause = 97,
RISCV_FeatureStdExtZihpm = 98,
RISCV_FeatureStdExtZimop = 99,
RISCV_FeatureStdExtZk = 100,
RISCV_FeatureStdExtZkn = 101,
RISCV_FeatureStdExtZknd = 102,
RISCV_FeatureStdExtZkne = 103,
RISCV_FeatureStdExtZknh = 104,
RISCV_FeatureStdExtZkr = 105,
RISCV_FeatureStdExtZks = 106,
RISCV_FeatureStdExtZksed = 107,
RISCV_FeatureStdExtZksh = 108,
RISCV_FeatureStdExtZkt = 109,
RISCV_FeatureStdExtZmmul = 110,
RISCV_FeatureStdExtZtso = 111,
RISCV_FeatureStdExtZvbb = 112,
RISCV_FeatureStdExtZvbc = 113,
RISCV_FeatureStdExtZve32f = 114,
RISCV_FeatureStdExtZve32x = 115,
RISCV_FeatureStdExtZve64d = 116,
RISCV_FeatureStdExtZve64f = 117,
RISCV_FeatureStdExtZve64x = 118,
RISCV_FeatureStdExtZvfbfmin = 119,
RISCV_FeatureStdExtZvfbfwma = 120,
RISCV_FeatureStdExtZvfh = 121,
RISCV_FeatureStdExtZvfhmin = 122,
RISCV_FeatureStdExtZvkb = 123,
RISCV_FeatureStdExtZvkg = 124,
RISCV_FeatureStdExtZvkn = 125,
RISCV_FeatureStdExtZvknc = 126,
RISCV_FeatureStdExtZvkned = 127,
RISCV_FeatureStdExtZvkng = 128,
RISCV_FeatureStdExtZvknha = 129,
RISCV_FeatureStdExtZvknhb = 130,
RISCV_FeatureStdExtZvks = 131,
RISCV_FeatureStdExtZvksc = 132,
RISCV_FeatureStdExtZvksed = 133,
RISCV_FeatureStdExtZvksg = 134,
RISCV_FeatureStdExtZvksh = 135,
RISCV_FeatureStdExtZvkt = 136,
RISCV_FeatureStdExtZvl32b = 137,
RISCV_FeatureStdExtZvl64b = 138,
RISCV_FeatureStdExtZvl128b = 139,
RISCV_FeatureStdExtZvl256b = 140,
RISCV_FeatureStdExtZvl512b = 141,
RISCV_FeatureStdExtZvl1024b = 142,
RISCV_FeatureStdExtZvl2048b = 143,
RISCV_FeatureStdExtZvl4096b = 144,
RISCV_FeatureStdExtZvl8192b = 145,
RISCV_FeatureStdExtZvl16384b = 146,
RISCV_FeatureStdExtZvl32768b = 147,
RISCV_FeatureStdExtZvl65536b = 148,
RISCV_FeatureTaggedGlobals = 149,
RISCV_FeatureTrailingSeqCstFence = 150,
RISCV_FeatureVendorXCValu = 151,
RISCV_FeatureVendorXCVbi = 152,
RISCV_FeatureVendorXCVbitmanip = 153,
RISCV_FeatureVendorXCVelw = 154,
RISCV_FeatureVendorXCVmac = 155,
RISCV_FeatureVendorXCVmem = 156,
RISCV_FeatureVendorXCVsimd = 157,
RISCV_FeatureVendorXSfvcp = 158,
RISCV_FeatureVendorXSfvfnrclipxfqf = 159,
RISCV_FeatureVendorXSfvfwmaccqqq = 160,
RISCV_FeatureVendorXSfvqmaccdod = 161,
RISCV_FeatureVendorXSfvqmaccqoq = 162,
RISCV_FeatureVendorXTHeadBa = 163,
RISCV_FeatureVendorXTHeadBb = 164,
RISCV_FeatureVendorXTHeadBs = 165,
RISCV_FeatureVendorXTHeadCmo = 166,
RISCV_FeatureVendorXTHeadCondMov = 167,
RISCV_FeatureVendorXTHeadFMemIdx = 168,
RISCV_FeatureVendorXTHeadMac = 169,
RISCV_FeatureVendorXTHeadMemIdx = 170,
RISCV_FeatureVendorXTHeadMemPair = 171,
RISCV_FeatureVendorXTHeadSync = 172,
RISCV_FeatureVendorXTHeadVdot = 173,
RISCV_FeatureVendorXVentanaCondOps = 174,
RISCV_TuneAUIPCADDIFusion = 175,
RISCV_TuneConditionalCompressedMoveFusion = 176,
RISCV_TuneDLenFactor2 = 177,
RISCV_TuneLDADDFusion = 178,
RISCV_TuneLUIADDIFusion = 179,
RISCV_TuneNoDefaultUnroll = 180,
RISCV_TuneNoOptimizedZeroStrideLoad = 181,
RISCV_TuneShiftedZExtWFusion = 182,
RISCV_TuneShortForwardBranchOpt = 183,
RISCV_TuneSiFive7 = 184,
RISCV_TuneVentanaVeyron = 185,
RISCV_TuneZExtHFusion = 186,
RISCV_TuneZExtWFusion = 187,
RISCV_NumSubtargetFeatures = 188
};
#endif // GET_SUBTARGETINFO_ENUM
arch/RISCV/RISCVGenSystemOperands.inc
+34192
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arch/RISCV/RISCVInstPrinter.c
+380 -758
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arch/RISCV/RISCVInstPrinter.h
+56 -11
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@@ -1,24 +1,69 @@
//===-- RISCVInstPrinter.h - Convert RISCV MCInst to asm syntax ---*- C++ -*--//
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* By Nguyen Anh Quynh <[email protected]>, 2013-2022, */
/* Rot127 <[email protected]> 2022-2023 */
/* Automatically translated source file from LLVM. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Only small edits allowed. */
/* For multiple similar edits, please create a Patch for the translator. */
/* Capstone's C++ file translator: */
/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
//===-- RISCVInstPrinter.h - Convert RISC-V MCInst to asm syntax --*- C++ -*--//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This class prints a RISCV MCInst to a .s file.
// This class prints a RISC-V MCInst to a .s file.
//
//===----------------------------------------------------------------------===//
#ifndef CS_RISCVINSTPRINTER_H
#define CS_RISCVINSTPRINTER_H
#ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVINSTPRINTER_H
#define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVINSTPRINTER_H
#include "../../MCInst.h"
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <capstone/platform.h>
#include "../../MCInstPrinter.h"
#include "../../cs_priv.h"
#include "../../SStream.h"
#include "RISCVBaseInfo.h"
#include "RISCVDisassemblerExtension.h"
void RISCV_printInst(MCInst *MI, SStream *O, void *info);
#define CONCAT(a, b) CONCAT_(a, b)
#define CONCAT_(a, b) a##_##b
void RISCV_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci);
void printBranchOperand(MCInst *MI, uint64_t Address, unsigned OpNo,
SStream *O);
void printCSRSystemRegister(MCInst *MI, unsigned OpNo, SStream *O);
void printFenceArg(MCInst *MI, unsigned OpNo, SStream *O);
void printFRMArg(MCInst *MI, unsigned OpNo, SStream *O);
void printFRMArgLegacy(MCInst *MI, unsigned OpNo, SStream *O);
void printFPImmOperand(MCInst *MI, unsigned OpNo, SStream *O);
void printZeroOffsetMemOp(MCInst *MI, unsigned OpNo, SStream *O);
void printVTypeI(MCInst *MI, unsigned OpNo, SStream *O);
void printVMaskReg(MCInst *MI, unsigned OpNo, SStream *O);
void printRlist(MCInst *MI, unsigned OpNo, SStream *O);
void printSpimm(MCInst *MI, unsigned OpNo, SStream *O);
void printRegReg(MCInst *MI, unsigned OpNo, SStream *O);
const char *RISCV_LLVM_getRegisterName(unsigned RegNo, unsigned AltIdx);
const char *getSysRegName(unsigned reg);
bool isCompressed(MCInst *MI);
typedef enum {
#define GET_ENUM_VALUES_SysReg
#include "RISCVGenCSSystemOperandsEnum.inc"
} SysRegValue;
#endif
arch/RISCV/RISCVLinkage.h
+17
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@@ -0,0 +1,17 @@
#ifndef CS_MIPS_LINKAGE_H
#define CS_MIPS_LINKAGE_H
#include "../../MCDisassembler.h"
#include "../../MCInst.h"
#include "../../MCRegisterInfo.h"
#include "../../SStream.h"
#include "capstone/capstone.h"
bool RISCV_LLVM_getInstruction(csh handle, const uint8_t *Bytes, size_t ByteLen,
MCInst *MI, uint16_t *Size, uint64_t Address,
void *Info);
const char *RISCV_LLVM_getRegisterName(unsigned RegNo, unsigned AltIdx);
void RISCV_LLVM_printInstruction(MCInst *MI, SStream *O,
void * /* MCRegisterInfo* */ info);
#endif // CS_MIPS_LINKAGE_H
arch/RISCV/RISCVMapping.c
+275 -238
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@@ -1,131 +1,289 @@
#include "capstone/cs_operand.h"
#include "capstone/riscv.h"
#include <stdint.h>
#include <float.h>
#include <math.h>
#ifdef CAPSTONE_HAS_RISCV
#include <stdio.h> // debug
#include <string.h>
#include "../../Mapping.h"
#include "../../utils.h"
#include "../../cs_simple_types.h"
#include "../../utils.h"
#include "RISCVMapping.h"
#include "RISCVInstPrinter.h"
#define GET_INSTRINFO_ENUM
#include "RISCVGenInstrInfo.inc"
#ifndef CAPSTONE_DIET
static const name_map reg_name_maps[] = {
{ RISCV_REG_INVALID, NULL },
#define GET_REGINFO_ENUM
#define GET_REGINFO_MC_DESC
#include "RISCVGenRegisterInfo.inc"
{ RISCV_REG_X0, "zero" }, { RISCV_REG_X1, "ra" },
{ RISCV_REG_X2, "sp" }, { RISCV_REG_X3, "gp" },
{ RISCV_REG_X4, "tp" }, { RISCV_REG_X5, "t0" },
{ RISCV_REG_X6, "t1" }, { RISCV_REG_X7, "t2" },
{ RISCV_REG_X8, "s0" }, { RISCV_REG_X9, "s1" },
{ RISCV_REG_X10, "a0" }, { RISCV_REG_X11, "a1" },
{ RISCV_REG_X12, "a2" }, { RISCV_REG_X13, "a3" },
{ RISCV_REG_X14, "a4" }, { RISCV_REG_X15, "a5" },
{ RISCV_REG_X16, "a6" }, { RISCV_REG_X17, "a7" },
{ RISCV_REG_X18, "s2" }, { RISCV_REG_X19, "s3" },
{ RISCV_REG_X20, "s4" }, { RISCV_REG_X21, "s5" },
{ RISCV_REG_X22, "s6" }, { RISCV_REG_X23, "s7" },
{ RISCV_REG_X24, "s8" }, { RISCV_REG_X25, "s9" },
{ RISCV_REG_X26, "s10" }, { RISCV_REG_X27, "s11" },
{ RISCV_REG_X28, "t3" }, { RISCV_REG_X29, "t4" },
{ RISCV_REG_X30, "t5" }, { RISCV_REG_X31, "t6" },
{ RISCV_REG_F0_32, "ft0" }, { RISCV_REG_F0_64, "ft0" },
{ RISCV_REG_F1_32, "ft1" }, { RISCV_REG_F1_64, "ft1" },
{ RISCV_REG_F2_32, "ft2" }, { RISCV_REG_F2_64, "ft2" },
{ RISCV_REG_F3_32, "ft3" }, { RISCV_REG_F3_64, "ft3" },
{ RISCV_REG_F4_32, "ft4" }, { RISCV_REG_F4_64, "ft4" },
{ RISCV_REG_F5_32, "ft5" }, { RISCV_REG_F5_64, "ft5" },
{ RISCV_REG_F6_32, "ft6" }, { RISCV_REG_F6_64, "ft6" },
{ RISCV_REG_F7_32, "ft7" }, { RISCV_REG_F7_64, "ft7" },
{ RISCV_REG_F8_32, "fs0" }, { RISCV_REG_F8_64, "fs0" },
{ RISCV_REG_F9_32, "fs1" }, { RISCV_REG_F9_64, "fs1" },
{ RISCV_REG_F10_32, "fa0" }, { RISCV_REG_F10_64, "fa0" },
{ RISCV_REG_F11_32, "fa1" }, { RISCV_REG_F11_64, "fa1" },
{ RISCV_REG_F12_32, "fa2" }, { RISCV_REG_F12_64, "fa2" },
{ RISCV_REG_F13_32, "fa3" }, { RISCV_REG_F13_64, "fa3" },
{ RISCV_REG_F14_32, "fa4" }, { RISCV_REG_F14_64, "fa4" },
{ RISCV_REG_F15_32, "fa5" }, { RISCV_REG_F15_64, "fa5" },
{ RISCV_REG_F16_32, "fa6" }, { RISCV_REG_F16_64, "fa6" },
{ RISCV_REG_F17_32, "fa7" }, { RISCV_REG_F17_64, "fa7" },
{ RISCV_REG_F18_32, "fs2" }, { RISCV_REG_F18_64, "fs2" },
{ RISCV_REG_F19_32, "fs3" }, { RISCV_REG_F19_64, "fs3" },
{ RISCV_REG_F20_32, "fs4" }, { RISCV_REG_F20_64, "fs4" },
{ RISCV_REG_F21_32, "fs5" }, { RISCV_REG_F21_64, "fs5" },
{ RISCV_REG_F22_32, "fs6" }, { RISCV_REG_F22_64, "fs6" },
{ RISCV_REG_F23_32, "fs7" }, { RISCV_REG_F23_64, "fs7" },
{ RISCV_REG_F24_32, "fs8" }, { RISCV_REG_F24_64, "fs8" },
{ RISCV_REG_F25_32, "fs9" }, { RISCV_REG_F25_64, "fs9" },
{ RISCV_REG_F26_32, "fs10" }, { RISCV_REG_F26_64, "fs10" },
{ RISCV_REG_F27_32, "fs11" }, { RISCV_REG_F27_64, "fs11" },
{ RISCV_REG_F28_32, "ft8" }, { RISCV_REG_F28_64, "ft8" },
{ RISCV_REG_F29_32, "ft9" }, { RISCV_REG_F29_64, "ft9" },
{ RISCV_REG_F30_32, "ft10" }, { RISCV_REG_F30_64, "ft10" },
{ RISCV_REG_F31_32, "ft11" }, { RISCV_REG_F31_64, "ft11" },
};
#endif
#include "RISCVInstPrinter.h"
const char *RISCV_reg_name(csh handle, unsigned int reg)
{
#ifndef CAPSTONE_DIET
if (reg >= RISCV_REG_ENDING)
return NULL;
return reg_name_maps[reg].name;
#else
return NULL;
#endif
int syntax_opt = ((cs_struct *)(uintptr_t)handle)->syntax;
if (syntax_opt & CS_OPT_SYNTAX_NOREGNAME) {
return RISCV_LLVM_getRegisterName(reg, RISCV_NoRegAltName);
}
return RISCV_LLVM_getRegisterName(reg, RISCV_ABIRegAltName);
}
static const insn_map insns[] = {
// dummy item
{ 0,
0,
#ifndef CAPSTONE_DIET
{ 0 },
{ 0 },
{ 0 },
0,
0
#endif
},
#include "RISCVMappingInsn.inc"
#include "RISCVGenCSMappingInsn.inc"
};
#ifndef CAPSTONE_DIET
static const map_insn_ops insn_operands[] = {
#include "RISCVMappingInsnOp.inc"
#include "RISCVGenCSMappingInsnOp.inc"
};
#endif
void RISCV_add_cs_detail(MCInst *MI, unsigned OpNum)
void RISCV_add_cs_detail_0(MCInst *MI, riscv_op_group opgroup, unsigned OpNum)
{
if (!detail_is_set(MI))
return;
// are not "true" arguments and has no Capstone equivalent
if (opgroup == RISCV_OP_GROUP_FRMArg ||
opgroup == RISCV_OP_GROUP_FRMArgLegacy)
return;
if (opgroup == RISCV_OP_GROUP_FPImmOperand) {
unsigned Imm = (unsigned)MCInst_getOperand(MI, OpNum)->ImmVal;
cs_riscv_op *op = RISCV_get_detail_op_at(MI, OpNum);
op->type = RISCV_OP_FP;
op->access = (cs_ac_type)map_get_op_access(MI, OpNum);
switch (Imm) {
case 1: // min
switch (MI->Opcode) {
case RISCV_FLI_S:
op->dimm = (double)FLT_MIN;
break;
case RISCV_FLI_D:
op->dimm = (double)DBL_MIN;
break;
case RISCV_FLI_H:
op->dimm = 6.103515625e-05;
break;
default:
op->dimm = 0.0;
break;
}
break;
case 30: // inf
op->dimm = INFINITY;
break;
case 31: // nan
op->dimm = NAN;
break;
default:
op->dimm = (double)getFPImm(Imm);
break;
}
RISCV_inc_op_count(MI);
return;
}
cs_riscv_op *op = RISCV_get_detail_op_at(MI, OpNum);
op->type = (riscv_op_type)map_get_op_type(MI, OpNum);
op->access = (cs_ac_type)map_get_op_access(MI, OpNum);
switch (map_get_op_type(MI, OpNum)) {
case CS_OP_REG:
op->reg = MCInst_getOperand(MI, OpNum)->RegVal;
break;
case CS_OP_MEM:
op->mem.base = 0;
op->mem.disp = MCInst_getOperand(MI, OpNum)->ImmVal;
break;
case CS_OP_IMM: {
uint64_t val = MCInst_getOperand(MI, OpNum)->ImmVal;
if (opgroup != RISCV_OP_GROUP_CSRSystemRegister) {
op->imm = val;
if (opgroup == RISCV_OP_GROUP_BranchOperand) {
op->imm += MI->address;
}
} else /* system register read-write */ {
op->type = RISCV_OP_CSR;
op->csr = val;
// CSR instruction always read-writes the system operand
op->access = CS_AC_READ_WRITE;
}
break;
}
case CS_OP_MEM_REG:
op->type = (riscv_op_type)CS_OP_MEM;
op->mem.base = MCInst_getOperand(MI, OpNum)->RegVal;
break;
case CS_OP_MEM_IMM:
// fill in the disp in the last operand
op = RISCV_get_detail_op_at(MI, OpNum - 1);
op->type = (riscv_op_type)CS_OP_MEM;
op->mem.disp = MCInst_getOperand(MI, OpNum)->ImmVal;
RISCV_dec_op_count(
MI); // don't increase the count, cancel the coming increment
break;
case CS_OP_INVALID:
break;
default: {
CS_ASSERT(0 && "unhandled operand type");
}
}
RISCV_inc_op_count(MI);
}
static inline void RISCV_add_adhoc_groups(MCInst *MI);
void RISCV_add_groups(MCInst *MI)
{
if (!detail_is_set(MI))
return;
cs_op_type op_type = map_get_op_type(MI, OpNum);
get_detail(MI)->groups_count = 0;
if (op_type == CS_OP_IMM) {
RISCV_get_detail_op(MI, 0)->type = RISCV_OP_IMM;
RISCV_get_detail_op(MI, 0)->imm = MCInst_getOpVal(MI, OpNum);
RISCV_get_detail_op(MI, 0)->access =
map_get_op_access(MI, OpNum);
RISCV_inc_op_count(MI);
} else if (op_type == CS_OP_REG) {
RISCV_get_detail_op(MI, 0)->type = RISCV_OP_REG;
RISCV_get_detail_op(MI, 0)->reg = MCInst_getOpVal(MI, OpNum);
RISCV_get_detail_op(MI, 0)->access =
map_get_op_access(MI, OpNum);
RISCV_inc_op_count(MI);
} else {
CS_ASSERT(0 && "Op type not handled.");
#ifndef CAPSTONE_DIET
int i = 0;
while (insns[MI->Opcode].groups[i] != 0) {
add_group(MI, insns[MI->Opcode].groups[i]);
i++;
}
#endif
RISCV_add_adhoc_groups(MI);
}
enum {
#define GET_ENUM_VALUES_RISCVOpcode
#include "RISCVGenCSSystemOperandsEnum.inc"
};
static inline void RISCV_add_privileged_group(MCInst *MI)
{
const uint8_t *bytes = MI->flat_insn->bytes;
uint8_t opcode = bytes[0] & 0x80;
// no privileged instruction has a major opcode other than SYSTEM
if (opcode != RISCV_RISCVOPCODE_SYSTEM) {
return;
}
uint8_t func3 = (bytes[1] >> 4) & 0x7;
// no privileged instruction has a minor opcode other than PRIV or PRIVM
if (func3 != 0 && func3 != 0x4) {
return;
}
uint16_t func12 = readBytes16(MI, &(bytes[2])) >> 4;
// ecall and ebreak has SYSTEM and PRIV but aren't privileged
if (func12 == 0 || func12 == 1) {
return;
}
uint8_t func6 = func12 >> 6;
// a subspace under extension-defined custom SYSTEM instructions that is not privileged
if (func6 == 0x23 || func6 == 0x33) {
return;
}
add_group(MI, RISCV_GRP_PRIVILEGE);
}
static inline void RISCV_add_interrupt_group(MCInst *MI)
{
if (MI->Opcode == RISCV_ECALL || MI->Opcode == RISCV_EBREAK) {
add_group(MI, RISCV_GRP_INT);
}
}
static inline void RISCV_add_interrupt_ret_group(MCInst *MI)
{
if (MI->Opcode == RISCV_MRET || MI->Opcode == RISCV_SRET) {
add_group(MI, RISCV_GRP_IRET);
}
}
// calls are implemented in RISCV as plain jumps that happen to set a link register containing the return address
// but this link register could be given as the null register x0, discarding the return address and making them jumps
static inline void RISCV_add_call_group(MCInst *MI)
{
if (MI->Opcode == RISCV_JAL || MI->Opcode == RISCV_JALR) {
cs_riscv_op *op = RISCV_get_detail_op_at(MI, 0);
if ((op->type == (riscv_op_type)CS_OP_REG) &&
op->reg != RISCV_REG_X0 && (op->access & CS_AC_WRITE)) {
add_group(MI, RISCV_GRP_CALL);
}
if (MI->Opcode == RISCV_JAL) {
add_group(MI, RISCV_GRP_BRANCH_RELATIVE);
}
}
}
// returns are implemented in RISCV as a plain indirect jump that happen to reference the return address register ra == x1
static inline void RISCV_add_ret_group(MCInst *MI)
{
if (MI->Opcode == RISCV_C_JR) {
cs_riscv_op *op = RISCV_get_detail_op_at(MI, 0);
if ((op->type == (riscv_op_type)CS_OP_REG) &&
op->reg == RISCV_REG_X1) {
add_group(MI, RISCV_GRP_RET);
} else {
add_group(MI, RISCV_GRP_JUMP);
}
}
}
static inline void RISCV_add_adhoc_groups(MCInst *MI)
{
RISCV_add_privileged_group(MI);
RISCV_add_interrupt_group(MI);
RISCV_add_interrupt_ret_group(MI);
RISCV_add_call_group(MI);
RISCV_add_ret_group(MI);
}
// for weird reasons some instructions end up with valid operands that are
// interspersed with invalid operands, i.e. the operands array is an "island"
// of valid operands with invalid gaps between them, this function will compactify
// all the valid operands and pad the rest of the array to invalid
void RISCV_compact_operands(MCInst *MI)
{
if (!detail_is_set(MI))
return;
cs_riscv_op *ops = RISCV_get_detail(MI)->operands;
unsigned int write_pos = 0;
// Move valid elements to front
for (unsigned int read_pos = 0; read_pos < NUM_RISCV_OPS; read_pos++) {
if (ops[read_pos].type != (riscv_op_type)CS_OP_INVALID) {
if (write_pos != read_pos) {
ops[write_pos] = ops[read_pos];
}
write_pos++;
}
}
// fill the rest, if any, with invalid
memset((void *)(&ops[write_pos]), CS_OP_INVALID,
(NUM_RISCV_OPS - write_pos) * sizeof(cs_riscv_op));
}
// some RISC-V instructions have only 2 apparent operands, one of them is read-write
// the actual operand information for those instruction should have 3 operands, the first and second are the same operand,
// but once with read and once write access
// when those instructions are disassembled only the operand entry with the read access is used,
// and therefore the read-write operand is wrongly classified as only-read
// this logic tries to correct that
void RISCV_add_missing_write_access(MCInst *MI)
{
if (!detail_is_set(MI))
return;
if (!isCompressed(MI))
return;
cs_riscv *riscv_details = RISCV_get_detail(MI);
cs_riscv_op *ops = riscv_details->operands;
// make the detection condition as specific as possible
// so it doesn't accidentally trigger for other cases
if (riscv_details->op_count == 2 && ops[0].type == RISCV_OP_INVALID &&
ops[1].type == RISCV_OP_REG && ops[1].access == CS_AC_READ) {
ops[1].access |= CS_AC_WRITE;
}
}
@@ -167,10 +325,10 @@ void RISCV_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
}
}
static const name_map insn_name_maps[] = {
{ RISCV_INS_INVALID, NULL },
static const char *const insn_name_maps[] = {
/*RISCV_INS_INVALID:*/ NULL,
#include "RISCVGenInsnNameMaps.inc"
#include "RISCVGenCSMappingInsnName.inc"
};
const char *RISCV_insn_name(csh handle, unsigned int id)
@@ -179,7 +337,7 @@ const char *RISCV_insn_name(csh handle, unsigned int id)
if (id >= RISCV_INS_ENDING)
return NULL;
return insn_name_maps[id].name;
return insn_name_maps[id];
#else
return NULL;
#endif
@@ -197,30 +355,9 @@ static const name_map group_name_maps[] = {
{ RISCV_GRP_PRIVILEGE, "privileged" },
{ RISCV_GRP_BRANCH_RELATIVE, "branch_relative" },
// architecture specific
{ RISCV_GRP_ISRV32, "isrv32" },
{ RISCV_GRP_ISRV64, "isrv64" },
{ RISCV_GRP_HASSTDEXTA, "hasStdExtA" },
{ RISCV_GRP_HASSTDEXTC, "hasStdExtC" },
{ RISCV_GRP_HASSTDEXTD, "hasStdExtD" },
{ RISCV_GRP_HASSTDEXTF, "hasStdExtF" },
{ RISCV_GRP_HASSTDEXTM, "hasStdExtM" },
// architecture specific
#include "RISCVGenCSFeatureName.inc"
/*
{ RISCV_GRP_ISRVA, "isrva" },
{ RISCV_GRP_ISRVC, "isrvc" },
{ RISCV_GRP_ISRVD, "isrvd" },
{ RISCV_GRP_ISRVCD, "isrvcd" },
{ RISCV_GRP_ISRVF, "isrvf" },
{ RISCV_GRP_ISRV32C, "isrv32c" },
{ RISCV_GRP_ISRV32CF, "isrv32cf" },
{ RISCV_GRP_ISRVM, "isrvm" },
{ RISCV_GRP_ISRV64A, "isrv64a" },
{ RISCV_GRP_ISRV64C, "isrv64c" },
{ RISCV_GRP_ISRV64D, "isrv64d" },
{ RISCV_GRP_ISRV64F, "isrv64f" },
{ RISCV_GRP_ISRV64M, "isrv64m" }
*/
{ RISCV_GRP_ENDING, NULL }
};
#endif
@@ -229,8 +366,10 @@ const char *RISCV_group_name(csh handle, unsigned int id)
{
#ifndef CAPSTONE_DIET
// verify group id
// if past the end
if (id >= RISCV_GRP_ENDING ||
(id > RISCV_GRP_BRANCH_RELATIVE && id < RISCV_GRP_ISRV32))
// or in the encoding gap between generic groups and arch-specific groups
(id > RISCV_GRP_BRANCH_RELATIVE && id < RISCV_FEATURE_HASSTDEXTI))
return NULL;
return id2name(group_name_maps, ARR_SIZE(group_name_maps), id);
#else
@@ -239,126 +378,24 @@ const char *RISCV_group_name(csh handle, unsigned int id)
}
// map instruction name to public instruction ID
riscv_reg RISCV_map_insn(const char *name)
riscv_insn RISCV_map_insn(const char *name)
{
// handle special alias first
unsigned int i;
// NOTE: skip first NULL name in insn_name_maps
i = name2id(&insn_name_maps[1], ARR_SIZE(insn_name_maps) - 1, name);
return (i != -1) ? i : RISCV_REG_INVALID;
for (i = 1; i < ARR_SIZE(insn_name_maps); i++) {
if (!strcmp(name, insn_name_maps[i]))
return i;
}
return RISCV_INS_INVALID;
}
// map internal raw register to 'public' register
riscv_reg RISCV_map_register(unsigned int r)
void RISCV_init(MCRegisterInfo *MRI)
{
static const unsigned int map[] = {
0,
RISCV_REG_X0,
RISCV_REG_X1,
RISCV_REG_X2,
RISCV_REG_X3,
RISCV_REG_X4,
RISCV_REG_X5,
RISCV_REG_X6,
RISCV_REG_X7,
RISCV_REG_X8,
RISCV_REG_X9,
RISCV_REG_X10,
RISCV_REG_X11,
RISCV_REG_X12,
RISCV_REG_X13,
RISCV_REG_X14,
RISCV_REG_X15,
RISCV_REG_X16,
RISCV_REG_X17,
RISCV_REG_X18,
RISCV_REG_X19,
RISCV_REG_X20,
RISCV_REG_X21,
RISCV_REG_X22,
RISCV_REG_X23,
RISCV_REG_X24,
RISCV_REG_X25,
RISCV_REG_X26,
RISCV_REG_X27,
RISCV_REG_X28,
RISCV_REG_X29,
RISCV_REG_X30,
RISCV_REG_X31,
RISCV_REG_F0_32,
RISCV_REG_F0_64,
RISCV_REG_F1_32,
RISCV_REG_F1_64,
RISCV_REG_F2_32,
RISCV_REG_F2_64,
RISCV_REG_F3_32,
RISCV_REG_F3_64,
RISCV_REG_F4_32,
RISCV_REG_F4_64,
RISCV_REG_F5_32,
RISCV_REG_F5_64,
RISCV_REG_F6_32,
RISCV_REG_F6_64,
RISCV_REG_F7_32,
RISCV_REG_F7_64,
RISCV_REG_F8_32,
RISCV_REG_F8_64,
RISCV_REG_F9_32,
RISCV_REG_F9_64,
RISCV_REG_F10_32,
RISCV_REG_F10_64,
RISCV_REG_F11_32,
RISCV_REG_F11_64,
RISCV_REG_F12_32,
RISCV_REG_F12_64,
RISCV_REG_F13_32,
RISCV_REG_F13_64,
RISCV_REG_F14_32,
RISCV_REG_F14_64,
RISCV_REG_F15_32,
RISCV_REG_F15_64,
RISCV_REG_F16_32,
RISCV_REG_F16_64,
RISCV_REG_F17_32,
RISCV_REG_F17_64,
RISCV_REG_F18_32,
RISCV_REG_F18_64,
RISCV_REG_F19_32,
RISCV_REG_F19_64,
RISCV_REG_F20_32,
RISCV_REG_F20_64,
RISCV_REG_F21_32,
RISCV_REG_F21_64,
RISCV_REG_F22_32,
RISCV_REG_F22_64,
RISCV_REG_F23_32,
RISCV_REG_F23_64,
RISCV_REG_F24_32,
RISCV_REG_F24_64,
RISCV_REG_F25_32,
RISCV_REG_F25_64,
RISCV_REG_F26_32,
RISCV_REG_F26_64,
RISCV_REG_F27_32,
RISCV_REG_F27_64,
RISCV_REG_F28_32,
RISCV_REG_F28_64,
RISCV_REG_F29_32,
RISCV_REG_F29_64,
RISCV_REG_F30_32,
RISCV_REG_F30_64,
RISCV_REG_F31_32,
RISCV_REG_F31_64,
};
if (r < ARR_SIZE(map))
return map[r];
// cannot find this register
return 0;
MCRegisterInfo_InitMCRegisterInfo(MRI, RISCVRegDesc, RISCV_REG_ENDING,
0, 0, RISCVMCRegisterClasses,
ARR_SIZE(RISCVMCRegisterClasses), 0,
0, RISCVRegDiffLists, 0,
RISCVSubRegIdxLists,
ARR_SIZE(RISCVSubRegIdxLists), 0);
}
#endif
arch/RISCV/RISCVMapping.h
+14 -4
View File
@@ -3,6 +3,11 @@
#define CS_RISCV_MAP_H
#include "../../include/capstone/capstone.h"
#include "../../cs_priv.h"
typedef enum {
#include "RISCVGenCSOpGroup.inc"
} riscv_op_group;
// given internal insn id, return public instruction info
void RISCV_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
@@ -13,12 +18,17 @@ const char *RISCV_group_name(csh handle, unsigned int id);
const char *RISCV_reg_name(csh handle, unsigned int reg);
void RISCV_add_cs_detail(MCInst *MI, unsigned OpNum);
void RISCV_add_cs_detail_0(MCInst *MI, riscv_op_group opgroup, unsigned OpNum);
void RISCV_add_groups(MCInst *MI);
void RISCV_compact_operands(MCInst *MI);
void RISCV_add_missing_write_access(MCInst *MI);
// map instruction name to instruction ID
riscv_reg RISCV_map_insn(const char *name);
riscv_insn RISCV_map_insn(const char *name);
// map internal raw register to 'public' register
riscv_reg RISCV_map_register(unsigned int r);
void RISCV_init(MCRegisterInfo *MRI);
#endif
arch/RISCV/RISCVMappingInsn.inc
-1635
View File
File diff suppressed because it is too large Load Diff
arch/RISCV/RISCVMappingInsnOp.inc
-2438
View File
File diff suppressed because it is too large Load Diff
arch/RISCV/RISCVModule.c
+3 -3
View File
@@ -6,10 +6,10 @@
#include "../../utils.h"
#include "../../MCRegisterInfo.h"
#include "RISCVDisassembler.h"
#include "RISCVInstPrinter.h"
#include "RISCVMapping.h"
#include "RISCVModule.h"
#include "RISCVLinkage.h"
cs_err RISCV_global_init(cs_struct *ud)
{
@@ -17,10 +17,10 @@ cs_err RISCV_global_init(cs_struct *ud)
mri = cs_mem_malloc(sizeof(*mri));
RISCV_init(mri);
ud->printer = RISCV_printInst;
ud->printer = RISCV_LLVM_printInstruction;
ud->printer_info = mri;
ud->getinsn_info = mri;
ud->disasm = RISCV_getInstruction;
ud->disasm = RISCV_LLVM_getInstruction;
ud->post_printer = NULL;
ud->reg_name = RISCV_reg_name;
bindings/python/capstone/__init__.py
+104 -4
View File
@@ -106,7 +106,56 @@ __all__ = [
'CS_MODE_BPF_EXTENDED',
'CS_MODE_RISCV32',
'CS_MODE_RISCV64',
'CS_MODE_RISCVC',
'CS_MODE_RISCV_C',
'CS_MODE_RISCV_FD',
'CS_MODE_RISCV_F',
'CS_MODE_RISCV_D',
'CS_MODE_RISCV_V',
'CS_MODE_RISCV_ZFINX',
'CS_MODE_RISCV_ZDINX',
'CS_MODE_RISCV_ZHINX',
'CS_MODE_RISCV_ZHINXMIN',
'CS_MODE_RISCV_ZCMP_ZCMT_ZCE',
'CS_MODE_RISCV_ZCE',
'CS_MODE_RISCV_ZCMP',
'CS_MODE_RISCV_ZCMT',
'CS_MODE_RISCV_ZICFISS',
'CS_MODE_RISCV_EXPERIMENTAL_ZICFISS',
'CS_MODE_RISCV_E',
'CS_MODE_RISCV_A',
'CS_MODE_RISCV_COREV',
'CS_MODE_RISCV_XCVALU',
'CS_MODE_RISCV_XCVBI',
'CS_MODE_RISCV_XCVBITMANIP',
'CS_MODE_RISCV_XCVELW',
'CS_MODE_RISCV_XCVMAC',
'CS_MODE_RISCV_XCVMEM',
'CS_MODE_RISCV_XCVSIMD',
'CS_MODE_RISCV_THEAD',
'CS_MODE_RISCV_XTHEADBA',
'CS_MODE_RISCV_XTHEADBS',
'CS_MODE_RISCV_XTHEADCMO',
'CS_MODE_RISCV_XTHEADCONDMOV',
'CS_MODE_RISCV_XTHEADFMEMIDX',
'CS_MODE_RISCV_XTHEADMAC',
'CS_MODE_RISCV_XTHEADMEMIDX',
'CS_MODE_RISCV_XTHEADMEMPAIR',
'CS_MODE_RISCV_XTHEADSYNC',
'CS_MODE_RISCV_XTHEADVDOT',
'CS_MODE_RISCV_SIFIVE',
'CS_MODE_RISCV_XSFVCP',
'CS_MODE_RISCV_XSFVFNRCLIPXFQF',
'CS_MODE_RISCV_XSFVFWMACCQQQ',
'CS_MODE_RISCV_XSFVQMACCDOD',
'CS_MODE_RISCV_XSFVQMACCQOQ',
'CS_MODE_RISCV_BITMANIP',
'CS_MODE_RISCV_ZBA',
'CS_MODE_RISCV_ZBB',
'CS_MODE_RISCV_ZBC',
'CS_MODE_RISCV_ZBKB',
'CS_MODE_RISCV_ZBKC',
'CS_MODE_RISCV_ZBKX',
'CS_MODE_RISCV_ZBS',
'CS_MODE_MOS65XX_6502',
'CS_MODE_MOS65XX_65C02',
'CS_MODE_MOS65XX_W65C02',
@@ -159,6 +208,7 @@ __all__ = [
'CS_OPT_SYNTAX_MOTOROLA',
'CS_OPT_SYNTAX_CS_REG_ALIAS',
'CS_OPT_SYNTAX_NO_DOLLAR',
'CS_OPT_SYNTAX_NO_ALIAS_TEXT',
'CS_OPT_DETAIL',
'CS_OPT_DETAIL_REAL',
@@ -332,7 +382,7 @@ CS_MODE_MIPS64R5 = 1 << 16 # Mips64r5 ISA Support
CS_MODE_MIPS64R6 = 1 << 17 # Mips64r6 ISA Support
CS_MODE_OCTEON = 1 << 18 # Octeon cnMIPS Support
CS_MODE_OCTEONP = 1 << 19 # Octeon+ cnMIPS Support
CS_MODE_NANOMIPS = 1 << 20 # Generic nanomips
CS_MODE_NANOMIPS = 1 << 20 # Generic nanomips
CS_MODE_NMS1 = ((1 << 21) | CS_MODE_NANOMIPS) # nanoMips NMS1
CS_MODE_I7200 = ((1 << 22) | CS_MODE_NANOMIPS) # nanoMips I7200
CS_MODE_MIPS_NOFLOAT = 1 << 23 # Disable floating points ops
@@ -353,7 +403,56 @@ CS_MODE_BPF_CLASSIC = 0 # Classic BPF mode (default)
CS_MODE_BPF_EXTENDED = (1 << 0) # Extended BPF mode
CS_MODE_RISCV32 = (1 << 0) # RISCV32 mode
CS_MODE_RISCV64 = (1 << 1) # RISCV64 mode
CS_MODE_RISCVC = (1 << 2) # RISCV compressed mode
CS_MODE_RISCV_C = 1 << 2 # RISCV compressed instructure mode
CS_MODE_RISCV_FD = 1 << 3
CS_MODE_RISCV_F = CS_MODE_RISCV_FD
CS_MODE_RISCV_D = CS_MODE_RISCV_FD
CS_MODE_RISCV_V = 1 << 4
CS_MODE_RISCV_ZFINX = 1 << 5
CS_MODE_RISCV_ZDINX = CS_MODE_RISCV_ZFINX
CS_MODE_RISCV_ZHINX = CS_MODE_RISCV_ZFINX
CS_MODE_RISCV_ZHINXMIN = CS_MODE_RISCV_ZFINX
CS_MODE_RISCV_ZCMP_ZCMT_ZCE = 1 << 6
CS_MODE_RISCV_ZCE = CS_MODE_RISCV_ZCMP_ZCMT_ZCE
CS_MODE_RISCV_ZCMP =CS_MODE_RISCV_ZCMP_ZCMT_ZCE
CS_MODE_RISCV_ZCMT = CS_MODE_RISCV_ZCMP_ZCMT_ZCE
CS_MODE_RISCV_ZICFISS = 1 << 7
CS_MODE_RISCV_EXPERIMENTAL_ZICFISS = CS_MODE_RISCV_ZICFISS
CS_MODE_RISCV_E = 1 << 8
CS_MODE_RISCV_A = 1 << 9
CS_MODE_RISCV_COREV = 1 << 10
CS_MODE_RISCV_XCVALU = CS_MODE_RISCV_COREV
CS_MODE_RISCV_XCVBI = CS_MODE_RISCV_COREV
CS_MODE_RISCV_XCVBITMANIP = CS_MODE_RISCV_COREV
CS_MODE_RISCV_XCVELW = CS_MODE_RISCV_COREV
CS_MODE_RISCV_XCVMAC = CS_MODE_RISCV_COREV
CS_MODE_RISCV_XCVMEM = CS_MODE_RISCV_COREV
CS_MODE_RISCV_XCVSIMD = CS_MODE_RISCV_COREV
CS_MODE_RISCV_THEAD = 1 << 11
CS_MODE_RISCV_XTHEADBA = CS_MODE_RISCV_THEAD
CS_MODE_RISCV_XTHEADBS = CS_MODE_RISCV_THEAD
CS_MODE_RISCV_XTHEADCMO = CS_MODE_RISCV_THEAD
CS_MODE_RISCV_XTHEADCONDMOV = CS_MODE_RISCV_THEAD
CS_MODE_RISCV_XTHEADFMEMIDX = CS_MODE_RISCV_THEAD
CS_MODE_RISCV_XTHEADMAC = CS_MODE_RISCV_THEAD
CS_MODE_RISCV_XTHEADMEMIDX = CS_MODE_RISCV_THEAD
CS_MODE_RISCV_XTHEADMEMPAIR = CS_MODE_RISCV_THEAD
CS_MODE_RISCV_XTHEADSYNC = CS_MODE_RISCV_THEAD
CS_MODE_RISCV_XTHEADVDOT = CS_MODE_RISCV_THEAD
CS_MODE_RISCV_SIFIVE = 1 << 12
CS_MODE_RISCV_XSFVCP = CS_MODE_RISCV_SIFIVE
CS_MODE_RISCV_XSFVFNRCLIPXFQF = CS_MODE_RISCV_SIFIVE
CS_MODE_RISCV_XSFVFWMACCQQQ = CS_MODE_RISCV_SIFIVE
CS_MODE_RISCV_XSFVQMACCDOD = CS_MODE_RISCV_SIFIVE
CS_MODE_RISCV_XSFVQMACCQOQ = CS_MODE_RISCV_SIFIVE
CS_MODE_RISCV_BITMANIP = 1 << 13
CS_MODE_RISCV_ZBA = 1 << 14
CS_MODE_RISCV_ZBB = 1 << 15
CS_MODE_RISCV_ZBC = 1 << 16
CS_MODE_RISCV_ZBKB = 1 << 17
CS_MODE_RISCV_ZBKC = 1 << 18
CS_MODE_RISCV_ZBKX = 1 << 19
CS_MODE_RISCV_ZBS = 1 << 20
CS_MODE_MOS65XX_6502 = (1 << 1) # MOS65XXX MOS 6502
CS_MODE_MOS65XX_65C02 = (1 << 2) # MOS65XXX WDC 65c02
CS_MODE_MOS65XX_W65C02 = (1 << 3) # MOS65XXX WDC W65c02
@@ -461,6 +560,7 @@ CS_OPT_SYNTAX_MOTOROLA = (1 << 6) # MOS65XX use $ as hex prefix
CS_OPT_SYNTAX_CS_REG_ALIAS = (1 << 7) # Prints common register alias which are not defined in LLVM (ARM: r9 = sb etc.)
CS_OPT_SYNTAX_PERCENT = (1 << 8) # Prints the % in front of PPC registers.
CS_OPT_SYNTAX_NO_DOLLAR = (1 << 9) # Does not print the $ in front of Mips, LoongArch registers.
CS_OPT_SYNTAX_NO_ALIAS_TEXT = (1 << 10) # Does not print an instruction's alias test if the instruction is an alias
CS_OPT_DETAIL_REAL = (1 << 1) # If enabled, always sets the real instruction detail.Even if the instruction is an alias.
# Capstone error type
@@ -1468,7 +1568,7 @@ def debug():
"m680x": CS_ARCH_M680X, 'evm': CS_ARCH_EVM, 'mos65xx': CS_ARCH_MOS65XX,
'bpf': CS_ARCH_BPF, 'riscv': CS_ARCH_RISCV, 'tricore': CS_ARCH_TRICORE,
'wasm': CS_ARCH_WASM, 'sh': CS_ARCH_SH, 'alpha': CS_ARCH_ALPHA,
'hppa': CS_ARCH_HPPA, 'loongarch': CS_ARCH_LOONGARCH, 'xtensa': CS_ARCH_XTENSA,
'hppa': CS_ARCH_HPPA, 'loongarch': CS_ARCH_LOONGARCH, 'xtensa': CS_ARCH_XTENSA,
'arc': CS_ARCH_ARC
}
bindings/python/capstone/riscv.py
+27 -13
View File
@@ -1,34 +1,44 @@
# Capstone Python bindings, by Nguyen Anh Quynnh <[email protected]>
import ctypes
from . import copy_ctypes_list
from .riscv_const import *
# define the API
class RISCVOpMem(ctypes.Structure):
_fields_ = (
('base', ctypes.c_uint),
('disp', ctypes.c_int64),
("base", ctypes.c_uint),
("disp", ctypes.c_int64),
)
class RISCVOpValue(ctypes.Union):
_fields_ = (
('reg', ctypes.c_uint),
('imm', ctypes.c_int64),
('mem', RISCVOpMem),
("reg", ctypes.c_uint),
("imm", ctypes.c_int64),
("dimm", ctypes.c_double),
("mem", RISCVOpMem),
("csr", ctypes.c_uint16),
)
class RISCVOp(ctypes.Structure):
_fields_ = (
('type', ctypes.c_uint),
('value', RISCVOpValue),
('access', ctypes.c_uint),
("type", ctypes.c_uint),
("value", RISCVOpValue),
("access", ctypes.c_uint),
)
@property
def imm(self):
return self.value.imm
@property
def dimm(self):
return self.value.dimm
@property
def reg(self):
return self.value.reg
@@ -37,14 +47,18 @@ class RISCVOp(ctypes.Structure):
def mem(self):
return self.value.mem
@property
def csr(self):
return self.value.csr
class CsRISCV(ctypes.Structure):
_fields_ = (
('need_effective_addr', ctypes.c_bool),
('op_count', ctypes.c_uint8),
('operands', RISCVOp * 8),
("need_effective_addr", ctypes.c_bool),
("op_count", ctypes.c_uint8),
("operands", RISCVOp * 8),
)
def get_arch_info(a):
return (a.need_effective_addr, copy_ctypes_list(a.operands[:a.op_count]))
def get_arch_info(a):
return (a.need_effective_addr, copy_ctypes_list(a.operands[: a.op_count]))
bindings/python/capstone/riscv_const.py
+3033 -381
View File
File diff suppressed because it is too large Load Diff
bindings/python/cstest_py/src/cstest_py/compare.py
+13 -1
View File
@@ -275,14 +275,26 @@ def compare_int64(actual: int, expected: None | int, msg: str) -> bool:
return True
def compare_fp(actual: float, expected: None | float, msg: str) -> bool:
def compare_fp(actual: float, expected: None | float | str, msg: str) -> bool:
if expected is None:
return True
from cstest_py.cstest import log
from math import isnan
if isinstance(expected, str):
try:
expected = float(expected)
except ValueError:
log.error(f"{msg}: Expected value '{expected}' is not a valid float.")
return False
def floatToBits(f):
return struct.unpack("=L", struct.pack("=f", f))[0]
# NAN's bit representation is non-canonical
if isnan(actual) and isnan(expected):
return True
if floatToBits(actual) != floatToBits(expected):
log.error(f"{msg}: {actual} != {expected}")
return False
bindings/python/cstest_py/src/cstest_py/cs_modes.py
+4
View File
@@ -42,4 +42,8 @@ configs = {
"type": cs.CS_OPT_SYNTAX,
"val": cs.CS_OPT_SYNTAX_NO_DOLLAR,
},
"CS_OPT_SYNTAX_NO_ALIAS_TEXT": {
"type": cs.CS_OPT_SYNTAX,
"val": cs.CS_OPT_SYNTAX_NO_ALIAS_TEXT
}
}
bindings/python/cstest_py/src/cstest_py/details.py
+9 -1
View File
@@ -8,6 +8,7 @@ from capstone import (
Cs,
CsInsn,
)
import capstone
from capstone.alpha_const import ALPHA_OP_IMM, ALPHA_OP_REG
from capstone.bpf_const import (
BPF_OP_REG,
@@ -71,7 +72,8 @@ from capstone.m68k_const import (
)
from capstone.mips_const import MIPS_OP_REG, MIPS_OP_IMM, MIPS_OP_MEM
from capstone.mos65xx_const import MOS65XX_OP_REG, MOS65XX_OP_MEM, MOS65XX_OP_IMM
from capstone.riscv_const import RISCV_OP_MEM, RISCV_OP_IMM, RISCV_OP_REG
from capstone.riscv import RISCV_OP_FP
from capstone.riscv_const import RISCV_OP_CSR, RISCV_OP_MEM, RISCV_OP_IMM, RISCV_OP_REG
from capstone.sh_const import SH_OP_REG, SH_OP_MEM, SH_OP_IMM
from capstone.sparc_const import SPARC_OP_REG, SPARC_OP_IMM, SPARC_OP_MEM, SPARC_OP_ASI, SPARC_OP_MEMBAR_TAG
from capstone.systemz_const import SYSTEMZ_OP_REG, SYSTEMZ_OP_IMM, SYSTEMZ_OP_MEM
@@ -1345,6 +1347,12 @@ def test_expected_riscv(actual: CsInsn, expected: dict) -> bool:
return False
if not compare_int64(aop.mem.disp, eop.get("mem_disp"), "mem_disp"):
return False
elif aop.type == RISCV_OP_FP:
if not compare_fp(aop.dimm, eop.get("dimm"), "dimm"):
return False
elif aop.type == RISCV_OP_CSR:
if not compare_uint16(aop.csr, capstone.riscv.SYSREG_NAME_TO_VAL[eop.get("csr")], "csr"):
return False
else:
raise ValueError("Operand type not handled.")
return True
cs.c
+12 -2
View File
@@ -201,7 +201,17 @@ typedef struct cs_arch_config {
#define CS_ARCH_CONFIG_RISCV \
{ \
RISCV_global_init, RISCV_option, \
~(CS_MODE_RISCV32 | CS_MODE_RISCV64 | CS_MODE_RISCVC), \
~(CS_MODE_RISCV32 | CS_MODE_RISCV64 | \
CS_MODE_RISCV_C | CS_MODE_RISCV_FD | \
CS_MODE_RISCV_V | CS_MODE_RISCV_ZFINX | \
CS_MODE_RISCV_ZCMP_ZCMT_ZCE | \
CS_MODE_RISCV_ZICFISS | CS_MODE_RISCV_E | \
CS_MODE_RISCV_A | CS_MODE_RISCV_COREV | \
CS_MODE_RISCV_SIFIVE | CS_MODE_RISCV_THEAD | \
CS_MODE_RISCV_ZBA | CS_MODE_RISCV_ZBB | \
CS_MODE_RISCV_ZBC | CS_MODE_RISCV_ZBKB | \
CS_MODE_RISCV_ZBKC | CS_MODE_RISCV_ZBKX | \
CS_MODE_RISCV_ZBS), \
}
#define CS_ARCH_CONFIG_SH \
{ \
@@ -994,7 +1004,7 @@ static uint8_t skipdata_size(cs_struct *handle)
return 8;
case CS_ARCH_RISCV:
// special compress mode
if (handle->mode & CS_MODE_RISCVC)
if (handle->mode & CS_MODE_RISCV_C)
return 2;
return 4;
case CS_ARCH_SH:
cstool/cstool.c
+94 -2
View File
@@ -64,6 +64,11 @@ static struct {
{ CS_ARCH_LOONGARCH, CS_ARCH_MIPS, CS_ARCH_MAX },
CS_OPT_SYNTAX_NO_DOLLAR,
0 },
{ "+noalias",
"Does not print the text alias of an alias instruction",
{ CS_ARCH_RISCV, CS_ARCH_MAX },
CS_OPT_SYNTAX_NO_ALIAS_TEXT,
0 },
// cs_mode only
{ "+nofloat",
"Disables floating point support",
@@ -135,6 +140,92 @@ static struct {
{ CS_ARCH_SPARC, CS_ARCH_MAX },
0,
CS_MODE_V9 },
{ "+c",
"Enables RISCV C extension.",
{ CS_ARCH_RISCV, CS_ARCH_MAX },
0,
CS_MODE_RISCV_C },
{ "+fd",
"Enables RISCV F and D extensions.",
{ CS_ARCH_RISCV, CS_ARCH_MAX },
0,
CS_MODE_RISCV_FD },
{ "+v",
"Enables RISCV V extension.",
{ CS_ARCH_RISCV, CS_ARCH_MAX },
0,
CS_MODE_RISCV_V },
{ "+inx",
"Enables RISCV Zfinx, Zdinx, and Zhinx extensions,"
" zhinxmin is also enabled as it's subset of zhinx ",
{ CS_ARCH_RISCV, CS_ARCH_MAX },
0,
CS_MODE_RISCV_ZFINX },
{ "+zcmp-t-e",
"Enables the following RISCV code size reduction extensions: zcmp, zcmt and zce",
{ CS_ARCH_RISCV, CS_ARCH_MAX },
0,
CS_MODE_RISCV_ZCMP_ZCMT_ZCE },
{ "a",
"Enables the RISCV A extension",
{ CS_ARCH_RISCV, CS_ARCH_MAX },
0,
CS_MODE_RISCV_A },
{ "+zbb",
"Enables the RISCV ZBB extension",
{ CS_ARCH_RISCV, CS_ARCH_MAX },
0,
CS_MODE_RISCV_ZBB },
{ "+zbc",
"Enables the RISCV ZBC extension",
{ CS_ARCH_RISCV, CS_ARCH_MAX },
0,
CS_MODE_RISCV_ZBC },
{ "+zba",
"Enables the RISCV ZBA extension",
{ CS_ARCH_RISCV, CS_ARCH_MAX },
0,
CS_MODE_RISCV_ZBA },
{ "+zbs",
"Enables the RISCV ZBS extension",
{ CS_ARCH_RISCV, CS_ARCH_MAX },
0,
CS_MODE_RISCV_ZBS },
{ "+zbk",
"Enables the RISCV crypto extensions (ZBKB, ZBKC, ZBKX)",
{ CS_ARCH_RISCV, CS_ARCH_MAX },
0,
CS_MODE_RISCV_ZBKB | CS_MODE_RISCV_ZBKC | CS_MODE_RISCV_ZBKX },
{ "+zicfiss",
"Enables the RISCV ZICFISS extension",
{ CS_ARCH_RISCV, CS_ARCH_MAX },
0,
CS_MODE_RISCV_ZICFISS },
{ "+e",
"Enables the RISCV E extension",
{ CS_ARCH_RISCV, CS_ARCH_MAX },
0,
CS_MODE_RISCV_E },
{ "+corev",
"Enables the RISCV COREV extension",
{ CS_ARCH_RISCV, CS_ARCH_MAX },
0,
CS_MODE_RISCV_COREV },
{ "+thead",
"Enables the RISCV T-HEAD extension",
{ CS_ARCH_RISCV, CS_ARCH_MAX },
0,
CS_MODE_RISCV_THEAD },
{ "+sifive",
"Enables the RISCV SiFive extension",
{ CS_ARCH_RISCV, CS_ARCH_MAX },
0,
CS_MODE_RISCV_SIFIVE },
{ "+bitmanip",
"Enables the RISCV bit manipulation extension",
{ CS_ARCH_RISCV, CS_ARCH_MAX },
0,
CS_MODE_RISCV_BITMANIP },
{ NULL }
};
@@ -351,9 +442,9 @@ static struct {
CS_MODE_BIG_ENDIAN | CS_MODE_BPF_EXTENDED },
{ "riscv32", "Risc-V 32-bit, little endian", CS_ARCH_RISCV,
CS_MODE_RISCV32 | CS_MODE_RISCVC },
CS_MODE_RISCV32 | CS_MODE_RISCV_C },
{ "riscv64", "Risc-V 64-bit, little endian", CS_ARCH_RISCV,
CS_MODE_RISCV64 | CS_MODE_RISCVC },
CS_MODE_RISCV64 | CS_MODE_RISCV_C },
{ "6502", "MOS 6502", CS_ARCH_MOS65XX, CS_MODE_MOS65XX_6502 },
{ "65c02", "WDC 65c02", CS_ARCH_MOS65XX, CS_MODE_MOS65XX_65C02 },
@@ -955,6 +1046,7 @@ int main(int argc, char **argv)
}
count = cs_disasm(handle, assembly, size, address, 0, &insn);
if (count > 0) {
for (i = 0; i < count; i++) {
int j;
cstool/cstool_riscv.c
+10
View File
@@ -5,6 +5,8 @@
#include <capstone/capstone.h>
#include "cstool.h"
#include "../arch/RISCV/RISCVInstPrinter.h"
void print_insn_detail_riscv(csh handle, cs_insn *ins)
{
cs_riscv *riscv;
@@ -41,6 +43,14 @@ void print_insn_detail_riscv(csh handle, cs_insn *ins)
i, (long)op->mem.disp);
break;
case RISCV_OP_FP:
printf("\t\toperands[%u].type: FP_IMM %f \n", i,
op->dimm);
break;
case RISCV_OP_CSR:
printf("\t\toperands[%u].type: CSR = %s\n", i,
getSysRegName(op->csr));
break;
}
switch (op->access) {
include/capstone/capstone.h
+22 -1
View File
@@ -209,7 +209,25 @@ typedef enum cs_mode {
CS_MODE_BPF_EXTENDED = 1 << 0, ///< Extended BPF mode
CS_MODE_RISCV32 = 1 << 0, ///< RISCV RV32G
CS_MODE_RISCV64 = 1 << 1, ///< RISCV RV64G
CS_MODE_RISCVC = 1 << 2, ///< RISCV compressed instructure mode
CS_MODE_RISCV_C = 1 << 2, ///< RISCV compressed instructure mode
CS_MODE_RISCV_FD = 1 << 3,
CS_MODE_RISCV_V = 1 << 4,
CS_MODE_RISCV_ZFINX = 1 << 5,
CS_MODE_RISCV_ZCMP_ZCMT_ZCE = 1 << 6,
CS_MODE_RISCV_ZICFISS = 1 << 7,
CS_MODE_RISCV_E = 1 << 8,
CS_MODE_RISCV_A = 1 << 9,
CS_MODE_RISCV_COREV = 1 << 10,
CS_MODE_RISCV_THEAD = 1 << 11,
CS_MODE_RISCV_SIFIVE = 1 << 12,
CS_MODE_RISCV_BITMANIP = 1 << 13,
CS_MODE_RISCV_ZBA = 1 << 14,
CS_MODE_RISCV_ZBB = 1 << 15,
CS_MODE_RISCV_ZBC = 1 << 16,
CS_MODE_RISCV_ZBKB = 1 << 17,
CS_MODE_RISCV_ZBKC = 1 << 18,
CS_MODE_RISCV_ZBKX = 1 << 19,
CS_MODE_RISCV_ZBS = 1 << 20,
CS_MODE_MOS65XX_6502 = 1 << 1, ///< MOS65XXX MOS 6502
CS_MODE_MOS65XX_65C02 = 1 << 2, ///< MOS65XXX WDC 65c02
CS_MODE_MOS65XX_W65C02 = 1 << 3, ///< MOS65XXX WDC W65c02
@@ -341,6 +359,9 @@ typedef enum cs_opt_value {
CS_OPT_SYNTAX_NO_DOLLAR =
1
<< 9, ///< Does not print the $ in front of Mips, LoongArch registers.
CS_OPT_SYNTAX_NO_ALIAS_TEXT =
1
<< 10, ///< Does not print an instruction's alias test if the instruction is an alias
CS_OPT_DETAIL_REAL =
1
<< 1, ///< If enabled, always sets the real instruction detail. Even if the instruction is an alias.
include/capstone/riscv.h
+2116 -180
View File
File diff suppressed because it is too large Load Diff
suite/MC/RISCV/XCValu_valid_riscv32_riscv_xcvalu_syntax_no_alias_text.txt.cs
+73
View File
@@ -0,0 +1,73 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32"|"CS_MODE_RISCV_XCVALU", None
0xab,0x32,0x73,0x86 == cv.addurnr t0, t1, t2
0x2b,0xb5,0xc5,0x86 == cv.addurnr a0, a1, a2
0xab,0x32,0x73,0x5c == cv.maxu t0, t1, t2
0x2b,0xb5,0xc5,0x5c == cv.maxu a0, a1, a2
0xab,0x32,0x73,0x8c == cv.subrnr t0, t1, t2
0x2b,0xb5,0xc5,0x8c == cv.subrnr a0, a1, a2
0xab,0x32,0x73,0x52 == cv.slet t0, t1, t2
0x2b,0xb5,0xc5,0x52 == cv.slet a0, a1, a2
0xdb,0x32,0x73,0x80 == cv.subrn t0, t1, t2, 0
0xdb,0x32,0x73,0xa0 == cv.subrn t0, t1, t2, 16
0x5b,0xb5,0x05,0xbe == cv.subrn a0, a1, zero, 31
0xab,0x32,0x73,0x88 == cv.subnr t0, t1, t2
0x2b,0xb5,0xc5,0x88 == cv.subnr a0, a1, a2
0xab,0x32,0x73,0x82 == cv.addunr t0, t1, t2
0x2b,0xb5,0xc5,0x82 == cv.addunr a0, a1, a2
0xdb,0x22,0x73,0xc0 == cv.addurn t0, t1, t2, 0
0xdb,0x22,0x73,0xe0 == cv.addurn t0, t1, t2, 16
0x5b,0xa5,0x05,0xfe == cv.addurn a0, a1, zero, 31
0xdb,0x22,0x73,0x40 == cv.addun t0, t1, t2, 0
0xdb,0x22,0x73,0x60 == cv.addun t0, t1, t2, 16
0x5b,0xa5,0x05,0x7e == cv.addun a0, a1, zero, 31
0xab,0x32,0x03,0x72 == cv.clipu t0, t1, 0
0xab,0x32,0x03,0x73 == cv.clipu t0, t1, 16
0x2b,0x35,0xf0,0x73 == cv.clipu a0, zero, 31
0xab,0x32,0x03,0x70 == cv.clip t0, t1, 0
0xab,0x32,0x03,0x71 == cv.clip t0, t1, 16
0x2b,0x35,0xf0,0x71 == cv.clip a0, zero, 31
0xab,0x32,0x03,0x62 == cv.exthz t0, t1
0x2b,0xb5,0x05,0x62 == cv.exthz a0, a1
0xab,0x32,0x73,0x5a == cv.max t0, t1, t2
0x2b,0xb5,0xc5,0x5a == cv.max a0, a1, a2
0xab,0x32,0x73,0x74 == cv.clipr t0, t1, t2
0x2b,0xb5,0xc5,0x74 == cv.clipr a0, a1, a2
0xdb,0x32,0x73,0x00 == cv.subn t0, t1, t2, 0
0xdb,0x32,0x73,0x20 == cv.subn t0, t1, t2, 16
0x5b,0xb5,0x05,0x3e == cv.subn a0, a1, zero, 31
0xab,0x32,0x03,0x66 == cv.extbz t0, t1
0x2b,0xb5,0x05,0x66 == cv.extbz a0, a1
0xab,0x32,0x03,0x50 == cv.abs t0, t1
0x2b,0xb5,0x05,0x50 == cv.abs a0, a1
0xab,0x32,0x73,0x76 == cv.clipur t0, t1, t2
0x2b,0xb5,0xc5,0x76 == cv.clipur a0, a1, a2
0xab,0x32,0x73,0x58 == cv.minu t0, t1, t2
0x2b,0xb5,0xc5,0x58 == cv.minu a0, a1, a2
0xdb,0x22,0x73,0x00 == cv.addn t0, t1, t2, 0
0xdb,0x22,0x73,0x20 == cv.addn t0, t1, t2, 16
0x5b,0xa5,0x05,0x3e == cv.addn a0, a1, zero, 31
0xab,0x32,0x73,0x8a == cv.subunr t0, t1, t2
0x2b,0xb5,0xc5,0x8a == cv.subunr a0, a1, a2
0xab,0x32,0x03,0x64 == cv.extbs t0, t1
0x2b,0xb5,0x05,0x64 == cv.extbs a0, a1
0xab,0x32,0x73,0x54 == cv.sletu t0, t1, t2
0x2b,0xb5,0xc5,0x54 == cv.sletu a0, a1, a2
0xab,0x32,0x73,0x56 == cv.min t0, t1, t2
0x2b,0xb5,0xc5,0x56 == cv.min a0, a1, a2
0xab,0x32,0x73,0x8e == cv.suburnr t0, t1, t2
0x2b,0xb5,0xc5,0x8e == cv.suburnr a0, a1, a2
0xab,0x32,0x73,0x84 == cv.addrnr t0, t1, t2
0x2b,0xb5,0xc5,0x84 == cv.addrnr a0, a1, a2
0xab,0x32,0x03,0x60 == cv.exths t0, t1
0x2b,0xb5,0x05,0x60 == cv.exths a0, a1
0xdb,0x22,0x73,0x80 == cv.addrn t0, t1, t2, 0
0xdb,0x22,0x73,0xa0 == cv.addrn t0, t1, t2, 16
0x5b,0xa5,0x05,0xbe == cv.addrn a0, a1, zero, 31
0xdb,0x32,0x73,0xc0 == cv.suburn t0, t1, t2, 0
0xdb,0x32,0x73,0xe0 == cv.suburn t0, t1, t2, 16
0x5b,0xb5,0x05,0xfe == cv.suburn a0, a1, zero, 31
0xab,0x32,0x73,0x80 == cv.addnr t0, t1, t2
0x2b,0xb5,0xc5,0x80 == cv.addnr a0, a1, a2
0xdb,0x32,0x73,0x40 == cv.subun t0, t1, t2, 0
0xdb,0x32,0x73,0x60 == cv.subun t0, t1, t2, 16
0x5b,0xb5,0x05,0x7e == cv.subun a0, a1, zero, 31
suite/MC/RISCV/XCVbi_riscv32_riscv_xcvbi.txt.cs
+5
View File
@@ -0,0 +1,5 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32"|"CS_MODE_RISCV_XCVBI", None
0x0b,0xe0,0x02,0x00 == cv.beqimm t0, 0, 0
0x0b,0x65,0x55,0x02 == cv.beqimm a0, 5, 42
0x0b,0xf0,0x02,0x00 == cv.bneimm t0, 0, 0
0x0b,0x75,0x55,0x02 == cv.bneimm a0, 5, 42
suite/MC/RISCV/XCVbitmanip_riscv32_riscv_xcvbitmanip.txt.cs
+49
View File
@@ -0,0 +1,49 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32"|"CS_MODE_RISCV_XCVBITMANIP", None
0xdb,0x02,0x13,0x00 == cv.extract t0, t1, 0, 1
0x5b,0x85,0x25,0x23 == cv.extract a0, a1, 17, 18
0x5b,0x84,0xf4,0x3d == cv.extract s0, s1, 30, 31
0xdb,0x02,0x13,0x40 == cv.extractu t0, t1, 0, 1
0x5b,0x85,0x25,0x63 == cv.extractu a0, a1, 17, 18
0x5b,0x84,0xf4,0x7d == cv.extractu s0, s1, 30, 31
0xdb,0x02,0x13,0x80 == cv.insert t0, t1, 0, 1
0x5b,0x85,0x25,0xa3 == cv.insert a0, a1, 17, 18
0x5b,0x84,0xf4,0xbd == cv.insert s0, s1, 30, 31
0xdb,0x12,0x13,0x00 == cv.bclr t0, t1, 0, 1
0x5b,0x95,0x25,0x23 == cv.bclr a0, a1, 17, 18
0x5b,0x94,0xf4,0x3d == cv.bclr s0, s1, 30, 31
0xdb,0x12,0x13,0x40 == cv.bset t0, t1, 0, 1
0x5b,0x95,0x25,0x63 == cv.bset a0, a1, 17, 18
0x5b,0x94,0xf4,0x7d == cv.bset s0, s1, 30, 31
0xdb,0x12,0x13,0xc0 == cv.bitrev t0, t1, 0, 1
0x5b,0x95,0x25,0xc3 == cv.bitrev a0, a1, 1, 18
0x5b,0x94,0xf4,0xc5 == cv.bitrev s0, s1, 2, 31
0xab,0x32,0x73,0x30 == cv.extractr t0, t1, t2
0x2b,0xb5,0xc5,0x30 == cv.extractr a0, a1, a2
0x2b,0xb4,0x24,0x31 == cv.extractr s0, s1, s2
0xab,0x32,0x73,0x32 == cv.extractur t0, t1, t2
0x2b,0xb5,0xc5,0x32 == cv.extractur a0, a1, a2
0x2b,0xb4,0x24,0x33 == cv.extractur s0, s1, s2
0xab,0x32,0x73,0x34 == cv.insertr t0, t1, t2
0x2b,0xb5,0xc5,0x34 == cv.insertr a0, a1, a2
0x2b,0xb4,0x24,0x35 == cv.insertr s0, s1, s2
0xab,0x32,0x73,0x38 == cv.bclrr t0, t1, t2
0x2b,0xb5,0xc5,0x38 == cv.bclrr a0, a1, a2
0x2b,0xb4,0x24,0x39 == cv.bclrr s0, s1, s2
0xab,0x32,0x73,0x3a == cv.bsetr t0, t1, t2
0x2b,0xb5,0xc5,0x3a == cv.bsetr a0, a1, a2
0x2b,0xb4,0x24,0x3b == cv.bsetr s0, s1, s2
0xab,0x32,0x73,0x40 == cv.ror t0, t1, t2
0x2b,0xb5,0xc5,0x40 == cv.ror a0, a1, a2
0x2b,0xb4,0x24,0x41 == cv.ror s0, s1, s2
0xab,0x32,0x03,0x42 == cv.ff1 t0, t1
0x2b,0xb5,0x05,0x42 == cv.ff1 a0, a1
0x2b,0xb4,0x04,0x42 == cv.ff1 s0, s1
0xab,0x32,0x03,0x44 == cv.fl1 t0, t1
0x2b,0xb5,0x05,0x44 == cv.fl1 a0, a1
0x2b,0xb4,0x04,0x44 == cv.fl1 s0, s1
0xab,0x32,0x03,0x46 == cv.clb t0, t1
0x2b,0xb5,0x05,0x46 == cv.clb a0, a1
0x2b,0xb4,0x04,0x46 == cv.clb s0, s1
0xab,0x32,0x03,0x48 == cv.cnt t0, t1
0x2b,0xb5,0x05,0x48 == cv.cnt a0, a1
0x2b,0xb4,0x04,0x48 == cv.cnt s0, s1
suite/MC/RISCV/XCVelw_valid_riscv32_riscv_xcvelw.txt.cs
+4
View File
@@ -0,0 +1,4 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32"|"CS_MODE_RISCV_XCVELW", None
0x0b,0x35,0x05,0x40 == cv.elw a0, 1024(a0)
0x8b,0xb5,0x15,0x00 == cv.elw a1, 1(a1)
0x0b,0xb6,0x06,0xc0 == cv.elw a2, -1024(a3)
suite/MC/RISCV/XCVmac_valid_riscv32_riscv_xcvmac_syntax_no_alias_text.txt.cs
+57
View File
@@ -0,0 +1,57 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32"|"CS_MODE_RISCV_XCVMAC", None
0xab,0x32,0x73,0x90 == cv.mac t0, t1, t2
0xab,0x32,0x03,0x90 == cv.mac t0, t1, zero
0xdb,0x62,0x73,0x40 == cv.machhsn t0, t1, t2, 0
0xdb,0x62,0x03,0x60 == cv.machhsn t0, t1, zero, 16
0xdb,0x62,0x03,0x7e == cv.machhsn t0, t1, zero, 31
0xdb,0x62,0x73,0xc0 == cv.machhsrn t0, t1, t2, 0
0xdb,0x62,0x03,0xe0 == cv.machhsrn t0, t1, zero, 16
0xdb,0x62,0x03,0xfe == cv.machhsrn t0, t1, zero, 31
0xdb,0x72,0x73,0x40 == cv.machhun t0, t1, t2, 0
0xdb,0x72,0x03,0x60 == cv.machhun t0, t1, zero, 16
0xdb,0x72,0x03,0x7e == cv.machhun t0, t1, zero, 31
0xdb,0x72,0x73,0xc0 == cv.machhurn t0, t1, t2, 0
0xdb,0x72,0x03,0xe0 == cv.machhurn t0, t1, zero, 16
0xdb,0x72,0x03,0xfe == cv.machhurn t0, t1, zero, 31
0xdb,0x62,0x73,0x00 == cv.macsn t0, t1, t2, 0
0xdb,0x62,0x03,0x20 == cv.macsn t0, t1, zero, 16
0xdb,0x62,0x03,0x3e == cv.macsn t0, t1, zero, 31
0xdb,0x62,0x73,0x80 == cv.macsrn t0, t1, t2, 0
0xdb,0x62,0x03,0xa0 == cv.macsrn t0, t1, zero, 16
0xdb,0x62,0x03,0xbe == cv.macsrn t0, t1, zero, 31
0xdb,0x72,0x73,0x00 == cv.macun t0, t1, t2, 0
0xdb,0x72,0x03,0x20 == cv.macun t0, t1, zero, 16
0xdb,0x72,0x03,0x3e == cv.macun t0, t1, zero, 31
0xdb,0x72,0x73,0x80 == cv.macurn t0, t1, t2, 0
0xdb,0x72,0x03,0xa0 == cv.macurn t0, t1, zero, 16
0xdb,0x72,0x03,0xbe == cv.macurn t0, t1, zero, 31
0xab,0x32,0x73,0x92 == cv.msu t0, t1, t2
0xab,0x32,0x03,0x92 == cv.msu t0, t1, zero
0xdb,0x42,0x73,0x40 == cv.mulhhsn t0, t1, t2, 0
0xdb,0x42,0x03,0x40 == cv.mulhhsn t0, t1, zero, 0
0xdb,0x42,0x03,0x60 == cv.mulhhsn t0, t1, zero, 16
0xdb,0x42,0x03,0x7e == cv.mulhhsn t0, t1, zero, 31
0xdb,0x42,0x73,0xc0 == cv.mulhhsrn t0, t1, t2, 0
0xdb,0x42,0x03,0xe0 == cv.mulhhsrn t0, t1, zero, 16
0xdb,0x42,0x03,0xfe == cv.mulhhsrn t0, t1, zero, 31
0xdb,0x52,0x73,0x40 == cv.mulhhun t0, t1, t2, 0
0xdb,0x52,0x03,0x40 == cv.mulhhun t0, t1, zero, 0
0xdb,0x52,0x03,0x60 == cv.mulhhun t0, t1, zero, 16
0xdb,0x52,0x03,0x7e == cv.mulhhun t0, t1, zero, 31
0xdb,0x52,0x73,0xc0 == cv.mulhhurn t0, t1, t2, 0
0xdb,0x52,0x03,0xe0 == cv.mulhhurn t0, t1, zero, 16
0xdb,0x52,0x03,0xfe == cv.mulhhurn t0, t1, zero, 31
0xdb,0x42,0x73,0x00 == cv.mulsn t0, t1, t2, 0
0xdb,0x42,0x03,0x00 == cv.mulsn t0, t1, zero, 0
0xdb,0x42,0x03,0x20 == cv.mulsn t0, t1, zero, 16
0xdb,0x42,0x03,0x3e == cv.mulsn t0, t1, zero, 31
0xdb,0x42,0x73,0x80 == cv.mulsrn t0, t1, t2, 0
0xdb,0x42,0x03,0xa0 == cv.mulsrn t0, t1, zero, 16
0xdb,0x42,0x03,0xbe == cv.mulsrn t0, t1, zero, 31
0xdb,0x52,0x73,0x00 == cv.mulun t0, t1, t2, 0
0xdb,0x52,0x03,0x00 == cv.mulun t0, t1, zero, 0
0xdb,0x52,0x03,0x20 == cv.mulun t0, t1, zero, 16
0xdb,0x52,0x03,0x3e == cv.mulun t0, t1, zero, 31
0xdb,0x52,0x73,0x80 == cv.mulurn t0, t1, t2, 0
0xdb,0x52,0x03,0xa0 == cv.mulurn t0, t1, zero, 16
0xdb,0x52,0x03,0xbe == cv.mulurn t0, t1, zero, 31
suite/MC/RISCV/XCVmem_valid_riscv32_riscv_xcvmem.txt.cs
+49
View File
@@ -0,0 +1,49 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32"|"CS_MODE_RISCV_XCVMEM", None
0x8b,0x02,0x03,0x00 == cv.lb t0, (t1), 0
0x0b,0x85,0xf5,0x7f == cv.lb a0, (a1), 2047
0xab,0x32,0x73,0x00 == cv.lb t0, (t1), t2
0x2b,0xb5,0xc5,0x00 == cv.lb a0, (a1), a2
0xab,0x32,0x73,0x08 == cv.lb t0, t2(t1)
0x2b,0xb5,0xc5,0x08 == cv.lb a0, a2(a1)
0x8b,0x42,0x03,0x00 == cv.lbu t0, (t1), 0
0x0b,0xc5,0xf5,0x7f == cv.lbu a0, (a1), 2047
0xab,0x32,0x73,0x10 == cv.lbu t0, (t1), t2
0x2b,0xb5,0xc5,0x10 == cv.lbu a0, (a1), a2
0xab,0x32,0x73,0x18 == cv.lbu t0, t2(t1)
0x2b,0xb5,0xc5,0x18 == cv.lbu a0, a2(a1)
0x8b,0x12,0x03,0x00 == cv.lh t0, (t1), 0
0x0b,0x95,0xf5,0x7f == cv.lh a0, (a1), 2047
0xab,0x32,0x73,0x02 == cv.lh t0, (t1), t2
0x2b,0xb5,0xc5,0x02 == cv.lh a0, (a1), a2
0xab,0x32,0x73,0x0a == cv.lh t0, t2(t1)
0x2b,0xb5,0xc5,0x0a == cv.lh a0, a2(a1)
0x8b,0x52,0x03,0x00 == cv.lhu t0, (t1), 0
0x0b,0xd5,0xf5,0x7f == cv.lhu a0, (a1), 2047
0xab,0x32,0x73,0x12 == cv.lhu t0, (t1), t2
0x2b,0xb5,0xc5,0x12 == cv.lhu a0, (a1), a2
0xab,0x32,0x73,0x1a == cv.lhu t0, t2(t1)
0x2b,0xb5,0xc5,0x1a == cv.lhu a0, a2(a1)
0x8b,0x22,0x03,0x00 == cv.lw t0, (t1), 0
0x0b,0xa5,0xf5,0x7f == cv.lw a0, (a1), 2047
0xab,0x32,0x73,0x04 == cv.lw t0, (t1), t2
0x2b,0xb5,0xc5,0x04 == cv.lw a0, (a1), a2
0xab,0x32,0x73,0x0c == cv.lw t0, t2(t1)
0x2b,0xb5,0xc5,0x0c == cv.lw a0, a2(a1)
0x2b,0x00,0x53,0x00 == cv.sb t0, (t1), 0
0xab,0x8f,0xa5,0x7e == cv.sb a0, (a1), 2047
0xab,0x33,0x53,0x20 == cv.sb t0, (t1), t2
0x2b,0xb6,0xa5,0x20 == cv.sb a0, (a1), a2
0xab,0x33,0x53,0x28 == cv.sb t0, t2(t1)
0x2b,0xb6,0xa5,0x28 == cv.sb a0, a2(a1)
0x2b,0x10,0x53,0x00 == cv.sh t0, (t1), 0
0xab,0x9f,0xa5,0x7e == cv.sh a0, (a1), 2047
0xab,0x33,0x53,0x22 == cv.sh t0, (t1), t2
0x2b,0xb6,0xa5,0x22 == cv.sh a0, (a1), a2
0xab,0x33,0x53,0x2a == cv.sh t0, t2(t1)
0x2b,0xb6,0xa5,0x2a == cv.sh a0, a2(a1)
0x2b,0x20,0x53,0x00 == cv.sw t0, (t1), 0
0xab,0xaf,0xa5,0x7e == cv.sw a0, (a1), 2047
0xab,0x33,0x53,0x24 == cv.sw t0, (t1), t2
0x2b,0xb6,0xa5,0x24 == cv.sw a0, (a1), a2
0xab,0x33,0x53,0x2c == cv.sw t0, t2(t1)
0x2b,0xb6,0xa5,0x2c == cv.sw a0, a2(a1)
suite/MC/RISCV/XCVsimd_riscv32_riscv_xcvsimd.txt.cs
+881
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@@ -0,0 +1,881 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32"|"CS_MODE_RISCV_XCVSIMD", None
0xfb,0x02,0x73,0x00 == cv.add.h t0, t1, t2
0x7b,0x8e,0xee,0x01 == cv.add.h t3, t4, t5
0x7b,0x85,0xc5,0x00 == cv.add.h a0, a1, a2
0x7b,0x84,0x24,0x01 == cv.add.h s0, s1, s2
0xfb,0x12,0x73,0x00 == cv.add.b t0, t1, t2
0x7b,0x9e,0xee,0x01 == cv.add.b t3, t4, t5
0x7b,0x95,0xc5,0x00 == cv.add.b a0, a1, a2
0x7b,0x94,0x24,0x01 == cv.add.b s0, s1, s2
0xfb,0x42,0x73,0x00 == cv.add.sc.h t0, t1, t2
0x7b,0xce,0xee,0x01 == cv.add.sc.h t3, t4, t5
0x7b,0xc5,0xc5,0x00 == cv.add.sc.h a0, a1, a2
0x7b,0xc4,0x24,0x01 == cv.add.sc.h s0, s1, s2
0xfb,0x52,0x73,0x00 == cv.add.sc.b t0, t1, t2
0x7b,0xde,0xee,0x01 == cv.add.sc.b t3, t4, t5
0x7b,0xd5,0xc5,0x00 == cv.add.sc.b a0, a1, a2
0x7b,0xd4,0x24,0x01 == cv.add.sc.b s0, s1, s2
0xfb,0x62,0x03,0x00 == cv.add.sci.h t0, t1, 0
0x7b,0xee,0x0e,0x01 == cv.add.sci.h t3, t4, -32
0x7b,0xe5,0x35,0x02 == cv.add.sci.h a0, a1, 7
0x7b,0xe4,0xf4,0x03 == cv.add.sci.h s0, s1, -1
0xfb,0x72,0x03,0x00 == cv.add.sci.b t0, t1, 0
0x7b,0xfe,0x0e,0x01 == cv.add.sci.b t3, t4, -32
0x7b,0xf5,0x35,0x02 == cv.add.sci.b a0, a1, 7
0x7b,0xf4,0xf4,0x03 == cv.add.sci.b s0, s1, -1
0xfb,0x02,0x73,0x08 == cv.sub.h t0, t1, t2
0x7b,0x8e,0xee,0x09 == cv.sub.h t3, t4, t5
0x7b,0x85,0xc5,0x08 == cv.sub.h a0, a1, a2
0x7b,0x84,0x24,0x09 == cv.sub.h s0, s1, s2
0xfb,0x12,0x73,0x08 == cv.sub.b t0, t1, t2
0x7b,0x9e,0xee,0x09 == cv.sub.b t3, t4, t5
0x7b,0x95,0xc5,0x08 == cv.sub.b a0, a1, a2
0x7b,0x94,0x24,0x09 == cv.sub.b s0, s1, s2
0xfb,0x42,0x73,0x08 == cv.sub.sc.h t0, t1, t2
0x7b,0xce,0xee,0x09 == cv.sub.sc.h t3, t4, t5
0x7b,0xc5,0xc5,0x08 == cv.sub.sc.h a0, a1, a2
0x7b,0xc4,0x24,0x09 == cv.sub.sc.h s0, s1, s2
0xfb,0x52,0x73,0x08 == cv.sub.sc.b t0, t1, t2
0x7b,0xde,0xee,0x09 == cv.sub.sc.b t3, t4, t5
0x7b,0xd5,0xc5,0x08 == cv.sub.sc.b a0, a1, a2
0x7b,0xd4,0x24,0x09 == cv.sub.sc.b s0, s1, s2
0xfb,0x62,0x03,0x08 == cv.sub.sci.h t0, t1, 0
0x7b,0xee,0x0e,0x09 == cv.sub.sci.h t3, t4, -32
0x7b,0xe5,0x35,0x0a == cv.sub.sci.h a0, a1, 7
0x7b,0xe4,0xf4,0x0b == cv.sub.sci.h s0, s1, -1
0xfb,0x72,0x03,0x08 == cv.sub.sci.b t0, t1, 0
0x7b,0xfe,0x0e,0x09 == cv.sub.sci.b t3, t4, -32
0x7b,0xf5,0x35,0x0a == cv.sub.sci.b a0, a1, 7
0x7b,0xf4,0xf4,0x0b == cv.sub.sci.b s0, s1, -1
0xfb,0x02,0x73,0x10 == cv.avg.h t0, t1, t2
0x7b,0x8e,0xee,0x11 == cv.avg.h t3, t4, t5
0x7b,0x85,0xc5,0x10 == cv.avg.h a0, a1, a2
0x7b,0x84,0x24,0x11 == cv.avg.h s0, s1, s2
0xfb,0x12,0x73,0x10 == cv.avg.b t0, t1, t2
0x7b,0x9e,0xee,0x11 == cv.avg.b t3, t4, t5
0x7b,0x95,0xc5,0x10 == cv.avg.b a0, a1, a2
0x7b,0x94,0x24,0x11 == cv.avg.b s0, s1, s2
0xfb,0x42,0x73,0x10 == cv.avg.sc.h t0, t1, t2
0x7b,0xce,0xee,0x11 == cv.avg.sc.h t3, t4, t5
0x7b,0xc5,0xc5,0x10 == cv.avg.sc.h a0, a1, a2
0x7b,0xc4,0x24,0x11 == cv.avg.sc.h s0, s1, s2
0xfb,0x52,0x73,0x10 == cv.avg.sc.b t0, t1, t2
0x7b,0xde,0xee,0x11 == cv.avg.sc.b t3, t4, t5
0x7b,0xd5,0xc5,0x10 == cv.avg.sc.b a0, a1, a2
0x7b,0xd4,0x24,0x11 == cv.avg.sc.b s0, s1, s2
0xfb,0x62,0x03,0x10 == cv.avg.sci.h t0, t1, 0
0x7b,0xee,0x0e,0x11 == cv.avg.sci.h t3, t4, -32
0x7b,0xe5,0x35,0x12 == cv.avg.sci.h a0, a1, 7
0x7b,0xe4,0xf4,0x13 == cv.avg.sci.h s0, s1, -1
0xfb,0x72,0x03,0x10 == cv.avg.sci.b t0, t1, 0
0x7b,0xfe,0x0e,0x11 == cv.avg.sci.b t3, t4, -32
0x7b,0xf5,0x35,0x12 == cv.avg.sci.b a0, a1, 7
0x7b,0xf4,0xf4,0x13 == cv.avg.sci.b s0, s1, -1
0xfb,0x02,0x73,0x18 == cv.avgu.h t0, t1, t2
0x7b,0x8e,0xee,0x19 == cv.avgu.h t3, t4, t5
0x7b,0x85,0xc5,0x18 == cv.avgu.h a0, a1, a2
0x7b,0x84,0x24,0x19 == cv.avgu.h s0, s1, s2
0xfb,0x12,0x73,0x18 == cv.avgu.b t0, t1, t2
0x7b,0x9e,0xee,0x19 == cv.avgu.b t3, t4, t5
0x7b,0x95,0xc5,0x18 == cv.avgu.b a0, a1, a2
0x7b,0x94,0x24,0x19 == cv.avgu.b s0, s1, s2
0xfb,0x42,0x73,0x18 == cv.avgu.sc.h t0, t1, t2
0x7b,0xce,0xee,0x19 == cv.avgu.sc.h t3, t4, t5
0x7b,0xc5,0xc5,0x18 == cv.avgu.sc.h a0, a1, a2
0x7b,0xc4,0x24,0x19 == cv.avgu.sc.h s0, s1, s2
0xfb,0x52,0x73,0x18 == cv.avgu.sc.b t0, t1, t2
0x7b,0xde,0xee,0x19 == cv.avgu.sc.b t3, t4, t5
0x7b,0xd5,0xc5,0x18 == cv.avgu.sc.b a0, a1, a2
0x7b,0xd4,0x24,0x19 == cv.avgu.sc.b s0, s1, s2
0xfb,0x62,0x03,0x18 == cv.avgu.sci.h t0, t1, 0
0x7b,0xee,0x0e,0x19 == cv.avgu.sci.h t3, t4, 32
0x7b,0xe5,0x35,0x1a == cv.avgu.sci.h a0, a1, 7
0x7b,0xe4,0xf4,0x1b == cv.avgu.sci.h s0, s1, 63
0xfb,0x72,0x03,0x18 == cv.avgu.sci.b t0, t1, 0
0x7b,0xfe,0x0e,0x19 == cv.avgu.sci.b t3, t4, 32
0x7b,0xf5,0x35,0x1a == cv.avgu.sci.b a0, a1, 7
0x7b,0xf4,0xf4,0x1b == cv.avgu.sci.b s0, s1, 63
0xfb,0x02,0x73,0x20 == cv.min.h t0, t1, t2
0x7b,0x8e,0xee,0x21 == cv.min.h t3, t4, t5
0x7b,0x85,0xc5,0x20 == cv.min.h a0, a1, a2
0x7b,0x84,0x24,0x21 == cv.min.h s0, s1, s2
0xfb,0x12,0x73,0x20 == cv.min.b t0, t1, t2
0x7b,0x9e,0xee,0x21 == cv.min.b t3, t4, t5
0x7b,0x95,0xc5,0x20 == cv.min.b a0, a1, a2
0x7b,0x94,0x24,0x21 == cv.min.b s0, s1, s2
0xfb,0x42,0x73,0x20 == cv.min.sc.h t0, t1, t2
0x7b,0xce,0xee,0x21 == cv.min.sc.h t3, t4, t5
0x7b,0xc5,0xc5,0x20 == cv.min.sc.h a0, a1, a2
0x7b,0xc4,0x24,0x21 == cv.min.sc.h s0, s1, s2
0xfb,0x52,0x73,0x20 == cv.min.sc.b t0, t1, t2
0x7b,0xde,0xee,0x21 == cv.min.sc.b t3, t4, t5
0x7b,0xd5,0xc5,0x20 == cv.min.sc.b a0, a1, a2
0x7b,0xd4,0x24,0x21 == cv.min.sc.b s0, s1, s2
0xfb,0x62,0x03,0x20 == cv.min.sci.h t0, t1, 0
0x7b,0xee,0x0e,0x21 == cv.min.sci.h t3, t4, -32
0x7b,0xe5,0x35,0x22 == cv.min.sci.h a0, a1, 7
0x7b,0xe4,0xf4,0x23 == cv.min.sci.h s0, s1, -1
0xfb,0x72,0x03,0x20 == cv.min.sci.b t0, t1, 0
0x7b,0xfe,0x0e,0x21 == cv.min.sci.b t3, t4, -32
0x7b,0xf5,0x35,0x22 == cv.min.sci.b a0, a1, 7
0x7b,0xf4,0xf4,0x23 == cv.min.sci.b s0, s1, -1
0xfb,0x02,0x73,0x28 == cv.minu.h t0, t1, t2
0x7b,0x8e,0xee,0x29 == cv.minu.h t3, t4, t5
0x7b,0x85,0xc5,0x28 == cv.minu.h a0, a1, a2
0x7b,0x84,0x24,0x29 == cv.minu.h s0, s1, s2
0xfb,0x12,0x73,0x28 == cv.minu.b t0, t1, t2
0x7b,0x9e,0xee,0x29 == cv.minu.b t3, t4, t5
0x7b,0x95,0xc5,0x28 == cv.minu.b a0, a1, a2
0x7b,0x94,0x24,0x29 == cv.minu.b s0, s1, s2
0xfb,0x42,0x73,0x28 == cv.minu.sc.h t0, t1, t2
0x7b,0xce,0xee,0x29 == cv.minu.sc.h t3, t4, t5
0x7b,0xc5,0xc5,0x28 == cv.minu.sc.h a0, a1, a2
0x7b,0xc4,0x24,0x29 == cv.minu.sc.h s0, s1, s2
0xfb,0x52,0x73,0x28 == cv.minu.sc.b t0, t1, t2
0x7b,0xde,0xee,0x29 == cv.minu.sc.b t3, t4, t5
0x7b,0xd5,0xc5,0x28 == cv.minu.sc.b a0, a1, a2
0x7b,0xd4,0x24,0x29 == cv.minu.sc.b s0, s1, s2
0xfb,0x62,0x03,0x28 == cv.minu.sci.h t0, t1, 0
0x7b,0xee,0x0e,0x29 == cv.minu.sci.h t3, t4, 32
0x7b,0xe5,0x35,0x2a == cv.minu.sci.h a0, a1, 7
0x7b,0xe4,0xf4,0x2b == cv.minu.sci.h s0, s1, 63
0xfb,0x72,0x03,0x28 == cv.minu.sci.b t0, t1, 0
0x7b,0xfe,0x0e,0x29 == cv.minu.sci.b t3, t4, 32
0x7b,0xf5,0x35,0x2a == cv.minu.sci.b a0, a1, 7
0x7b,0xf4,0xf4,0x2b == cv.minu.sci.b s0, s1, 63
0xfb,0x02,0x73,0x30 == cv.max.h t0, t1, t2
0x7b,0x8e,0xee,0x31 == cv.max.h t3, t4, t5
0x7b,0x85,0xc5,0x30 == cv.max.h a0, a1, a2
0x7b,0x84,0x24,0x31 == cv.max.h s0, s1, s2
0xfb,0x12,0x73,0x30 == cv.max.b t0, t1, t2
0x7b,0x9e,0xee,0x31 == cv.max.b t3, t4, t5
0x7b,0x95,0xc5,0x30 == cv.max.b a0, a1, a2
0x7b,0x94,0x24,0x31 == cv.max.b s0, s1, s2
0xfb,0x42,0x73,0x30 == cv.max.sc.h t0, t1, t2
0x7b,0xce,0xee,0x31 == cv.max.sc.h t3, t4, t5
0x7b,0xc5,0xc5,0x30 == cv.max.sc.h a0, a1, a2
0x7b,0xc4,0x24,0x31 == cv.max.sc.h s0, s1, s2
0xfb,0x52,0x73,0x30 == cv.max.sc.b t0, t1, t2
0x7b,0xde,0xee,0x31 == cv.max.sc.b t3, t4, t5
0x7b,0xd5,0xc5,0x30 == cv.max.sc.b a0, a1, a2
0x7b,0xd4,0x24,0x31 == cv.max.sc.b s0, s1, s2
0xfb,0x62,0x03,0x30 == cv.max.sci.h t0, t1, 0
0x7b,0xee,0x0e,0x31 == cv.max.sci.h t3, t4, -32
0x7b,0xe5,0x35,0x32 == cv.max.sci.h a0, a1, 7
0x7b,0xe4,0xf4,0x33 == cv.max.sci.h s0, s1, -1
0xfb,0x72,0x03,0x30 == cv.max.sci.b t0, t1, 0
0x7b,0xfe,0x0e,0x31 == cv.max.sci.b t3, t4, -32
0x7b,0xf5,0x35,0x32 == cv.max.sci.b a0, a1, 7
0x7b,0xf4,0xf4,0x33 == cv.max.sci.b s0, s1, -1
0xfb,0x02,0x73,0x38 == cv.maxu.h t0, t1, t2
0x7b,0x8e,0xee,0x39 == cv.maxu.h t3, t4, t5
0x7b,0x85,0xc5,0x38 == cv.maxu.h a0, a1, a2
0x7b,0x84,0x24,0x39 == cv.maxu.h s0, s1, s2
0xfb,0x12,0x73,0x38 == cv.maxu.b t0, t1, t2
0x7b,0x9e,0xee,0x39 == cv.maxu.b t3, t4, t5
0x7b,0x95,0xc5,0x38 == cv.maxu.b a0, a1, a2
0x7b,0x94,0x24,0x39 == cv.maxu.b s0, s1, s2
0xfb,0x42,0x73,0x38 == cv.maxu.sc.h t0, t1, t2
0x7b,0xce,0xee,0x39 == cv.maxu.sc.h t3, t4, t5
0x7b,0xc5,0xc5,0x38 == cv.maxu.sc.h a0, a1, a2
0x7b,0xc4,0x24,0x39 == cv.maxu.sc.h s0, s1, s2
0xfb,0x52,0x73,0x38 == cv.maxu.sc.b t0, t1, t2
0x7b,0xde,0xee,0x39 == cv.maxu.sc.b t3, t4, t5
0x7b,0xd5,0xc5,0x38 == cv.maxu.sc.b a0, a1, a2
0x7b,0xd4,0x24,0x39 == cv.maxu.sc.b s0, s1, s2
0xfb,0x62,0x03,0x38 == cv.maxu.sci.h t0, t1, 0
0x7b,0xee,0x0e,0x39 == cv.maxu.sci.h t3, t4, 32
0x7b,0xe5,0x35,0x3a == cv.maxu.sci.h a0, a1, 7
0x7b,0xe4,0xf4,0x3b == cv.maxu.sci.h s0, s1, 63
0xfb,0x72,0x03,0x38 == cv.maxu.sci.b t0, t1, 0
0x7b,0xfe,0x0e,0x39 == cv.maxu.sci.b t3, t4, 32
0x7b,0xf5,0x35,0x3a == cv.maxu.sci.b a0, a1, 7
0x7b,0xf4,0xf4,0x3b == cv.maxu.sci.b s0, s1, 63
0xfb,0x02,0x73,0x40 == cv.srl.h t0, t1, t2
0x7b,0x8e,0xee,0x41 == cv.srl.h t3, t4, t5
0x7b,0x85,0xc5,0x40 == cv.srl.h a0, a1, a2
0x7b,0x84,0x24,0x41 == cv.srl.h s0, s1, s2
0xfb,0x12,0x73,0x40 == cv.srl.b t0, t1, t2
0x7b,0x9e,0xee,0x41 == cv.srl.b t3, t4, t5
0x7b,0x95,0xc5,0x40 == cv.srl.b a0, a1, a2
0x7b,0x94,0x24,0x41 == cv.srl.b s0, s1, s2
0xfb,0x42,0x73,0x40 == cv.srl.sc.h t0, t1, t2
0x7b,0xce,0xee,0x41 == cv.srl.sc.h t3, t4, t5
0x7b,0xc5,0xc5,0x40 == cv.srl.sc.h a0, a1, a2
0x7b,0xc4,0x24,0x41 == cv.srl.sc.h s0, s1, s2
0xfb,0x52,0x73,0x40 == cv.srl.sc.b t0, t1, t2
0x7b,0xde,0xee,0x41 == cv.srl.sc.b t3, t4, t5
0x7b,0xd5,0xc5,0x40 == cv.srl.sc.b a0, a1, a2
0x7b,0xd4,0x24,0x41 == cv.srl.sc.b s0, s1, s2
0xfb,0x62,0x03,0x40 == cv.srl.sci.h t0, t1, 0
0x7b,0xee,0x0e,0x40 == cv.srl.sci.h t3, t4, 0
0x7b,0xe5,0x35,0x42 == cv.srl.sci.h a0, a1, 7
0x7b,0xe4,0x74,0x42 == cv.srl.sci.h s0, s1, 15
0xfb,0x72,0x03,0x40 == cv.srl.sci.b t0, t1, 0
0x7b,0xfe,0x0e,0x40 == cv.srl.sci.b t3, t4, 0
0x7b,0xf5,0x35,0x42 == cv.srl.sci.b a0, a1, 7
0x7b,0xf4,0x34,0x42 == cv.srl.sci.b s0, s1, 7
0xfb,0x02,0x73,0x48 == cv.sra.h t0, t1, t2
0x7b,0x8e,0xee,0x49 == cv.sra.h t3, t4, t5
0x7b,0x85,0xc5,0x48 == cv.sra.h a0, a1, a2
0x7b,0x84,0x24,0x49 == cv.sra.h s0, s1, s2
0xfb,0x12,0x73,0x48 == cv.sra.b t0, t1, t2
0x7b,0x9e,0xee,0x49 == cv.sra.b t3, t4, t5
0x7b,0x95,0xc5,0x48 == cv.sra.b a0, a1, a2
0x7b,0x94,0x24,0x49 == cv.sra.b s0, s1, s2
0xfb,0x42,0x73,0x48 == cv.sra.sc.h t0, t1, t2
0x7b,0xce,0xee,0x49 == cv.sra.sc.h t3, t4, t5
0x7b,0xc5,0xc5,0x48 == cv.sra.sc.h a0, a1, a2
0x7b,0xc4,0x24,0x49 == cv.sra.sc.h s0, s1, s2
0xfb,0x52,0x73,0x48 == cv.sra.sc.b t0, t1, t2
0x7b,0xde,0xee,0x49 == cv.sra.sc.b t3, t4, t5
0x7b,0xd5,0xc5,0x48 == cv.sra.sc.b a0, a1, a2
0x7b,0xd4,0x24,0x49 == cv.sra.sc.b s0, s1, s2
0xfb,0x62,0x03,0x48 == cv.sra.sci.h t0, t1, 0
0x7b,0xee,0x0e,0x48 == cv.sra.sci.h t3, t4, 0
0x7b,0xe5,0x35,0x4a == cv.sra.sci.h a0, a1, 7
0x7b,0xe4,0x74,0x4a == cv.sra.sci.h s0, s1, 15
0xfb,0x72,0x03,0x48 == cv.sra.sci.b t0, t1, 0
0x7b,0xfe,0x0e,0x48 == cv.sra.sci.b t3, t4, 0
0x7b,0xf5,0x35,0x4a == cv.sra.sci.b a0, a1, 7
0x7b,0xf4,0x34,0x4a == cv.sra.sci.b s0, s1, 7
0xfb,0x02,0x73,0x50 == cv.sll.h t0, t1, t2
0x7b,0x8e,0xee,0x51 == cv.sll.h t3, t4, t5
0x7b,0x85,0xc5,0x50 == cv.sll.h a0, a1, a2
0x7b,0x84,0x24,0x51 == cv.sll.h s0, s1, s2
0xfb,0x12,0x73,0x50 == cv.sll.b t0, t1, t2
0x7b,0x9e,0xee,0x51 == cv.sll.b t3, t4, t5
0x7b,0x95,0xc5,0x50 == cv.sll.b a0, a1, a2
0x7b,0x94,0x24,0x51 == cv.sll.b s0, s1, s2
0xfb,0x42,0x73,0x50 == cv.sll.sc.h t0, t1, t2
0x7b,0xce,0xee,0x51 == cv.sll.sc.h t3, t4, t5
0x7b,0xc5,0xc5,0x50 == cv.sll.sc.h a0, a1, a2
0x7b,0xc4,0x24,0x51 == cv.sll.sc.h s0, s1, s2
0xfb,0x52,0x73,0x50 == cv.sll.sc.b t0, t1, t2
0x7b,0xde,0xee,0x51 == cv.sll.sc.b t3, t4, t5
0x7b,0xd5,0xc5,0x50 == cv.sll.sc.b a0, a1, a2
0x7b,0xd4,0x24,0x51 == cv.sll.sc.b s0, s1, s2
0xfb,0x62,0x03,0x50 == cv.sll.sci.h t0, t1, 0
0x7b,0xee,0x0e,0x50 == cv.sll.sci.h t3, t4, 0
0x7b,0xe5,0x35,0x52 == cv.sll.sci.h a0, a1, 7
0x7b,0xe4,0x74,0x52 == cv.sll.sci.h s0, s1, 15
0xfb,0x72,0x03,0x50 == cv.sll.sci.b t0, t1, 0
0x7b,0xfe,0x0e,0x50 == cv.sll.sci.b t3, t4, 0
0x7b,0xf5,0x35,0x52 == cv.sll.sci.b a0, a1, 7
0x7b,0xf4,0x34,0x52 == cv.sll.sci.b s0, s1, 7
0xfb,0x02,0x73,0x58 == cv.or.h t0, t1, t2
0x7b,0x8e,0xee,0x59 == cv.or.h t3, t4, t5
0x7b,0x85,0xc5,0x58 == cv.or.h a0, a1, a2
0x7b,0x84,0x24,0x59 == cv.or.h s0, s1, s2
0xfb,0x12,0x73,0x58 == cv.or.b t0, t1, t2
0x7b,0x9e,0xee,0x59 == cv.or.b t3, t4, t5
0x7b,0x95,0xc5,0x58 == cv.or.b a0, a1, a2
0x7b,0x94,0x24,0x59 == cv.or.b s0, s1, s2
0xfb,0x42,0x73,0x58 == cv.or.sc.h t0, t1, t2
0x7b,0xce,0xee,0x59 == cv.or.sc.h t3, t4, t5
0x7b,0xc5,0xc5,0x58 == cv.or.sc.h a0, a1, a2
0x7b,0xc4,0x24,0x59 == cv.or.sc.h s0, s1, s2
0xfb,0x52,0x73,0x58 == cv.or.sc.b t0, t1, t2
0x7b,0xde,0xee,0x59 == cv.or.sc.b t3, t4, t5
0x7b,0xd5,0xc5,0x58 == cv.or.sc.b a0, a1, a2
0x7b,0xd4,0x24,0x59 == cv.or.sc.b s0, s1, s2
0xfb,0x62,0x03,0x58 == cv.or.sci.h t0, t1, 0
0x7b,0xee,0x0e,0x59 == cv.or.sci.h t3, t4, -32
0x7b,0xe5,0x35,0x5a == cv.or.sci.h a0, a1, 7
0x7b,0xe4,0xf4,0x5b == cv.or.sci.h s0, s1, -1
0xfb,0x72,0x03,0x58 == cv.or.sci.b t0, t1, 0
0x7b,0xfe,0x0e,0x59 == cv.or.sci.b t3, t4, -32
0x7b,0xf5,0x35,0x5a == cv.or.sci.b a0, a1, 7
0x7b,0xf4,0xf4,0x5b == cv.or.sci.b s0, s1, -1
0xfb,0x02,0x73,0x60 == cv.xor.h t0, t1, t2
0x7b,0x8e,0xee,0x61 == cv.xor.h t3, t4, t5
0x7b,0x85,0xc5,0x60 == cv.xor.h a0, a1, a2
0x7b,0x84,0x24,0x61 == cv.xor.h s0, s1, s2
0xfb,0x12,0x73,0x60 == cv.xor.b t0, t1, t2
0x7b,0x9e,0xee,0x61 == cv.xor.b t3, t4, t5
0x7b,0x95,0xc5,0x60 == cv.xor.b a0, a1, a2
0x7b,0x94,0x24,0x61 == cv.xor.b s0, s1, s2
0xfb,0x42,0x73,0x60 == cv.xor.sc.h t0, t1, t2
0x7b,0xce,0xee,0x61 == cv.xor.sc.h t3, t4, t5
0x7b,0xc5,0xc5,0x60 == cv.xor.sc.h a0, a1, a2
0x7b,0xc4,0x24,0x61 == cv.xor.sc.h s0, s1, s2
0xfb,0x52,0x73,0x60 == cv.xor.sc.b t0, t1, t2
0x7b,0xde,0xee,0x61 == cv.xor.sc.b t3, t4, t5
0x7b,0xd5,0xc5,0x60 == cv.xor.sc.b a0, a1, a2
0x7b,0xd4,0x24,0x61 == cv.xor.sc.b s0, s1, s2
0xfb,0x62,0x03,0x60 == cv.xor.sci.h t0, t1, 0
0x7b,0xee,0x0e,0x61 == cv.xor.sci.h t3, t4, -32
0x7b,0xe5,0x35,0x62 == cv.xor.sci.h a0, a1, 7
0x7b,0xe4,0xf4,0x63 == cv.xor.sci.h s0, s1, -1
0xfb,0x72,0x03,0x60 == cv.xor.sci.b t0, t1, 0
0x7b,0xfe,0x0e,0x61 == cv.xor.sci.b t3, t4, -32
0x7b,0xf5,0x35,0x62 == cv.xor.sci.b a0, a1, 7
0x7b,0xf4,0xf4,0x63 == cv.xor.sci.b s0, s1, -1
0xfb,0x02,0x73,0x68 == cv.and.h t0, t1, t2
0x7b,0x8e,0xee,0x69 == cv.and.h t3, t4, t5
0x7b,0x85,0xc5,0x68 == cv.and.h a0, a1, a2
0x7b,0x84,0x24,0x69 == cv.and.h s0, s1, s2
0xfb,0x12,0x73,0x68 == cv.and.b t0, t1, t2
0x7b,0x9e,0xee,0x69 == cv.and.b t3, t4, t5
0x7b,0x95,0xc5,0x68 == cv.and.b a0, a1, a2
0x7b,0x94,0x24,0x69 == cv.and.b s0, s1, s2
0xfb,0x42,0x73,0x68 == cv.and.sc.h t0, t1, t2
0x7b,0xce,0xee,0x69 == cv.and.sc.h t3, t4, t5
0x7b,0xc5,0xc5,0x68 == cv.and.sc.h a0, a1, a2
0x7b,0xc4,0x24,0x69 == cv.and.sc.h s0, s1, s2
0xfb,0x52,0x73,0x68 == cv.and.sc.b t0, t1, t2
0x7b,0xde,0xee,0x69 == cv.and.sc.b t3, t4, t5
0x7b,0xd5,0xc5,0x68 == cv.and.sc.b a0, a1, a2
0x7b,0xd4,0x24,0x69 == cv.and.sc.b s0, s1, s2
0xfb,0x62,0x03,0x68 == cv.and.sci.h t0, t1, 0
0x7b,0xee,0x0e,0x69 == cv.and.sci.h t3, t4, -32
0x7b,0xe5,0x35,0x6a == cv.and.sci.h a0, a1, 7
0x7b,0xe4,0xf4,0x6b == cv.and.sci.h s0, s1, -1
0xfb,0x72,0x03,0x68 == cv.and.sci.b t0, t1, 0
0x7b,0xfe,0x0e,0x69 == cv.and.sci.b t3, t4, -32
0x7b,0xf5,0x35,0x6a == cv.and.sci.b a0, a1, 7
0x7b,0xf4,0xf4,0x6b == cv.and.sci.b s0, s1, -1
0xfb,0x02,0x03,0x70 == cv.abs.h t0, t1
0x7b,0x8e,0x0e,0x70 == cv.abs.h t3, t4
0x7b,0x85,0x05,0x70 == cv.abs.h a0, a1
0x7b,0x84,0x04,0x70 == cv.abs.h s0, s1
0xfb,0x12,0x03,0x70 == cv.abs.b t0, t1
0x7b,0x9e,0x0e,0x70 == cv.abs.b t3, t4
0x7b,0x95,0x05,0x70 == cv.abs.b a0, a1
0x7b,0x94,0x04,0x70 == cv.abs.b s0, s1
0xfb,0x02,0x73,0x80 == cv.dotup.h t0, t1, t2
0x7b,0x8e,0xee,0x81 == cv.dotup.h t3, t4, t5
0x7b,0x85,0xc5,0x80 == cv.dotup.h a0, a1, a2
0x7b,0x84,0x24,0x81 == cv.dotup.h s0, s1, s2
0xfb,0x12,0x73,0x80 == cv.dotup.b t0, t1, t2
0x7b,0x9e,0xee,0x81 == cv.dotup.b t3, t4, t5
0x7b,0x95,0xc5,0x80 == cv.dotup.b a0, a1, a2
0x7b,0x94,0x24,0x81 == cv.dotup.b s0, s1, s2
0xfb,0x42,0x73,0x80 == cv.dotup.sc.h t0, t1, t2
0x7b,0xce,0xee,0x81 == cv.dotup.sc.h t3, t4, t5
0x7b,0xc5,0xc5,0x80 == cv.dotup.sc.h a0, a1, a2
0x7b,0xc4,0x24,0x81 == cv.dotup.sc.h s0, s1, s2
0xfb,0x52,0x73,0x80 == cv.dotup.sc.b t0, t1, t2
0x7b,0xde,0xee,0x81 == cv.dotup.sc.b t3, t4, t5
0x7b,0xd5,0xc5,0x80 == cv.dotup.sc.b a0, a1, a2
0x7b,0xd4,0x24,0x81 == cv.dotup.sc.b s0, s1, s2
0xfb,0x62,0x03,0x80 == cv.dotup.sci.h t0, t1, 0
0x7b,0xee,0x0e,0x81 == cv.dotup.sci.h t3, t4, 32
0x7b,0xe5,0x35,0x82 == cv.dotup.sci.h a0, a1, 7
0x7b,0xe4,0xf4,0x83 == cv.dotup.sci.h s0, s1, 63
0xfb,0x72,0x03,0x80 == cv.dotup.sci.b t0, t1, 0
0x7b,0xfe,0x0e,0x81 == cv.dotup.sci.b t3, t4, 32
0x7b,0xf5,0x35,0x82 == cv.dotup.sci.b a0, a1, 7
0x7b,0xf4,0xf4,0x83 == cv.dotup.sci.b s0, s1, 63
0xfb,0x02,0x73,0x88 == cv.dotusp.h t0, t1, t2
0x7b,0x8e,0xee,0x89 == cv.dotusp.h t3, t4, t5
0x7b,0x85,0xc5,0x88 == cv.dotusp.h a0, a1, a2
0x7b,0x84,0x24,0x89 == cv.dotusp.h s0, s1, s2
0xfb,0x12,0x73,0x88 == cv.dotusp.b t0, t1, t2
0x7b,0x9e,0xee,0x89 == cv.dotusp.b t3, t4, t5
0x7b,0x95,0xc5,0x88 == cv.dotusp.b a0, a1, a2
0x7b,0x94,0x24,0x89 == cv.dotusp.b s0, s1, s2
0xfb,0x42,0x73,0x88 == cv.dotusp.sc.h t0, t1, t2
0x7b,0xce,0xee,0x89 == cv.dotusp.sc.h t3, t4, t5
0x7b,0xc5,0xc5,0x88 == cv.dotusp.sc.h a0, a1, a2
0x7b,0xc4,0x24,0x89 == cv.dotusp.sc.h s0, s1, s2
0xfb,0x52,0x73,0x88 == cv.dotusp.sc.b t0, t1, t2
0x7b,0xde,0xee,0x89 == cv.dotusp.sc.b t3, t4, t5
0x7b,0xd5,0xc5,0x88 == cv.dotusp.sc.b a0, a1, a2
0x7b,0xd4,0x24,0x89 == cv.dotusp.sc.b s0, s1, s2
0xfb,0x62,0x03,0x88 == cv.dotusp.sci.h t0, t1, 0
0x7b,0xee,0x0e,0x89 == cv.dotusp.sci.h t3, t4, -32
0x7b,0xe5,0x35,0x8a == cv.dotusp.sci.h a0, a1, 7
0x7b,0xe4,0xf4,0x8b == cv.dotusp.sci.h s0, s1, -1
0xfb,0x72,0x03,0x88 == cv.dotusp.sci.b t0, t1, 0
0x7b,0xfe,0x0e,0x89 == cv.dotusp.sci.b t3, t4, -32
0x7b,0xf5,0x35,0x8a == cv.dotusp.sci.b a0, a1, 7
0x7b,0xf4,0xf4,0x8b == cv.dotusp.sci.b s0, s1, -1
0xfb,0x02,0x73,0x90 == cv.dotsp.h t0, t1, t2
0x7b,0x8e,0xee,0x91 == cv.dotsp.h t3, t4, t5
0x7b,0x85,0xc5,0x90 == cv.dotsp.h a0, a1, a2
0x7b,0x84,0x24,0x91 == cv.dotsp.h s0, s1, s2
0xfb,0x12,0x73,0x90 == cv.dotsp.b t0, t1, t2
0x7b,0x9e,0xee,0x91 == cv.dotsp.b t3, t4, t5
0x7b,0x95,0xc5,0x90 == cv.dotsp.b a0, a1, a2
0x7b,0x94,0x24,0x91 == cv.dotsp.b s0, s1, s2
0xfb,0x42,0x73,0x90 == cv.dotsp.sc.h t0, t1, t2
0x7b,0xce,0xee,0x91 == cv.dotsp.sc.h t3, t4, t5
0x7b,0xc5,0xc5,0x90 == cv.dotsp.sc.h a0, a1, a2
0x7b,0xc4,0x24,0x91 == cv.dotsp.sc.h s0, s1, s2
0xfb,0x52,0x73,0x90 == cv.dotsp.sc.b t0, t1, t2
0x7b,0xde,0xee,0x91 == cv.dotsp.sc.b t3, t4, t5
0x7b,0xd5,0xc5,0x90 == cv.dotsp.sc.b a0, a1, a2
0x7b,0xd4,0x24,0x91 == cv.dotsp.sc.b s0, s1, s2
0xfb,0x62,0x03,0x90 == cv.dotsp.sci.h t0, t1, 0
0x7b,0xee,0x0e,0x91 == cv.dotsp.sci.h t3, t4, -32
0x7b,0xe5,0x35,0x92 == cv.dotsp.sci.h a0, a1, 7
0x7b,0xe4,0xf4,0x93 == cv.dotsp.sci.h s0, s1, -1
0xfb,0x72,0x03,0x90 == cv.dotsp.sci.b t0, t1, 0
0x7b,0xfe,0x0e,0x91 == cv.dotsp.sci.b t3, t4, -32
0x7b,0xf5,0x35,0x92 == cv.dotsp.sci.b a0, a1, 7
0x7b,0xf4,0xf4,0x93 == cv.dotsp.sci.b s0, s1, -1
0xfb,0x02,0x73,0x98 == cv.sdotup.h t0, t1, t2
0x7b,0x8e,0xee,0x99 == cv.sdotup.h t3, t4, t5
0x7b,0x85,0xc5,0x98 == cv.sdotup.h a0, a1, a2
0x7b,0x84,0x24,0x99 == cv.sdotup.h s0, s1, s2
0xfb,0x12,0x73,0x98 == cv.sdotup.b t0, t1, t2
0x7b,0x9e,0xee,0x99 == cv.sdotup.b t3, t4, t5
0x7b,0x95,0xc5,0x98 == cv.sdotup.b a0, a1, a2
0x7b,0x94,0x24,0x99 == cv.sdotup.b s0, s1, s2
0xfb,0x42,0x73,0x98 == cv.sdotup.sc.h t0, t1, t2
0x7b,0xce,0xee,0x99 == cv.sdotup.sc.h t3, t4, t5
0x7b,0xc5,0xc5,0x98 == cv.sdotup.sc.h a0, a1, a2
0x7b,0xc4,0x24,0x99 == cv.sdotup.sc.h s0, s1, s2
0xfb,0x52,0x73,0x98 == cv.sdotup.sc.b t0, t1, t2
0x7b,0xde,0xee,0x99 == cv.sdotup.sc.b t3, t4, t5
0x7b,0xd5,0xc5,0x98 == cv.sdotup.sc.b a0, a1, a2
0x7b,0xd4,0x24,0x99 == cv.sdotup.sc.b s0, s1, s2
0xfb,0x62,0x03,0x98 == cv.sdotup.sci.h t0, t1, 0
0x7b,0xee,0x0e,0x99 == cv.sdotup.sci.h t3, t4, 32
0x7b,0xe5,0x35,0x9a == cv.sdotup.sci.h a0, a1, 7
0x7b,0xe4,0xf4,0x9b == cv.sdotup.sci.h s0, s1, 63
0xfb,0x72,0x03,0x98 == cv.sdotup.sci.b t0, t1, 0
0x7b,0xfe,0x0e,0x99 == cv.sdotup.sci.b t3, t4, 32
0x7b,0xf5,0x35,0x9a == cv.sdotup.sci.b a0, a1, 7
0x7b,0xf4,0xf4,0x9b == cv.sdotup.sci.b s0, s1, 63
0xfb,0x02,0x73,0xa0 == cv.sdotusp.h t0, t1, t2
0x7b,0x8e,0xee,0xa1 == cv.sdotusp.h t3, t4, t5
0x7b,0x85,0xc5,0xa0 == cv.sdotusp.h a0, a1, a2
0x7b,0x84,0x24,0xa1 == cv.sdotusp.h s0, s1, s2
0xfb,0x12,0x73,0xa0 == cv.sdotusp.b t0, t1, t2
0x7b,0x9e,0xee,0xa1 == cv.sdotusp.b t3, t4, t5
0x7b,0x95,0xc5,0xa0 == cv.sdotusp.b a0, a1, a2
0x7b,0x94,0x24,0xa1 == cv.sdotusp.b s0, s1, s2
0xfb,0x42,0x73,0xa0 == cv.sdotusp.sc.h t0, t1, t2
0x7b,0xce,0xee,0xa1 == cv.sdotusp.sc.h t3, t4, t5
0x7b,0xc5,0xc5,0xa0 == cv.sdotusp.sc.h a0, a1, a2
0x7b,0xc4,0x24,0xa1 == cv.sdotusp.sc.h s0, s1, s2
0xfb,0x52,0x73,0xa0 == cv.sdotusp.sc.b t0, t1, t2
0x7b,0xde,0xee,0xa1 == cv.sdotusp.sc.b t3, t4, t5
0x7b,0xd5,0xc5,0xa0 == cv.sdotusp.sc.b a0, a1, a2
0x7b,0xd4,0x24,0xa1 == cv.sdotusp.sc.b s0, s1, s2
0xfb,0x62,0x03,0xa0 == cv.sdotusp.sci.h t0, t1, 0
0x7b,0xee,0x0e,0xa1 == cv.sdotusp.sci.h t3, t4, -32
0x7b,0xe5,0x35,0xa2 == cv.sdotusp.sci.h a0, a1, 7
0x7b,0xe4,0xf4,0xa3 == cv.sdotusp.sci.h s0, s1, -1
0xfb,0x72,0x03,0xa0 == cv.sdotusp.sci.b t0, t1, 0
0x7b,0xfe,0x0e,0xa1 == cv.sdotusp.sci.b t3, t4, -32
0x7b,0xf5,0x35,0xa2 == cv.sdotusp.sci.b a0, a1, 7
0x7b,0xf4,0xf4,0xa3 == cv.sdotusp.sci.b s0, s1, -1
0xfb,0x02,0x73,0xa8 == cv.sdotsp.h t0, t1, t2
0x7b,0x8e,0xee,0xa9 == cv.sdotsp.h t3, t4, t5
0x7b,0x85,0xc5,0xa8 == cv.sdotsp.h a0, a1, a2
0x7b,0x84,0x24,0xa9 == cv.sdotsp.h s0, s1, s2
0xfb,0x12,0x73,0xa8 == cv.sdotsp.b t0, t1, t2
0x7b,0x9e,0xee,0xa9 == cv.sdotsp.b t3, t4, t5
0x7b,0x95,0xc5,0xa8 == cv.sdotsp.b a0, a1, a2
0x7b,0x94,0x24,0xa9 == cv.sdotsp.b s0, s1, s2
0xfb,0x42,0x73,0xa8 == cv.sdotsp.sc.h t0, t1, t2
0x7b,0xce,0xee,0xa9 == cv.sdotsp.sc.h t3, t4, t5
0x7b,0xc5,0xc5,0xa8 == cv.sdotsp.sc.h a0, a1, a2
0x7b,0xc4,0x24,0xa9 == cv.sdotsp.sc.h s0, s1, s2
0xfb,0x52,0x73,0xa8 == cv.sdotsp.sc.b t0, t1, t2
0x7b,0xde,0xee,0xa9 == cv.sdotsp.sc.b t3, t4, t5
0x7b,0xd5,0xc5,0xa8 == cv.sdotsp.sc.b a0, a1, a2
0x7b,0xd4,0x24,0xa9 == cv.sdotsp.sc.b s0, s1, s2
0xfb,0x62,0x03,0xa8 == cv.sdotsp.sci.h t0, t1, 0
0x7b,0xee,0x0e,0xa9 == cv.sdotsp.sci.h t3, t4, -32
0x7b,0xe5,0x35,0xaa == cv.sdotsp.sci.h a0, a1, 7
0x7b,0xe4,0xf4,0xab == cv.sdotsp.sci.h s0, s1, -1
0xfb,0x72,0x03,0xa8 == cv.sdotsp.sci.b t0, t1, 0
0x7b,0xfe,0x0e,0xa9 == cv.sdotsp.sci.b t3, t4, -32
0x7b,0xf5,0x35,0xaa == cv.sdotsp.sci.b a0, a1, 7
0x7b,0xf4,0xf4,0xab == cv.sdotsp.sci.b s0, s1, -1
0xfb,0x02,0x03,0xb8 == cv.extract.h t0, t1, 0
0x7b,0x8e,0x0e,0xb9 == cv.extract.h t3, t4, 32
0x7b,0x85,0x35,0xba == cv.extract.h a0, a1, 7
0x7b,0x84,0xf4,0xbb == cv.extract.h s0, s1, 63
0xfb,0x12,0x03,0xb8 == cv.extract.b t0, t1, 0
0x7b,0x9e,0x0e,0xb9 == cv.extract.b t3, t4, 32
0x7b,0x95,0x35,0xba == cv.extract.b a0, a1, 7
0x7b,0x94,0xf4,0xbb == cv.extract.b s0, s1, 63
0xfb,0x22,0x03,0xb8 == cv.extractu.h t0, t1, 0
0x7b,0xae,0x0e,0xb9 == cv.extractu.h t3, t4, 32
0x7b,0xa5,0x35,0xba == cv.extractu.h a0, a1, 7
0x7b,0xa4,0xf4,0xbb == cv.extractu.h s0, s1, 63
0xfb,0x32,0x03,0xb8 == cv.extractu.b t0, t1, 0
0x7b,0xbe,0x0e,0xb9 == cv.extractu.b t3, t4, 32
0x7b,0xb5,0x35,0xba == cv.extractu.b a0, a1, 7
0x7b,0xb4,0xf4,0xbb == cv.extractu.b s0, s1, 63
0xfb,0x42,0x03,0xb8 == cv.insert.h t0, t1, 0
0x7b,0xce,0x0e,0xb9 == cv.insert.h t3, t4, 32
0x7b,0xc5,0x35,0xba == cv.insert.h a0, a1, 7
0x7b,0xc4,0xf4,0xbb == cv.insert.h s0, s1, 63
0xfb,0x52,0x03,0xb8 == cv.insert.b t0, t1, 0
0x7b,0xde,0x0e,0xb9 == cv.insert.b t3, t4, 32
0x7b,0xd5,0x35,0xba == cv.insert.b a0, a1, 7
0x7b,0xd4,0xf4,0xbb == cv.insert.b s0, s1, 63
0xfb,0x02,0x73,0xc0 == cv.shuffle.h t0, t1, t2
0x7b,0x8e,0xee,0xc1 == cv.shuffle.h t3, t4, t5
0x7b,0x85,0xc5,0xc0 == cv.shuffle.h a0, a1, a2
0x7b,0x84,0x24,0xc1 == cv.shuffle.h s0, s1, s2
0xfb,0x12,0x73,0xc0 == cv.shuffle.b t0, t1, t2
0x7b,0x9e,0xee,0xc1 == cv.shuffle.b t3, t4, t5
0x7b,0x95,0xc5,0xc0 == cv.shuffle.b a0, a1, a2
0x7b,0x94,0x24,0xc1 == cv.shuffle.b s0, s1, s2
0xfb,0x62,0x03,0xc0 == cv.shuffle.sci.h t0, t1, 0
0x7b,0xee,0x0e,0xc1 == cv.shuffle.sci.h t3, t4, 32
0x7b,0xe5,0x35,0xc2 == cv.shuffle.sci.h a0, a1, 7
0x7b,0xe4,0xf4,0xc3 == cv.shuffle.sci.h s0, s1, 63
0xfb,0x72,0x03,0xc0 == cv.shufflei0.sci.b t0, t1, 0
0x7b,0xfe,0x0e,0xc1 == cv.shufflei0.sci.b t3, t4, 32
0x7b,0xf5,0x35,0xc2 == cv.shufflei0.sci.b a0, a1, 7
0x7b,0xf4,0xf4,0xc3 == cv.shufflei0.sci.b s0, s1, 63
0xfb,0x72,0x03,0xc8 == cv.shufflei1.sci.b t0, t1, 0
0x7b,0xfe,0x0e,0xc9 == cv.shufflei1.sci.b t3, t4, 32
0x7b,0xf5,0x35,0xca == cv.shufflei1.sci.b a0, a1, 7
0x7b,0xf4,0xf4,0xcb == cv.shufflei1.sci.b s0, s1, 63
0xfb,0x72,0x03,0xd0 == cv.shufflei2.sci.b t0, t1, 0
0x7b,0xfe,0x0e,0xd1 == cv.shufflei2.sci.b t3, t4, 32
0x7b,0xf5,0x35,0xd2 == cv.shufflei2.sci.b a0, a1, 7
0x7b,0xf4,0xf4,0xd3 == cv.shufflei2.sci.b s0, s1, 63
0xfb,0x72,0x03,0xd8 == cv.shufflei3.sci.b t0, t1, 0
0x7b,0xfe,0x0e,0xd9 == cv.shufflei3.sci.b t3, t4, 32
0x7b,0xf5,0x35,0xda == cv.shufflei3.sci.b a0, a1, 7
0x7b,0xf4,0xf4,0xdb == cv.shufflei3.sci.b s0, s1, 63
0xfb,0x02,0x73,0xe0 == cv.shuffle2.h t0, t1, t2
0x7b,0x8e,0xee,0xe1 == cv.shuffle2.h t3, t4, t5
0x7b,0x85,0xc5,0xe0 == cv.shuffle2.h a0, a1, a2
0x7b,0x84,0x24,0xe1 == cv.shuffle2.h s0, s1, s2
0xfb,0x12,0x73,0xe0 == cv.shuffle2.b t0, t1, t2
0x7b,0x9e,0xee,0xe1 == cv.shuffle2.b t3, t4, t5
0x7b,0x95,0xc5,0xe0 == cv.shuffle2.b a0, a1, a2
0x7b,0x94,0x24,0xe1 == cv.shuffle2.b s0, s1, s2
0xfb,0x02,0x73,0xf0 == cv.pack t0, t1, t2
0x7b,0x8e,0xee,0xf1 == cv.pack t3, t4, t5
0x7b,0x85,0xc5,0xf0 == cv.pack a0, a1, a2
0x7b,0x84,0x24,0xf1 == cv.pack s0, s1, s2
0xfb,0x02,0x73,0xf2 == cv.pack.h t0, t1, t2
0x7b,0x8e,0xee,0xf3 == cv.pack.h t3, t4, t5
0x7b,0x85,0xc5,0xf2 == cv.pack.h a0, a1, a2
0x7b,0x84,0x24,0xf3 == cv.pack.h s0, s1, s2
0xfb,0x12,0x73,0xfa == cv.packhi.b t0, t1, t2
0x7b,0x9e,0xee,0xfb == cv.packhi.b t3, t4, t5
0x7b,0x95,0xc5,0xfa == cv.packhi.b a0, a1, a2
0x7b,0x94,0x24,0xfb == cv.packhi.b s0, s1, s2
0xfb,0x12,0x73,0xf8 == cv.packlo.b t0, t1, t2
0x7b,0x9e,0xee,0xf9 == cv.packlo.b t3, t4, t5
0x7b,0x95,0xc5,0xf8 == cv.packlo.b a0, a1, a2
0x7b,0x94,0x24,0xf9 == cv.packlo.b s0, s1, s2
0xfb,0x02,0x73,0x04 == cv.cmpeq.h t0, t1, t2
0x7b,0x8e,0xee,0x05 == cv.cmpeq.h t3, t4, t5
0x7b,0x85,0xc5,0x04 == cv.cmpeq.h a0, a1, a2
0x7b,0x84,0x24,0x05 == cv.cmpeq.h s0, s1, s2
0xfb,0x12,0x73,0x04 == cv.cmpeq.b t0, t1, t2
0x7b,0x9e,0xee,0x05 == cv.cmpeq.b t3, t4, t5
0x7b,0x95,0xc5,0x04 == cv.cmpeq.b a0, a1, a2
0x7b,0x94,0x24,0x05 == cv.cmpeq.b s0, s1, s2
0xfb,0x42,0x73,0x04 == cv.cmpeq.sc.h t0, t1, t2
0x7b,0xce,0xee,0x05 == cv.cmpeq.sc.h t3, t4, t5
0x7b,0xc5,0xc5,0x04 == cv.cmpeq.sc.h a0, a1, a2
0x7b,0xc4,0x24,0x05 == cv.cmpeq.sc.h s0, s1, s2
0xfb,0x52,0x73,0x04 == cv.cmpeq.sc.b t0, t1, t2
0x7b,0xde,0xee,0x05 == cv.cmpeq.sc.b t3, t4, t5
0x7b,0xd5,0xc5,0x04 == cv.cmpeq.sc.b a0, a1, a2
0x7b,0xd4,0x24,0x05 == cv.cmpeq.sc.b s0, s1, s2
0xfb,0x62,0x03,0x04 == cv.cmpeq.sci.h t0, t1, 0
0x7b,0xee,0x0e,0x05 == cv.cmpeq.sci.h t3, t4, -32
0x7b,0xe5,0x35,0x06 == cv.cmpeq.sci.h a0, a1, 7
0x7b,0xe4,0xf4,0x07 == cv.cmpeq.sci.h s0, s1, -1
0xfb,0x72,0x03,0x04 == cv.cmpeq.sci.b t0, t1, 0
0x7b,0xfe,0x0e,0x05 == cv.cmpeq.sci.b t3, t4, -32
0x7b,0xf5,0x35,0x06 == cv.cmpeq.sci.b a0, a1, 7
0x7b,0xf4,0xf4,0x07 == cv.cmpeq.sci.b s0, s1, -1
0xfb,0x02,0x73,0x0c == cv.cmpne.h t0, t1, t2
0x7b,0x8e,0xee,0x0d == cv.cmpne.h t3, t4, t5
0x7b,0x85,0xc5,0x0c == cv.cmpne.h a0, a1, a2
0x7b,0x84,0x24,0x0d == cv.cmpne.h s0, s1, s2
0xfb,0x12,0x73,0x0c == cv.cmpne.b t0, t1, t2
0x7b,0x9e,0xee,0x0d == cv.cmpne.b t3, t4, t5
0x7b,0x95,0xc5,0x0c == cv.cmpne.b a0, a1, a2
0x7b,0x94,0x24,0x0d == cv.cmpne.b s0, s1, s2
0xfb,0x42,0x73,0x0c == cv.cmpne.sc.h t0, t1, t2
0x7b,0xce,0xee,0x0d == cv.cmpne.sc.h t3, t4, t5
0x7b,0xc5,0xc5,0x0c == cv.cmpne.sc.h a0, a1, a2
0x7b,0xc4,0x24,0x0d == cv.cmpne.sc.h s0, s1, s2
0xfb,0x52,0x73,0x0c == cv.cmpne.sc.b t0, t1, t2
0x7b,0xde,0xee,0x0d == cv.cmpne.sc.b t3, t4, t5
0x7b,0xd5,0xc5,0x0c == cv.cmpne.sc.b a0, a1, a2
0x7b,0xd4,0x24,0x0d == cv.cmpne.sc.b s0, s1, s2
0xfb,0x62,0x03,0x0c == cv.cmpne.sci.h t0, t1, 0
0x7b,0xee,0x0e,0x0d == cv.cmpne.sci.h t3, t4, -32
0x7b,0xe5,0x35,0x0e == cv.cmpne.sci.h a0, a1, 7
0x7b,0xe4,0xf4,0x0f == cv.cmpne.sci.h s0, s1, -1
0xfb,0x72,0x03,0x0c == cv.cmpne.sci.b t0, t1, 0
0x7b,0xfe,0x0e,0x0d == cv.cmpne.sci.b t3, t4, -32
0x7b,0xf5,0x35,0x0e == cv.cmpne.sci.b a0, a1, 7
0x7b,0xf4,0xf4,0x0f == cv.cmpne.sci.b s0, s1, -1
0xfb,0x02,0x73,0x14 == cv.cmpgt.h t0, t1, t2
0x7b,0x8e,0xee,0x15 == cv.cmpgt.h t3, t4, t5
0x7b,0x85,0xc5,0x14 == cv.cmpgt.h a0, a1, a2
0x7b,0x84,0x24,0x15 == cv.cmpgt.h s0, s1, s2
0xfb,0x12,0x73,0x14 == cv.cmpgt.b t0, t1, t2
0x7b,0x9e,0xee,0x15 == cv.cmpgt.b t3, t4, t5
0x7b,0x95,0xc5,0x14 == cv.cmpgt.b a0, a1, a2
0x7b,0x94,0x24,0x15 == cv.cmpgt.b s0, s1, s2
0xfb,0x42,0x73,0x14 == cv.cmpgt.sc.h t0, t1, t2
0x7b,0xce,0xee,0x15 == cv.cmpgt.sc.h t3, t4, t5
0x7b,0xc5,0xc5,0x14 == cv.cmpgt.sc.h a0, a1, a2
0x7b,0xc4,0x24,0x15 == cv.cmpgt.sc.h s0, s1, s2
0xfb,0x52,0x73,0x14 == cv.cmpgt.sc.b t0, t1, t2
0x7b,0xde,0xee,0x15 == cv.cmpgt.sc.b t3, t4, t5
0x7b,0xd5,0xc5,0x14 == cv.cmpgt.sc.b a0, a1, a2
0x7b,0xd4,0x24,0x15 == cv.cmpgt.sc.b s0, s1, s2
0xfb,0x62,0x03,0x14 == cv.cmpgt.sci.h t0, t1, 0
0x7b,0xee,0x0e,0x15 == cv.cmpgt.sci.h t3, t4, -32
0x7b,0xe5,0x35,0x16 == cv.cmpgt.sci.h a0, a1, 7
0x7b,0xe4,0xf4,0x17 == cv.cmpgt.sci.h s0, s1, -1
0xfb,0x72,0x03,0x14 == cv.cmpgt.sci.b t0, t1, 0
0x7b,0xfe,0x0e,0x15 == cv.cmpgt.sci.b t3, t4, -32
0x7b,0xf5,0x35,0x16 == cv.cmpgt.sci.b a0, a1, 7
0x7b,0xf4,0xf4,0x17 == cv.cmpgt.sci.b s0, s1, -1
0xfb,0x02,0x73,0x1c == cv.cmpge.h t0, t1, t2
0x7b,0x8e,0xee,0x1d == cv.cmpge.h t3, t4, t5
0x7b,0x85,0xc5,0x1c == cv.cmpge.h a0, a1, a2
0x7b,0x84,0x24,0x1d == cv.cmpge.h s0, s1, s2
0xfb,0x12,0x73,0x1c == cv.cmpge.b t0, t1, t2
0x7b,0x9e,0xee,0x1d == cv.cmpge.b t3, t4, t5
0x7b,0x95,0xc5,0x1c == cv.cmpge.b a0, a1, a2
0x7b,0x94,0x24,0x1d == cv.cmpge.b s0, s1, s2
0xfb,0x42,0x73,0x1c == cv.cmpge.sc.h t0, t1, t2
0x7b,0xce,0xee,0x1d == cv.cmpge.sc.h t3, t4, t5
0x7b,0xc5,0xc5,0x1c == cv.cmpge.sc.h a0, a1, a2
0x7b,0xc4,0x24,0x1d == cv.cmpge.sc.h s0, s1, s2
0xfb,0x52,0x73,0x1c == cv.cmpge.sc.b t0, t1, t2
0x7b,0xde,0xee,0x1d == cv.cmpge.sc.b t3, t4, t5
0x7b,0xd5,0xc5,0x1c == cv.cmpge.sc.b a0, a1, a2
0x7b,0xd4,0x24,0x1d == cv.cmpge.sc.b s0, s1, s2
0xfb,0x62,0x03,0x1c == cv.cmpge.sci.h t0, t1, 0
0x7b,0xee,0x0e,0x1d == cv.cmpge.sci.h t3, t4, -32
0x7b,0xe5,0x35,0x1e == cv.cmpge.sci.h a0, a1, 7
0x7b,0xe4,0xf4,0x1f == cv.cmpge.sci.h s0, s1, -1
0xfb,0x72,0x03,0x1c == cv.cmpge.sci.b t0, t1, 0
0x7b,0xfe,0x0e,0x1d == cv.cmpge.sci.b t3, t4, -32
0x7b,0xf5,0x35,0x1e == cv.cmpge.sci.b a0, a1, 7
0x7b,0xf4,0xf4,0x1f == cv.cmpge.sci.b s0, s1, -1
0xfb,0x02,0x73,0x24 == cv.cmplt.h t0, t1, t2
0x7b,0x8e,0xee,0x25 == cv.cmplt.h t3, t4, t5
0x7b,0x85,0xc5,0x24 == cv.cmplt.h a0, a1, a2
0x7b,0x84,0x24,0x25 == cv.cmplt.h s0, s1, s2
0xfb,0x12,0x73,0x24 == cv.cmplt.b t0, t1, t2
0x7b,0x9e,0xee,0x25 == cv.cmplt.b t3, t4, t5
0x7b,0x95,0xc5,0x24 == cv.cmplt.b a0, a1, a2
0x7b,0x94,0x24,0x25 == cv.cmplt.b s0, s1, s2
0xfb,0x42,0x73,0x24 == cv.cmplt.sc.h t0, t1, t2
0x7b,0xce,0xee,0x25 == cv.cmplt.sc.h t3, t4, t5
0x7b,0xc5,0xc5,0x24 == cv.cmplt.sc.h a0, a1, a2
0x7b,0xc4,0x24,0x25 == cv.cmplt.sc.h s0, s1, s2
0xfb,0x52,0x73,0x24 == cv.cmplt.sc.b t0, t1, t2
0x7b,0xde,0xee,0x25 == cv.cmplt.sc.b t3, t4, t5
0x7b,0xd5,0xc5,0x24 == cv.cmplt.sc.b a0, a1, a2
0x7b,0xd4,0x24,0x25 == cv.cmplt.sc.b s0, s1, s2
0xfb,0x62,0x03,0x24 == cv.cmplt.sci.h t0, t1, 0
0x7b,0xee,0x0e,0x25 == cv.cmplt.sci.h t3, t4, -32
0x7b,0xe5,0x35,0x26 == cv.cmplt.sci.h a0, a1, 7
0x7b,0xe4,0xf4,0x27 == cv.cmplt.sci.h s0, s1, -1
0xfb,0x72,0x03,0x24 == cv.cmplt.sci.b t0, t1, 0
0x7b,0xfe,0x0e,0x25 == cv.cmplt.sci.b t3, t4, -32
0x7b,0xf5,0x35,0x26 == cv.cmplt.sci.b a0, a1, 7
0x7b,0xf4,0xf4,0x27 == cv.cmplt.sci.b s0, s1, -1
0xfb,0x02,0x73,0x2c == cv.cmple.h t0, t1, t2
0x7b,0x8e,0xee,0x2d == cv.cmple.h t3, t4, t5
0x7b,0x85,0xc5,0x2c == cv.cmple.h a0, a1, a2
0x7b,0x84,0x24,0x2d == cv.cmple.h s0, s1, s2
0xfb,0x12,0x73,0x2c == cv.cmple.b t0, t1, t2
0x7b,0x9e,0xee,0x2d == cv.cmple.b t3, t4, t5
0x7b,0x95,0xc5,0x2c == cv.cmple.b a0, a1, a2
0x7b,0x94,0x24,0x2d == cv.cmple.b s0, s1, s2
0xfb,0x42,0x73,0x2c == cv.cmple.sc.h t0, t1, t2
0x7b,0xce,0xee,0x2d == cv.cmple.sc.h t3, t4, t5
0x7b,0xc5,0xc5,0x2c == cv.cmple.sc.h a0, a1, a2
0x7b,0xc4,0x24,0x2d == cv.cmple.sc.h s0, s1, s2
0xfb,0x52,0x73,0x2c == cv.cmple.sc.b t0, t1, t2
0x7b,0xde,0xee,0x2d == cv.cmple.sc.b t3, t4, t5
0x7b,0xd5,0xc5,0x2c == cv.cmple.sc.b a0, a1, a2
0x7b,0xd4,0x24,0x2d == cv.cmple.sc.b s0, s1, s2
0xfb,0x62,0x03,0x2c == cv.cmple.sci.h t0, t1, 0
0x7b,0xee,0x0e,0x2d == cv.cmple.sci.h t3, t4, -32
0x7b,0xe5,0x35,0x2e == cv.cmple.sci.h a0, a1, 7
0x7b,0xe4,0xf4,0x2f == cv.cmple.sci.h s0, s1, -1
0xfb,0x72,0x03,0x2c == cv.cmple.sci.b t0, t1, 0
0x7b,0xfe,0x0e,0x2d == cv.cmple.sci.b t3, t4, -32
0x7b,0xf5,0x35,0x2e == cv.cmple.sci.b a0, a1, 7
0x7b,0xf4,0xf4,0x2f == cv.cmple.sci.b s0, s1, -1
0xfb,0x02,0x73,0x34 == cv.cmpgtu.h t0, t1, t2
0x7b,0x8e,0xee,0x35 == cv.cmpgtu.h t3, t4, t5
0x7b,0x85,0xc5,0x34 == cv.cmpgtu.h a0, a1, a2
0x7b,0x84,0x24,0x35 == cv.cmpgtu.h s0, s1, s2
0xfb,0x12,0x73,0x34 == cv.cmpgtu.b t0, t1, t2
0x7b,0x9e,0xee,0x35 == cv.cmpgtu.b t3, t4, t5
0x7b,0x95,0xc5,0x34 == cv.cmpgtu.b a0, a1, a2
0x7b,0x94,0x24,0x35 == cv.cmpgtu.b s0, s1, s2
0xfb,0x42,0x73,0x34 == cv.cmpgtu.sc.h t0, t1, t2
0x7b,0xce,0xee,0x35 == cv.cmpgtu.sc.h t3, t4, t5
0x7b,0xc5,0xc5,0x34 == cv.cmpgtu.sc.h a0, a1, a2
0x7b,0xc4,0x24,0x35 == cv.cmpgtu.sc.h s0, s1, s2
0xfb,0x52,0x73,0x34 == cv.cmpgtu.sc.b t0, t1, t2
0x7b,0xde,0xee,0x35 == cv.cmpgtu.sc.b t3, t4, t5
0x7b,0xd5,0xc5,0x34 == cv.cmpgtu.sc.b a0, a1, a2
0x7b,0xd4,0x24,0x35 == cv.cmpgtu.sc.b s0, s1, s2
0xfb,0x62,0x03,0x34 == cv.cmpgtu.sci.h t0, t1, 0
0x7b,0xee,0x0e,0x35 == cv.cmpgtu.sci.h t3, t4, 32
0x7b,0xe5,0x35,0x36 == cv.cmpgtu.sci.h a0, a1, 7
0x7b,0xe4,0xf4,0x37 == cv.cmpgtu.sci.h s0, s1, 63
0xfb,0x72,0x03,0x34 == cv.cmpgtu.sci.b t0, t1, 0
0x7b,0xfe,0x0e,0x35 == cv.cmpgtu.sci.b t3, t4, 32
0x7b,0xf5,0x35,0x36 == cv.cmpgtu.sci.b a0, a1, 7
0x7b,0xf4,0xf4,0x37 == cv.cmpgtu.sci.b s0, s1, 63
0xfb,0x02,0x73,0x3c == cv.cmpgeu.h t0, t1, t2
0x7b,0x8e,0xee,0x3d == cv.cmpgeu.h t3, t4, t5
0x7b,0x85,0xc5,0x3c == cv.cmpgeu.h a0, a1, a2
0x7b,0x84,0x24,0x3d == cv.cmpgeu.h s0, s1, s2
0xfb,0x12,0x73,0x3c == cv.cmpgeu.b t0, t1, t2
0x7b,0x9e,0xee,0x3d == cv.cmpgeu.b t3, t4, t5
0x7b,0x95,0xc5,0x3c == cv.cmpgeu.b a0, a1, a2
0x7b,0x94,0x24,0x3d == cv.cmpgeu.b s0, s1, s2
0xfb,0x42,0x73,0x3c == cv.cmpgeu.sc.h t0, t1, t2
0x7b,0xce,0xee,0x3d == cv.cmpgeu.sc.h t3, t4, t5
0x7b,0xc5,0xc5,0x3c == cv.cmpgeu.sc.h a0, a1, a2
0x7b,0xc4,0x24,0x3d == cv.cmpgeu.sc.h s0, s1, s2
0xfb,0x52,0x73,0x3c == cv.cmpgeu.sc.b t0, t1, t2
0x7b,0xde,0xee,0x3d == cv.cmpgeu.sc.b t3, t4, t5
0x7b,0xd5,0xc5,0x3c == cv.cmpgeu.sc.b a0, a1, a2
0x7b,0xd4,0x24,0x3d == cv.cmpgeu.sc.b s0, s1, s2
0xfb,0x62,0x03,0x3c == cv.cmpgeu.sci.h t0, t1, 0
0x7b,0xee,0x0e,0x3d == cv.cmpgeu.sci.h t3, t4, 32
0x7b,0xe5,0x35,0x3e == cv.cmpgeu.sci.h a0, a1, 7
0x7b,0xe4,0xf4,0x3f == cv.cmpgeu.sci.h s0, s1, 63
0xfb,0x72,0x03,0x3c == cv.cmpgeu.sci.b t0, t1, 0
0x7b,0xfe,0x0e,0x3d == cv.cmpgeu.sci.b t3, t4, 32
0x7b,0xf5,0x35,0x3e == cv.cmpgeu.sci.b a0, a1, 7
0x7b,0xf4,0xf4,0x3f == cv.cmpgeu.sci.b s0, s1, 63
0xfb,0x02,0x73,0x44 == cv.cmpltu.h t0, t1, t2
0x7b,0x8e,0xee,0x45 == cv.cmpltu.h t3, t4, t5
0x7b,0x85,0xc5,0x44 == cv.cmpltu.h a0, a1, a2
0x7b,0x84,0x24,0x45 == cv.cmpltu.h s0, s1, s2
0xfb,0x12,0x73,0x44 == cv.cmpltu.b t0, t1, t2
0x7b,0x9e,0xee,0x45 == cv.cmpltu.b t3, t4, t5
0x7b,0x95,0xc5,0x44 == cv.cmpltu.b a0, a1, a2
0x7b,0x94,0x24,0x45 == cv.cmpltu.b s0, s1, s2
0xfb,0x42,0x73,0x44 == cv.cmpltu.sc.h t0, t1, t2
0x7b,0xce,0xee,0x45 == cv.cmpltu.sc.h t3, t4, t5
0x7b,0xc5,0xc5,0x44 == cv.cmpltu.sc.h a0, a1, a2
0x7b,0xc4,0x24,0x45 == cv.cmpltu.sc.h s0, s1, s2
0xfb,0x52,0x73,0x44 == cv.cmpltu.sc.b t0, t1, t2
0x7b,0xde,0xee,0x45 == cv.cmpltu.sc.b t3, t4, t5
0x7b,0xd5,0xc5,0x44 == cv.cmpltu.sc.b a0, a1, a2
0x7b,0xd4,0x24,0x45 == cv.cmpltu.sc.b s0, s1, s2
0xfb,0x62,0x03,0x44 == cv.cmpltu.sci.h t0, t1, 0
0x7b,0xee,0x0e,0x45 == cv.cmpltu.sci.h t3, t4, 32
0x7b,0xe5,0x35,0x46 == cv.cmpltu.sci.h a0, a1, 7
0x7b,0xe4,0xf4,0x47 == cv.cmpltu.sci.h s0, s1, 63
0xfb,0x72,0x03,0x44 == cv.cmpltu.sci.b t0, t1, 0
0x7b,0xfe,0x0e,0x45 == cv.cmpltu.sci.b t3, t4, 32
0x7b,0xf5,0x35,0x46 == cv.cmpltu.sci.b a0, a1, 7
0x7b,0xf4,0xf4,0x47 == cv.cmpltu.sci.b s0, s1, 63
0xfb,0x02,0x73,0x4c == cv.cmpleu.h t0, t1, t2
0x7b,0x8e,0xee,0x4d == cv.cmpleu.h t3, t4, t5
0x7b,0x85,0xc5,0x4c == cv.cmpleu.h a0, a1, a2
0x7b,0x84,0x24,0x4d == cv.cmpleu.h s0, s1, s2
0xfb,0x12,0x73,0x4c == cv.cmpleu.b t0, t1, t2
0x7b,0x9e,0xee,0x4d == cv.cmpleu.b t3, t4, t5
0x7b,0x95,0xc5,0x4c == cv.cmpleu.b a0, a1, a2
0x7b,0x94,0x24,0x4d == cv.cmpleu.b s0, s1, s2
0xfb,0x42,0x73,0x4c == cv.cmpleu.sc.h t0, t1, t2
0x7b,0xce,0xee,0x4d == cv.cmpleu.sc.h t3, t4, t5
0x7b,0xc5,0xc5,0x4c == cv.cmpleu.sc.h a0, a1, a2
0x7b,0xc4,0x24,0x4d == cv.cmpleu.sc.h s0, s1, s2
0xfb,0x52,0x73,0x4c == cv.cmpleu.sc.b t0, t1, t2
0x7b,0xde,0xee,0x4d == cv.cmpleu.sc.b t3, t4, t5
0x7b,0xd5,0xc5,0x4c == cv.cmpleu.sc.b a0, a1, a2
0x7b,0xd4,0x24,0x4d == cv.cmpleu.sc.b s0, s1, s2
0xfb,0x62,0x03,0x4c == cv.cmpleu.sci.h t0, t1, 0
0x7b,0xee,0x0e,0x4d == cv.cmpleu.sci.h t3, t4, 32
0x7b,0xe5,0x35,0x4e == cv.cmpleu.sci.h a0, a1, 7
0x7b,0xe4,0xf4,0x4f == cv.cmpleu.sci.h s0, s1, 63
0xfb,0x72,0x03,0x4c == cv.cmpleu.sci.b t0, t1, 0
0x7b,0xfe,0x0e,0x4d == cv.cmpleu.sci.b t3, t4, 32
0x7b,0xf5,0x35,0x4e == cv.cmpleu.sci.b a0, a1, 7
0x7b,0xf4,0xf4,0x4f == cv.cmpleu.sci.b s0, s1, 63
0xfb,0x02,0x73,0x54 == cv.cplxmul.r t0, t1, t2
0x7b,0x8e,0xee,0x55 == cv.cplxmul.r t3, t4, t5
0x7b,0x85,0xc5,0x54 == cv.cplxmul.r a0, a1, a2
0x7b,0x84,0x24,0x55 == cv.cplxmul.r s0, s1, s2
0xfb,0x02,0x73,0x56 == cv.cplxmul.i t0, t1, t2
0x7b,0x8e,0xee,0x57 == cv.cplxmul.i t3, t4, t5
0x7b,0x85,0xc5,0x56 == cv.cplxmul.i a0, a1, a2
0x7b,0x84,0x24,0x57 == cv.cplxmul.i s0, s1, s2
0xfb,0x22,0x73,0x54 == cv.cplxmul.r.div2 t0, t1, t2
0x7b,0xae,0xee,0x55 == cv.cplxmul.r.div2 t3, t4, t5
0x7b,0xa5,0xc5,0x54 == cv.cplxmul.r.div2 a0, a1, a2
0x7b,0xa4,0x24,0x55 == cv.cplxmul.r.div2 s0, s1, s2
0xfb,0x22,0x73,0x56 == cv.cplxmul.i.div2 t0, t1, t2
0x7b,0xae,0xee,0x57 == cv.cplxmul.i.div2 t3, t4, t5
0x7b,0xa5,0xc5,0x56 == cv.cplxmul.i.div2 a0, a1, a2
0x7b,0xa4,0x24,0x57 == cv.cplxmul.i.div2 s0, s1, s2
0xfb,0x42,0x73,0x54 == cv.cplxmul.r.div4 t0, t1, t2
0x7b,0xce,0xee,0x55 == cv.cplxmul.r.div4 t3, t4, t5
0x7b,0xc5,0xc5,0x54 == cv.cplxmul.r.div4 a0, a1, a2
0x7b,0xc4,0x24,0x55 == cv.cplxmul.r.div4 s0, s1, s2
0xfb,0x42,0x73,0x56 == cv.cplxmul.i.div4 t0, t1, t2
0x7b,0xce,0xee,0x57 == cv.cplxmul.i.div4 t3, t4, t5
0x7b,0xc5,0xc5,0x56 == cv.cplxmul.i.div4 a0, a1, a2
0x7b,0xc4,0x24,0x57 == cv.cplxmul.i.div4 s0, s1, s2
0xfb,0x62,0x73,0x54 == cv.cplxmul.r.div8 t0, t1, t2
0x7b,0xee,0xee,0x55 == cv.cplxmul.r.div8 t3, t4, t5
0x7b,0xe5,0xc5,0x54 == cv.cplxmul.r.div8 a0, a1, a2
0x7b,0xe4,0x24,0x55 == cv.cplxmul.r.div8 s0, s1, s2
0xfb,0x62,0x73,0x56 == cv.cplxmul.i.div8 t0, t1, t2
0x7b,0xee,0xee,0x57 == cv.cplxmul.i.div8 t3, t4, t5
0x7b,0xe5,0xc5,0x56 == cv.cplxmul.i.div8 a0, a1, a2
0x7b,0xe4,0x24,0x57 == cv.cplxmul.i.div8 s0, s1, s2
0xfb,0x02,0x03,0x5c == cv.cplxconj t0, t1
0x7b,0x8e,0x0e,0x5c == cv.cplxconj t3, t4
0x7b,0x85,0x05,0x5c == cv.cplxconj a0, a1
0x7b,0x84,0x04,0x5c == cv.cplxconj s0, s1
0xfb,0x02,0x73,0x64 == cv.subrotmj t0, t1, t2
0x7b,0x8e,0xee,0x65 == cv.subrotmj t3, t4, t5
0x7b,0x85,0xc5,0x64 == cv.subrotmj a0, a1, a2
0x7b,0x84,0x24,0x65 == cv.subrotmj s0, s1, s2
0xfb,0x22,0x73,0x64 == cv.subrotmj.div2 t0, t1, t2
0x7b,0xae,0xee,0x65 == cv.subrotmj.div2 t3, t4, t5
0x7b,0xa5,0xc5,0x64 == cv.subrotmj.div2 a0, a1, a2
0x7b,0xa4,0x24,0x65 == cv.subrotmj.div2 s0, s1, s2
0xfb,0x42,0x73,0x64 == cv.subrotmj.div4 t0, t1, t2
0x7b,0xce,0xee,0x65 == cv.subrotmj.div4 t3, t4, t5
0x7b,0xc5,0xc5,0x64 == cv.subrotmj.div4 a0, a1, a2
0x7b,0xc4,0x24,0x65 == cv.subrotmj.div4 s0, s1, s2
0xfb,0x62,0x73,0x64 == cv.subrotmj.div8 t0, t1, t2
0x7b,0xee,0xee,0x65 == cv.subrotmj.div8 t3, t4, t5
0x7b,0xe5,0xc5,0x64 == cv.subrotmj.div8 a0, a1, a2
0x7b,0xe4,0x24,0x65 == cv.subrotmj.div8 s0, s1, s2
0xfb,0x22,0x73,0x6c == cv.add.div2 t0, t1, t2
0x7b,0xae,0xee,0x6d == cv.add.div2 t3, t4, t5
0x7b,0xa5,0xc5,0x6c == cv.add.div2 a0, a1, a2
0x7b,0xa4,0x24,0x6d == cv.add.div2 s0, s1, s2
0xfb,0x42,0x73,0x6c == cv.add.div4 t0, t1, t2
0x7b,0xce,0xee,0x6d == cv.add.div4 t3, t4, t5
0x7b,0xc5,0xc5,0x6c == cv.add.div4 a0, a1, a2
0x7b,0xc4,0x24,0x6d == cv.add.div4 s0, s1, s2
0xfb,0x62,0x73,0x6c == cv.add.div8 t0, t1, t2
0x7b,0xee,0xee,0x6d == cv.add.div8 t3, t4, t5
0x7b,0xe5,0xc5,0x6c == cv.add.div8 a0, a1, a2
0x7b,0xe4,0x24,0x6d == cv.add.div8 s0, s1, s2
0xfb,0x22,0x73,0x74 == cv.sub.div2 t0, t1, t2
0x7b,0xae,0xee,0x75 == cv.sub.div2 t3, t4, t5
0x7b,0xa5,0xc5,0x74 == cv.sub.div2 a0, a1, a2
0x7b,0xa4,0x24,0x75 == cv.sub.div2 s0, s1, s2
0xfb,0x42,0x73,0x74 == cv.sub.div4 t0, t1, t2
0x7b,0xce,0xee,0x75 == cv.sub.div4 t3, t4, t5
0x7b,0xc5,0xc5,0x74 == cv.sub.div4 a0, a1, a2
0x7b,0xc4,0x24,0x75 == cv.sub.div4 s0, s1, s2
0xfb,0x62,0x73,0x74 == cv.sub.div8 t0, t1, t2
0x7b,0xee,0xee,0x75 == cv.sub.div8 t3, t4, t5
0x7b,0xe5,0xc5,0x74 == cv.sub.div8 a0, a1, a2
0x7b,0xe4,0x24,0x75 == cv.sub.div8 s0, s1, s2
suite/MC/RISCV/XTHeadBa_valid_riscv32_riscv_xtheadba.txt.cs
+5
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@@ -0,0 +1,5 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32"|"CS_MODE_RISCV_XTHEADBA", None
0x8b,0x12,0x73,0x00 == th.addsl t0, t1, t2, 0
0x8b,0x12,0x73,0x02 == th.addsl t0, t1, t2, 1
0x8b,0x12,0x73,0x04 == th.addsl t0, t1, t2, 2
0x8b,0x12,0x73,0x06 == th.addsl t0, t1, t2, 3
suite/MC/RISCV/XTHeadVdot_valid_riscv64_riscv_xtheadvdot.txt.cs
+15
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@@ -0,0 +1,15 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV64"|"CS_MODE_RISCV_XTHEADVDOT", None
0x0b,0x64,0x4a,0x88 == th.vmaqau.vv v8, v20, v4, v0.t
0x0b,0x64,0x4a,0x8a == th.vmaqau.vv v8, v20, v4
0x0b,0x64,0x45,0x8c == th.vmaqau.vx v8, a0, v4, v0.t
0x0b,0x64,0x45,0x8e == th.vmaqau.vx v8, a0, v4
0x0b,0x64,0x4a,0x80 == th.vmaqa.vv v8, v20, v4, v0.t
0x0b,0x64,0x4a,0x82 == th.vmaqa.vv v8, v20, v4
0x0b,0x64,0x45,0x84 == th.vmaqa.vx v8, a0, v4, v0.t
0x0b,0x64,0x45,0x86 == th.vmaqa.vx v8, a0, v4
0x0b,0x64,0x4a,0x90 == th.vmaqasu.vv v8, v20, v4, v0.t
0x0b,0x64,0x4a,0x92 == th.vmaqasu.vv v8, v20, v4
0x0b,0x64,0x45,0x94 == th.vmaqasu.vx v8, a0, v4, v0.t
0x0b,0x64,0x45,0x96 == th.vmaqasu.vx v8, a0, v4
0x0b,0x64,0x45,0x9c == th.vmaqaus.vx v8, a0, v4, v0.t
0x0b,0x64,0x45,0x9e == th.vmaqaus.vx v8, a0, v4
suite/MC/RISCV/XVentanaCondOps_valid_riscv64_xventanacondops_syntax_no_alias_text.txt.cs
+5
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@@ -0,0 +1,5 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV64", None
0x7b,0x60,0x00,0x00 == vt.maskc zero, zero, zero
0x7b,0x70,0x00,0x00 == vt.maskcn zero, zero, zero
0xfb,0x60,0x31,0x00 == vt.maskc ra, sp, gp
0xfb,0x70,0x31,0x00 == vt.maskcn ra, sp, gp
suite/MC/RISCV/Zawrs_valid_riscv32_zawrs_syntax_no_alias_text.txt.cs
+3
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@@ -0,0 +1,3 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32", None
0x73,0x00,0xd0,0x00 == wrs.nto
0x73,0x00,0xd0,0x01 == wrs.sto
suite/MC/RISCV/add_riscv64_riscv_v.txt.cs
+60
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@@ -0,0 +1,60 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV64"|"CS_MODE_RISCV_V", None
0x57,0x04,0x4a,0x00 == vadd.vv v8, v4, v20, v0.t
0x57,0x04,0x4a,0x02 == vadd.vv v8, v4, v20
0x57,0x44,0x45,0x00 == vadd.vx v8, v4, a0, v0.t
0x57,0x44,0x45,0x02 == vadd.vx v8, v4, a0
0x57,0xb4,0x47,0x00 == vadd.vi v8, v4, 15, v0.t
0x57,0xb4,0x47,0x02 == vadd.vi v8, v4, 15
0x57,0x24,0x4a,0xc0 == vwaddu.vv v8, v4, v20, v0.t
0x57,0x24,0x4a,0xc2 == vwaddu.vv v8, v4, v20
0x57,0x64,0x45,0xc0 == vwaddu.vx v8, v4, a0, v0.t
0x57,0x64,0x45,0xc2 == vwaddu.vx v8, v4, a0
0x57,0x24,0x4a,0xc4 == vwadd.vv v8, v4, v20, v0.t
0x57,0x24,0x4a,0xc6 == vwadd.vv v8, v4, v20
0x57,0x64,0x45,0xc4 == vwadd.vx v8, v4, a0, v0.t
0x57,0x64,0x45,0xc6 == vwadd.vx v8, v4, a0
0x57,0x24,0x4a,0xd0 == vwaddu.wv v8, v4, v20, v0.t
0x57,0x24,0x4a,0xd2 == vwaddu.wv v8, v4, v20
0x57,0x64,0x45,0xd0 == vwaddu.wx v8, v4, a0, v0.t
0x57,0x64,0x45,0xd2 == vwaddu.wx v8, v4, a0
0x57,0x24,0x4a,0xd4 == vwadd.wv v8, v4, v20, v0.t
0x57,0x24,0x4a,0xd6 == vwadd.wv v8, v4, v20
0x57,0x64,0x45,0xd4 == vwadd.wx v8, v4, a0, v0.t
0x57,0x64,0x45,0xd6 == vwadd.wx v8, v4, a0
0x57,0x04,0x4a,0x40 == vadc.vvm v8, v4, v20, v0
0x57,0x02,0x4a,0x40 == vadc.vvm v4, v4, v20, v0
0x57,0x04,0x44,0x40 == vadc.vvm v8, v4, v8, v0
0x57,0x44,0x45,0x40 == vadc.vxm v8, v4, a0, v0
0x57,0xb4,0x47,0x40 == vadc.vim v8, v4, 15, v0
0x57,0x04,0x4a,0x44 == vmadc.vvm v8, v4, v20, v0
0x57,0x02,0x4a,0x44 == vmadc.vvm v4, v4, v20, v0
0x57,0x04,0x44,0x44 == vmadc.vvm v8, v4, v8, v0
0x57,0x44,0x45,0x44 == vmadc.vxm v8, v4, a0, v0
0x57,0xb4,0x47,0x44 == vmadc.vim v8, v4, 15, v0
0x57,0x04,0x4a,0x46 == vmadc.vv v8, v4, v20
0x57,0x44,0x45,0x46 == vmadc.vx v8, v4, a0
0x57,0xb4,0x47,0x46 == vmadc.vi v8, v4, 15
0x57,0x04,0x4a,0x80 == vsaddu.vv v8, v4, v20, v0.t
0x57,0x04,0x4a,0x82 == vsaddu.vv v8, v4, v20
0x57,0x44,0x45,0x80 == vsaddu.vx v8, v4, a0, v0.t
0x57,0x44,0x45,0x82 == vsaddu.vx v8, v4, a0
0x57,0xb4,0x47,0x80 == vsaddu.vi v8, v4, 15, v0.t
0x57,0xb4,0x47,0x82 == vsaddu.vi v8, v4, 15
0x57,0x04,0x4a,0x84 == vsadd.vv v8, v4, v20, v0.t
0x57,0x04,0x4a,0x86 == vsadd.vv v8, v4, v20
0x57,0x44,0x45,0x84 == vsadd.vx v8, v4, a0, v0.t
0x57,0x44,0x45,0x86 == vsadd.vx v8, v4, a0
0x57,0xb4,0x47,0x84 == vsadd.vi v8, v4, 15, v0.t
0x57,0xb4,0x47,0x86 == vsadd.vi v8, v4, 15
0x57,0x24,0x4a,0x24 == vaadd.vv v8, v4, v20, v0.t
0x57,0x24,0x4a,0x26 == vaadd.vv v8, v4, v20
0x57,0x64,0x45,0x24 == vaadd.vx v8, v4, a0, v0.t
0x57,0x64,0x45,0x26 == vaadd.vx v8, v4, a0
0x57,0x24,0x4a,0x20 == vaaddu.vv v8, v4, v20, v0.t
0x57,0x24,0x4a,0x22 == vaaddu.vv v8, v4, v20
0x57,0x64,0x45,0x20 == vaaddu.vx v8, v4, a0, v0.t
0x57,0x64,0x45,0x22 == vaaddu.vx v8, v4, a0
0x57,0x64,0x40,0xc4 == vwcvt.x.x.v v8, v4, v0.t
0x57,0x64,0x40,0xc6 == vwcvt.x.x.v v8, v4
0x57,0x64,0x40,0xc0 == vwcvtu.x.x.v v8, v4, v0.t
0x57,0x64,0x40,0xc2 == vwcvtu.x.x.v v8, v4
suite/MC/RISCV/and_riscv64_riscv_v.txt.cs
+7
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@@ -0,0 +1,7 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV64"|"CS_MODE_RISCV_V", None
0x57,0x04,0x4a,0x24 == vand.vv v8, v4, v20, v0.t
0x57,0x04,0x4a,0x26 == vand.vv v8, v4, v20
0x57,0x44,0x45,0x24 == vand.vx v8, v4, a0, v0.t
0x57,0x44,0x45,0x26 == vand.vx v8, v4, a0
0x57,0xb4,0x47,0x24 == vand.vi v8, v4, 15, v0.t
0x57,0xb4,0x47,0x26 == vand.vi v8, v4, 15
suite/MC/RISCV/clip_riscv64_riscv_v.txt.cs
+13
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@@ -0,0 +1,13 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV64"|"CS_MODE_RISCV_V", None
0x57,0x04,0x4a,0xb8 == vnclipu.wv v8, v4, v20, v0.t
0x57,0x04,0x4a,0xba == vnclipu.wv v8, v4, v20
0x57,0x44,0x45,0xb8 == vnclipu.wx v8, v4, a0, v0.t
0x57,0x44,0x45,0xba == vnclipu.wx v8, v4, a0
0x57,0xb4,0x4f,0xb8 == vnclipu.wi v8, v4, 31, v0.t
0x57,0xb4,0x4f,0xba == vnclipu.wi v8, v4, 31
0x57,0x04,0x4a,0xbc == vnclip.wv v8, v4, v20, v0.t
0x57,0x04,0x4a,0xbe == vnclip.wv v8, v4, v20
0x57,0x44,0x45,0xbc == vnclip.wx v8, v4, a0, v0.t
0x57,0x44,0x45,0xbe == vnclip.wx v8, v4, a0
0x57,0xb4,0x4f,0xbc == vnclip.wi v8, v4, 31, v0.t
0x57,0xb4,0x4f,0xbe == vnclip.wi v8, v4, 31
suite/MC/RISCV/compare_riscv64_riscv_v.txt.cs
+58
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@@ -0,0 +1,58 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV64"|"CS_MODE_RISCV_V", None
0x57,0x00,0x4a,0x6c == vmslt.vv v0, v4, v20, v0.t
0x57,0x04,0x4a,0x60 == vmseq.vv v8, v4, v20, v0.t
0x57,0x04,0x4a,0x62 == vmseq.vv v8, v4, v20
0x57,0x44,0x45,0x60 == vmseq.vx v8, v4, a0, v0.t
0x57,0x44,0x45,0x62 == vmseq.vx v8, v4, a0
0x57,0xb4,0x47,0x60 == vmseq.vi v8, v4, 15, v0.t
0x57,0xb4,0x47,0x62 == vmseq.vi v8, v4, 15
0x57,0x04,0x4a,0x64 == vmsne.vv v8, v4, v20, v0.t
0x57,0x04,0x4a,0x66 == vmsne.vv v8, v4, v20
0x57,0x44,0x45,0x64 == vmsne.vx v8, v4, a0, v0.t
0x57,0x44,0x45,0x66 == vmsne.vx v8, v4, a0
0x57,0xb4,0x47,0x64 == vmsne.vi v8, v4, 15, v0.t
0x57,0xb4,0x47,0x66 == vmsne.vi v8, v4, 15
0x57,0x04,0x4a,0x68 == vmsltu.vv v8, v4, v20, v0.t
0x57,0x04,0x4a,0x6a == vmsltu.vv v8, v4, v20
0x57,0x44,0x45,0x68 == vmsltu.vx v8, v4, a0, v0.t
0x57,0x44,0x45,0x6a == vmsltu.vx v8, v4, a0
0x57,0x04,0x4a,0x6c == vmslt.vv v8, v4, v20, v0.t
0x57,0x04,0x4a,0x6e == vmslt.vv v8, v4, v20
0x57,0x44,0x45,0x6c == vmslt.vx v8, v4, a0, v0.t
0x57,0x44,0x45,0x6e == vmslt.vx v8, v4, a0
0x57,0x04,0x4a,0x70 == vmsleu.vv v8, v4, v20, v0.t
0x57,0x04,0x4a,0x72 == vmsleu.vv v8, v4, v20
0x57,0x44,0x45,0x70 == vmsleu.vx v8, v4, a0, v0.t
0x57,0x44,0x45,0x72 == vmsleu.vx v8, v4, a0
0x57,0xb4,0x47,0x70 == vmsleu.vi v8, v4, 15, v0.t
0x57,0xb4,0x47,0x72 == vmsleu.vi v8, v4, 15
0x57,0x04,0x4a,0x74 == vmsle.vv v8, v4, v20, v0.t
0x57,0x04,0x4a,0x76 == vmsle.vv v8, v4, v20
0x57,0x44,0x45,0x74 == vmsle.vx v8, v4, a0, v0.t
0x57,0x44,0x45,0x76 == vmsle.vx v8, v4, a0
0x57,0xb4,0x47,0x74 == vmsle.vi v8, v4, 15, v0.t
0x57,0xb4,0x47,0x76 == vmsle.vi v8, v4, 15
0x57,0x44,0x45,0x78 == vmsgtu.vx v8, v4, a0, v0.t
0x57,0x44,0x45,0x7a == vmsgtu.vx v8, v4, a0
0x57,0xb4,0x47,0x78 == vmsgtu.vi v8, v4, 15, v0.t
0x57,0xb4,0x47,0x7a == vmsgtu.vi v8, v4, 15
0x57,0x44,0x45,0x7c == vmsgt.vx v8, v4, a0, v0.t
0x57,0x44,0x45,0x7e == vmsgt.vx v8, v4, a0
0x57,0xb4,0x47,0x7c == vmsgt.vi v8, v4, 15, v0.t
0x57,0xb4,0x47,0x7e == vmsgt.vi v8, v4, 15
0x57,0x04,0x42,0x64 == vmsne.vv v8, v4, v4, v0.t
0x57,0x04,0x42,0x66 == vmsne.vv v8, v4, v4
0x57,0x04,0x42,0x60 == vmseq.vv v8, v4, v4, v0.t
0x57,0x04,0x42,0x62 == vmseq.vv v8, v4, v4
0x57,0x24,0x84,0x76 == vmnot.m v8, v8
0x57,0x40,0x45,0x6e == vmslt.vx v0, v4, a0
0x57,0x20,0x00,0x76 == vmnot.m v0, v0
0x57,0x24,0x80,0x6e == vmxor.mm v8, v8, v0
0x57,0x41,0x45,0x6a == vmsltu.vx v2, v4, a0
0x57,0x20,0x01,0x62 == vmandn.mm v0, v0, v2
0x57,0x41,0x45,0x6e == vmslt.vx v2, v4, a0
0x57,0x21,0x01,0x62 == vmandn.mm v2, v0, v2
0xd7,0x24,0x90,0x62 == vmandn.mm v9, v9, v0
0xd7,0xa4,0x24,0x6a == vmor.mm v9, v2, v9
0x57,0x24,0x80,0x62 == vmandn.mm v8, v8, v0
0x57,0x24,0x24,0x6a == vmor.mm v8, v2, v8
suite/MC/RISCV/compress_cjal_riscv32_riscv_c.txt.cs
+2
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@@ -0,0 +1,2 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32"|"CS_MODE_RISCV_C", None
0xfd,0x2f == jal 2046
suite/MC/RISCV/compress_rv32d_riscv32_riscv_c_riscv_d.txt.cs
+5
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@@ -0,0 +1,5 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32"|"CS_MODE_RISCV_C"|"CS_MODE_RISCV_D", None
0x06,0x20 == fld ft0, 64(sp)
0x82,0xa0 == fsd ft0, 64(sp)
0x60,0x3c == fld fs0, 248(s0)
0x60,0xbc == fsd fs0, 248(s0)
suite/MC/RISCV/compress_rv32f_riscv32_riscv_c_riscv_f.txt.cs
+5
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@@ -0,0 +1,5 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32"|"CS_MODE_RISCV_C"|"CS_MODE_RISCV_F", None
0x76,0x70 == flw ft0, 124(sp)
0x82,0xfe == fsw ft0, 124(sp)
0x60,0x7c == flw fs0, 124(s0)
0x60,0xfc == fsw fs0, 124(s0)
suite/MC/RISCV/compress_rv32i_riscv32_riscv_c.txt.cs
+30
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@@ -0,0 +1,30 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32"|"CS_MODE_RISCV_C", None
0x2e,0x85 == mv a0, a1
0xe0,0x1f == addi s0, sp, 1020
0xe0,0x5f == lw s0, 124(a5)
0xe0,0xdf == sw s0, 124(a5)
0x01,0x00 == nop
0x81,0x10 == addi ra, ra, -32
0x85,0x50 == li ra, -31
0x39,0x71 == addi sp, sp, -64
0xfd,0x61 == lui gp, 31
0x7d,0x80 == srli s0, s0, 31
0x7d,0x84 == srai s0, s0, 31
0x7d,0x88 == andi s0, s0, 31
0x1d,0x8c == sub s0, s0, a5
0x3d,0x8c == xor s0, s0, a5
0x5d,0x8c == or s0, s0, a5
0x45,0x8c == or s0, s0, s1
0x7d,0x8c == and s0, s0, a5
0x01,0xb0 == j -2048
0x01,0xd0 == beqz s0, -256
0x7d,0xec == bnez s0, 254
0x7e,0x04 == slli s0, s0, 31
0xfe,0x50 == lw ra, 252(sp)
0x82,0x80 == ret
0x92,0x80 == mv ra, tp
0x02,0x90 == ebreak
0x02,0x94 == jalr s0
0x3e,0x94 == add s0, s0, a5
0x82,0xdf == sw zero, 252(sp)
0x00,0x00 == unimp
suite/MC/RISCV/compress_rv64i_riscv64_riscv_c.txt.cs
+8
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@@ -0,0 +1,8 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV64"|"CS_MODE_RISCV_C", None
0xe0,0x7f == ld s0, 248(a5)
0xa0,0xe3 == sd s0, 64(a5)
0x7d,0x22 == addiw tp, tp, 31
0x1d,0x9c == subw s0, s0, a5
0x3d,0x9c == addw s0, s0, a5
0xee,0x70 == ld ra, 248(sp)
0xa2,0xe0 == sd s0, 64(sp)
suite/MC/RISCV/compressed_zicfiss_riscv32_riscv_experimental_zicfiss__experimental_zcmop_syntax_no_alias_text.txt.cs
+3
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@@ -0,0 +1,3 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32"|"CS_MODE_RISCV_EXPERIMENTAL_ZICFISS", None
0x81,0x62 == c.sspopchk t0
0x81,0x60 == c.sspush ra
suite/MC/RISCV/convert_riscv64_riscv_v_riscv_f.txt.cs
+44
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@@ -0,0 +1,44 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV64"|"CS_MODE_RISCV_V"|"CS_MODE_RISCV_F", None
0x57,0x14,0x40,0x48 == vfcvt.xu.f.v v8, v4, v0.t
0x57,0x14,0x40,0x4a == vfcvt.xu.f.v v8, v4
0x57,0x94,0x40,0x48 == vfcvt.x.f.v v8, v4, v0.t
0x57,0x94,0x40,0x4a == vfcvt.x.f.v v8, v4
0x57,0x14,0x41,0x48 == vfcvt.f.xu.v v8, v4, v0.t
0x57,0x14,0x41,0x4a == vfcvt.f.xu.v v8, v4
0x57,0x94,0x41,0x48 == vfcvt.f.x.v v8, v4, v0.t
0x57,0x94,0x41,0x4a == vfcvt.f.x.v v8, v4
0x57,0x14,0x43,0x48 == vfcvt.rtz.xu.f.v v8, v4, v0.t
0x57,0x14,0x43,0x4a == vfcvt.rtz.xu.f.v v8, v4
0x57,0x94,0x43,0x48 == vfcvt.rtz.x.f.v v8, v4, v0.t
0x57,0x94,0x43,0x4a == vfcvt.rtz.x.f.v v8, v4
0x57,0x14,0x44,0x48 == vfwcvt.xu.f.v v8, v4, v0.t
0x57,0x14,0x44,0x4a == vfwcvt.xu.f.v v8, v4
0x57,0x94,0x44,0x48 == vfwcvt.x.f.v v8, v4, v0.t
0x57,0x94,0x44,0x4a == vfwcvt.x.f.v v8, v4
0x57,0x14,0x45,0x48 == vfwcvt.f.xu.v v8, v4, v0.t
0x57,0x14,0x45,0x4a == vfwcvt.f.xu.v v8, v4
0x57,0x94,0x45,0x48 == vfwcvt.f.x.v v8, v4, v0.t
0x57,0x94,0x45,0x4a == vfwcvt.f.x.v v8, v4
0x57,0x14,0x46,0x48 == vfwcvt.f.f.v v8, v4, v0.t
0x57,0x14,0x46,0x4a == vfwcvt.f.f.v v8, v4
0x57,0x14,0x47,0x48 == vfwcvt.rtz.xu.f.v v8, v4, v0.t
0x57,0x14,0x47,0x4a == vfwcvt.rtz.xu.f.v v8, v4
0x57,0x94,0x47,0x48 == vfwcvt.rtz.x.f.v v8, v4, v0.t
0x57,0x94,0x47,0x4a == vfwcvt.rtz.x.f.v v8, v4
0x57,0x14,0x48,0x48 == vfncvt.xu.f.w v8, v4, v0.t
0x57,0x12,0x48,0x48 == vfncvt.xu.f.w v4, v4, v0.t
0x57,0x14,0x48,0x4a == vfncvt.xu.f.w v8, v4
0x57,0x94,0x48,0x48 == vfncvt.x.f.w v8, v4, v0.t
0x57,0x94,0x48,0x4a == vfncvt.x.f.w v8, v4
0x57,0x14,0x49,0x48 == vfncvt.f.xu.w v8, v4, v0.t
0x57,0x14,0x49,0x4a == vfncvt.f.xu.w v8, v4
0x57,0x94,0x49,0x48 == vfncvt.f.x.w v8, v4, v0.t
0x57,0x94,0x49,0x4a == vfncvt.f.x.w v8, v4
0x57,0x14,0x4a,0x48 == vfncvt.f.f.w v8, v4, v0.t
0x57,0x14,0x4a,0x4a == vfncvt.f.f.w v8, v4
0x57,0x94,0x4a,0x48 == vfncvt.rod.f.f.w v8, v4, v0.t
0x57,0x94,0x4a,0x4a == vfncvt.rod.f.f.w v8, v4
0x57,0x14,0x4b,0x48 == vfncvt.rtz.xu.f.w v8, v4, v0.t
0x57,0x14,0x4b,0x4a == vfncvt.rtz.xu.f.w v8, v4
0x57,0x94,0x4b,0x48 == vfncvt.rtz.x.f.w v8, v4, v0.t
0x57,0x94,0x4b,0x4a == vfncvt.rtz.x.f.w v8, v4
suite/MC/RISCV/debug_valid_riscv32_syntax_no_alias_text.txt.cs
+2
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@@ -0,0 +1,2 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32", None
0x73,0x00,0x20,0x7b == dret
suite/MC/RISCV/deprecated_csr_names_riscv32_syntax_no_alias_text.txt.cs
+4
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@@ -0,0 +1,4 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32", None
0x73,0x10,0x30,0x14 == csrrw zero, stval, zero
0x73,0x10,0x30,0x34 == csrrw zero, mtval, zero
0x73,0x10,0x00,0x18 == csrrw zero, satp, zero
suite/MC/RISCV/div_riscv64_riscv_v.txt.cs
+17
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@@ -0,0 +1,17 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV64"|"CS_MODE_RISCV_V", None
0x57,0x24,0x4a,0x80 == vdivu.vv v8, v4, v20, v0.t
0x57,0x24,0x4a,0x82 == vdivu.vv v8, v4, v20
0x57,0x64,0x45,0x80 == vdivu.vx v8, v4, a0, v0.t
0x57,0x64,0x45,0x82 == vdivu.vx v8, v4, a0
0x57,0x24,0x4a,0x84 == vdiv.vv v8, v4, v20, v0.t
0x57,0x24,0x4a,0x86 == vdiv.vv v8, v4, v20
0x57,0x64,0x45,0x84 == vdiv.vx v8, v4, a0, v0.t
0x57,0x64,0x45,0x86 == vdiv.vx v8, v4, a0
0x57,0x24,0x4a,0x88 == vremu.vv v8, v4, v20, v0.t
0x57,0x24,0x4a,0x8a == vremu.vv v8, v4, v20
0x57,0x64,0x45,0x88 == vremu.vx v8, v4, a0, v0.t
0x57,0x64,0x45,0x8a == vremu.vx v8, v4, a0
0x57,0x24,0x4a,0x8c == vrem.vv v8, v4, v20, v0.t
0x57,0x24,0x4a,0x8e == vrem.vv v8, v4, v20
0x57,0x64,0x45,0x8c == vrem.vx v8, v4, a0, v0.t
0x57,0x64,0x45,0x8e == vrem.vx v8, v4, a0
suite/MC/RISCV/ext_riscv64_riscv_v.txt.cs
+13
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@@ -0,0 +1,13 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV64"|"CS_MODE_RISCV_V", None
0x57,0x24,0x43,0x48 == vzext.vf2 v8, v4, v0.t
0x57,0x24,0x43,0x4a == vzext.vf2 v8, v4
0x57,0xa4,0x43,0x48 == vsext.vf2 v8, v4, v0.t
0x57,0xa4,0x43,0x4a == vsext.vf2 v8, v4
0x57,0x24,0x42,0x48 == vzext.vf4 v8, v4, v0.t
0x57,0x24,0x42,0x4a == vzext.vf4 v8, v4
0x57,0xa4,0x42,0x48 == vsext.vf4 v8, v4, v0.t
0x57,0xa4,0x42,0x4a == vsext.vf4 v8, v4
0x57,0x24,0x41,0x48 == vzext.vf8 v8, v4, v0.t
0x57,0x24,0x41,0x4a == vzext.vf8 v8, v4
0x57,0xa4,0x41,0x48 == vsext.vf8 v8, v4, v0.t
0x57,0xa4,0x41,0x4a == vsext.vf8 v8, v4
suite/MC/RISCV/fadd_riscv64_riscv_v_riscv_f.txt.cs
+13
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@@ -0,0 +1,13 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV64"|"CS_MODE_RISCV_V"|"CS_MODE_RISCV_F", None
0x57,0x14,0x4a,0x00 == vfadd.vv v8, v4, v20, v0.t
0x57,0x14,0x4a,0x02 == vfadd.vv v8, v4, v20
0x57,0x54,0x45,0x00 == vfadd.vf v8, v4, fa0, v0.t
0x57,0x54,0x45,0x02 == vfadd.vf v8, v4, fa0
0x57,0x14,0x4a,0xc0 == vfwadd.vv v8, v4, v20, v0.t
0x57,0x14,0x4a,0xc2 == vfwadd.vv v8, v4, v20
0x57,0x54,0x45,0xc0 == vfwadd.vf v8, v4, fa0, v0.t
0x57,0x54,0x45,0xc2 == vfwadd.vf v8, v4, fa0
0x57,0x14,0x4a,0xd0 == vfwadd.wv v8, v4, v20, v0.t
0x57,0x14,0x4a,0xd2 == vfwadd.wv v8, v4, v20
0x57,0x54,0x45,0xd0 == vfwadd.wf v8, v4, fa0, v0.t
0x57,0x54,0x45,0xd2 == vfwadd.wf v8, v4, fa0
suite/MC/RISCV/fcompare_riscv64_riscv_v_riscv_f.txt.cs
+22
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@@ -0,0 +1,22 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV64"|"CS_MODE_RISCV_V"|"CS_MODE_RISCV_F", None
0x57,0x14,0x4a,0x60 == vmfeq.vv v8, v4, v20, v0.t
0x57,0x14,0x4a,0x62 == vmfeq.vv v8, v4, v20
0x57,0x54,0x45,0x60 == vmfeq.vf v8, v4, fa0, v0.t
0x57,0x54,0x45,0x62 == vmfeq.vf v8, v4, fa0
0x57,0x14,0x4a,0x70 == vmfne.vv v8, v4, v20, v0.t
0x57,0x14,0x4a,0x72 == vmfne.vv v8, v4, v20
0x57,0x54,0x45,0x70 == vmfne.vf v8, v4, fa0, v0.t
0x57,0x54,0x45,0x72 == vmfne.vf v8, v4, fa0
0x57,0x14,0x4a,0x6c == vmflt.vv v8, v4, v20, v0.t
0x57,0x14,0x4a,0x6e == vmflt.vv v8, v4, v20
0x57,0x54,0x45,0x6c == vmflt.vf v8, v4, fa0, v0.t
0x57,0x54,0x45,0x6e == vmflt.vf v8, v4, fa0
0x57,0x14,0x4a,0x64 == vmfle.vv v8, v4, v20, v0.t
0x57,0x14,0x4a,0x66 == vmfle.vv v8, v4, v20
0x57,0x54,0x45,0x64 == vmfle.vf v8, v4, fa0, v0.t
0x57,0x54,0x45,0x66 == vmfle.vf v8, v4, fa0
0x57,0x54,0x45,0x74 == vmfgt.vf v8, v4, fa0, v0.t
0x57,0x54,0x45,0x76 == vmfgt.vf v8, v4, fa0
0x57,0x54,0x45,0x7c == vmfge.vf v8, v4, fa0, v0.t
0x57,0x54,0x45,0x7e == vmfge.vf v8, v4, fa0
0x57,0x10,0x4a,0x60 == vmfeq.vv v0, v4, v20, v0.t
suite/MC/RISCV/fdiv_riscv64_riscv_v_riscv_f.txt.cs
+7
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@@ -0,0 +1,7 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV64"|"CS_MODE_RISCV_V"|"CS_MODE_RISCV_F", None
0x57,0x14,0x4a,0x80 == vfdiv.vv v8, v4, v20, v0.t
0x57,0x14,0x4a,0x82 == vfdiv.vv v8, v4, v20
0x57,0x54,0x45,0x80 == vfdiv.vf v8, v4, fa0, v0.t
0x57,0x54,0x45,0x82 == vfdiv.vf v8, v4, fa0
0x57,0x54,0x45,0x84 == vfrdiv.vf v8, v4, fa0, v0.t
0x57,0x54,0x45,0x86 == vfrdiv.vf v8, v4, fa0
suite/MC/RISCV/fixups_compressed_riscv32_riscv_c.txt.cs
+2
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@@ -0,0 +1,2 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32"|"CS_MODE_RISCV_C", None
0x01,0x00 == nop
suite/MC/RISCV/fixups_riscv32_syntax_no_alias_text.txt.cs
+2
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@@ -0,0 +1,2 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32", None
0x13,0x00,0x00,0x00 == addi zero, zero, 0
suite/MC/RISCV/fmacc_riscv64_riscv_v_riscv_f.txt.cs
+49
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@@ -0,0 +1,49 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV64"|"CS_MODE_RISCV_V"|"CS_MODE_RISCV_F", None
0x57,0x14,0x4a,0xb0 == vfmacc.vv v8, v20, v4, v0.t
0x57,0x14,0x4a,0xb2 == vfmacc.vv v8, v20, v4
0x57,0x54,0x45,0xb0 == vfmacc.vf v8, fa0, v4, v0.t
0x57,0x54,0x45,0xb2 == vfmacc.vf v8, fa0, v4
0x57,0x14,0x4a,0xb4 == vfnmacc.vv v8, v20, v4, v0.t
0x57,0x14,0x4a,0xb6 == vfnmacc.vv v8, v20, v4
0x57,0x54,0x45,0xb4 == vfnmacc.vf v8, fa0, v4, v0.t
0x57,0x54,0x45,0xb6 == vfnmacc.vf v8, fa0, v4
0x57,0x14,0x4a,0xb8 == vfmsac.vv v8, v20, v4, v0.t
0x57,0x14,0x4a,0xba == vfmsac.vv v8, v20, v4
0x57,0x54,0x45,0xb8 == vfmsac.vf v8, fa0, v4, v0.t
0x57,0x54,0x45,0xba == vfmsac.vf v8, fa0, v4
0x57,0x14,0x4a,0xbc == vfnmsac.vv v8, v20, v4, v0.t
0x57,0x14,0x4a,0xbe == vfnmsac.vv v8, v20, v4
0x57,0x54,0x45,0xbc == vfnmsac.vf v8, fa0, v4, v0.t
0x57,0x54,0x45,0xbe == vfnmsac.vf v8, fa0, v4
0x57,0x14,0x4a,0xa0 == vfmadd.vv v8, v20, v4, v0.t
0x57,0x14,0x4a,0xa2 == vfmadd.vv v8, v20, v4
0x57,0x54,0x45,0xa0 == vfmadd.vf v8, fa0, v4, v0.t
0x57,0x54,0x45,0xa2 == vfmadd.vf v8, fa0, v4
0x57,0x14,0x4a,0xa4 == vfnmadd.vv v8, v20, v4, v0.t
0x57,0x14,0x4a,0xa6 == vfnmadd.vv v8, v20, v4
0x57,0x54,0x45,0xa4 == vfnmadd.vf v8, fa0, v4, v0.t
0x57,0x54,0x45,0xa6 == vfnmadd.vf v8, fa0, v4
0x57,0x14,0x4a,0xa8 == vfmsub.vv v8, v20, v4, v0.t
0x57,0x14,0x4a,0xaa == vfmsub.vv v8, v20, v4
0x57,0x54,0x45,0xa8 == vfmsub.vf v8, fa0, v4, v0.t
0x57,0x54,0x45,0xaa == vfmsub.vf v8, fa0, v4
0x57,0x14,0x4a,0xac == vfnmsub.vv v8, v20, v4, v0.t
0x57,0x14,0x4a,0xae == vfnmsub.vv v8, v20, v4
0x57,0x54,0x45,0xac == vfnmsub.vf v8, fa0, v4, v0.t
0x57,0x54,0x45,0xae == vfnmsub.vf v8, fa0, v4
0x57,0x14,0x4a,0xf0 == vfwmacc.vv v8, v20, v4, v0.t
0x57,0x14,0x4a,0xf2 == vfwmacc.vv v8, v20, v4
0x57,0x54,0x45,0xf0 == vfwmacc.vf v8, fa0, v4, v0.t
0x57,0x54,0x45,0xf2 == vfwmacc.vf v8, fa0, v4
0x57,0x14,0x4a,0xf4 == vfwnmacc.vv v8, v20, v4, v0.t
0x57,0x14,0x4a,0xf6 == vfwnmacc.vv v8, v20, v4
0x57,0x54,0x45,0xf4 == vfwnmacc.vf v8, fa0, v4, v0.t
0x57,0x54,0x45,0xf6 == vfwnmacc.vf v8, fa0, v4
0x57,0x14,0x4a,0xf8 == vfwmsac.vv v8, v20, v4, v0.t
0x57,0x14,0x4a,0xfa == vfwmsac.vv v8, v20, v4
0x57,0x54,0x45,0xf8 == vfwmsac.vf v8, fa0, v4, v0.t
0x57,0x54,0x45,0xfa == vfwmsac.vf v8, fa0, v4
0x57,0x14,0x4a,0xfc == vfwnmsac.vv v8, v20, v4, v0.t
0x57,0x14,0x4a,0xfe == vfwnmsac.vv v8, v20, v4
0x57,0x54,0x45,0xfc == vfwnmsac.vf v8, fa0, v4, v0.t
0x57,0x54,0x45,0xfe == vfwnmsac.vf v8, fa0, v4
suite/MC/RISCV/fminmax_riscv64_riscv_v_riscv_f.txt.cs
+9
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@@ -0,0 +1,9 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV64"|"CS_MODE_RISCV_V"|"CS_MODE_RISCV_F", None
0x57,0x14,0x4a,0x10 == vfmin.vv v8, v4, v20, v0.t
0x57,0x14,0x4a,0x12 == vfmin.vv v8, v4, v20
0x57,0x54,0x45,0x10 == vfmin.vf v8, v4, fa0, v0.t
0x57,0x54,0x45,0x12 == vfmin.vf v8, v4, fa0
0x57,0x14,0x4a,0x18 == vfmax.vv v8, v4, v20, v0.t
0x57,0x14,0x4a,0x1a == vfmax.vv v8, v4, v20
0x57,0x54,0x45,0x18 == vfmax.vf v8, v4, fa0, v0.t
0x57,0x54,0x45,0x1a == vfmax.vf v8, v4, fa0
suite/MC/RISCV/fmul_riscv64_riscv_v_riscv_f.txt.cs
+9
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@@ -0,0 +1,9 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV64"|"CS_MODE_RISCV_V"|"CS_MODE_RISCV_F", None
0x57,0x14,0x4a,0x90 == vfmul.vv v8, v4, v20, v0.t
0x57,0x14,0x4a,0x92 == vfmul.vv v8, v4, v20
0x57,0x54,0x45,0x90 == vfmul.vf v8, v4, fa0, v0.t
0x57,0x54,0x45,0x92 == vfmul.vf v8, v4, fa0
0x57,0x14,0x4a,0xe0 == vfwmul.vv v8, v4, v20, v0.t
0x57,0x14,0x4a,0xe2 == vfwmul.vv v8, v4, v20
0x57,0x54,0x45,0xe0 == vfwmul.vf v8, v4, fa0, v0.t
0x57,0x54,0x45,0xe2 == vfwmul.vf v8, v4, fa0
suite/MC/RISCV/fmv_riscv64_riscv_v_riscv_f.txt.cs
+4
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@@ -0,0 +1,4 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV64"|"CS_MODE_RISCV_V"|"CS_MODE_RISCV_F", None
0x57,0x54,0x05,0x5e == vfmv.v.f v8, fa0
0x57,0x15,0x40,0x42 == vfmv.f.s fa0, v4
0x57,0x54,0x05,0x42 == vfmv.s.f v8, fa0
suite/MC/RISCV/fothers_riscv64_riscv_v_riscv_f_syntax_no_alias_text.txt.cs
+14
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@@ -0,0 +1,14 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV64"|"CS_MODE_RISCV_V"|"CS_MODE_RISCV_F", None
0x57,0x14,0x40,0x4c == vfsqrt.v v8, v4, v0.t
0x57,0x14,0x40,0x4e == vfsqrt.v v8, v4
0x57,0x14,0x42,0x4c == vfrsqrt7.v v8, v4, v0.t
0x57,0x14,0x42,0x4e == vfrsqrt7.v v8, v4
0x57,0x94,0x42,0x4c == vfrec7.v v8, v4, v0.t
0x57,0x94,0x42,0x4e == vfrec7.v v8, v4
0x57,0x14,0x48,0x4c == vfclass.v v8, v4, v0.t
0x57,0x14,0x48,0x4e == vfclass.v v8, v4
0x57,0x54,0x45,0x5c == vfmerge.vfm v8, v4, fa0, v0
0x57,0x54,0x45,0x38 == vfslide1up.vf v8, v4, fa0, v0.t
0x57,0x54,0x45,0x3a == vfslide1up.vf v8, v4, fa0
0x57,0x54,0x45,0x3c == vfslide1down.vf v8, v4, fa0, v0.t
0x57,0x54,0x45,0x3e == vfslide1down.vf v8, v4, fa0
suite/MC/RISCV/freduction_riscv64_riscv_v_riscv_f_syntax_no_alias_text.txt.cs
+14
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@@ -0,0 +1,14 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV64"|"CS_MODE_RISCV_V"|"CS_MODE_RISCV_F", None
0x57,0x14,0x4a,0x0c == vfredosum.vs v8, v4, v20, v0.t
0x57,0x14,0x4a,0x0e == vfredosum.vs v8, v4, v20
0x57,0x14,0x4a,0x04 == vfredusum.vs v8, v4, v20, v0.t
0x57,0x14,0x4a,0x06 == vfredusum.vs v8, v4, v20
0x57,0x14,0x4a,0x1c == vfredmax.vs v8, v4, v20, v0.t
0x57,0x14,0x4a,0x1e == vfredmax.vs v8, v4, v20
0x57,0x14,0x4a,0x14 == vfredmin.vs v8, v4, v20, v0.t
0x57,0x14,0x4a,0x16 == vfredmin.vs v8, v4, v20
0x57,0x14,0x4a,0xcc == vfwredosum.vs v8, v4, v20, v0.t
0x57,0x14,0x4a,0xce == vfwredosum.vs v8, v4, v20
0x57,0x14,0x4a,0xc4 == vfwredusum.vs v8, v4, v20, v0.t
0x57,0x14,0x4a,0xc6 == vfwredusum.vs v8, v4, v20
0x57,0x10,0x4a,0x0c == vfredosum.vs v0, v4, v20, v0.t
suite/MC/RISCV/fsub_riscv64_riscv_v_riscv_f.txt.cs
+15
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@@ -0,0 +1,15 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV64"|"CS_MODE_RISCV_V"|"CS_MODE_RISCV_F", None
0x57,0x14,0x4a,0x08 == vfsub.vv v8, v4, v20, v0.t
0x57,0x14,0x4a,0x0a == vfsub.vv v8, v4, v20
0x57,0x54,0x45,0x08 == vfsub.vf v8, v4, fa0, v0.t
0x57,0x54,0x45,0x0a == vfsub.vf v8, v4, fa0
0x57,0x54,0x45,0x9c == vfrsub.vf v8, v4, fa0, v0.t
0x57,0x54,0x45,0x9e == vfrsub.vf v8, v4, fa0
0x57,0x14,0x4a,0xc8 == vfwsub.vv v8, v4, v20, v0.t
0x57,0x14,0x4a,0xca == vfwsub.vv v8, v4, v20
0x57,0x54,0x45,0xc8 == vfwsub.vf v8, v4, fa0, v0.t
0x57,0x54,0x45,0xca == vfwsub.vf v8, v4, fa0
0x57,0x14,0x4a,0xd8 == vfwsub.wv v8, v4, v20, v0.t
0x57,0x14,0x4a,0xda == vfwsub.wv v8, v4, v20
0x57,0x54,0x45,0xd8 == vfwsub.wf v8, v4, fa0, v0.t
0x57,0x54,0x45,0xda == vfwsub.wf v8, v4, fa0
suite/MC/RISCV/hypervisor_csr_names_riscv32_syntax_no_alias_text.txt.cs
+75
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@@ -0,0 +1,75 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32", None
0x73,0x23,0x00,0x60 == csrrs t1, hstatus, zero
0xf3,0x23,0x00,0x60 == csrrs t2, hstatus, zero
0x73,0x23,0x20,0x60 == csrrs t1, hedeleg, zero
0xf3,0x23,0x20,0x60 == csrrs t2, hedeleg, zero
0x73,0x23,0x30,0x60 == csrrs t1, hideleg, zero
0xf3,0x23,0x30,0x60 == csrrs t2, hideleg, zero
0x73,0x23,0x40,0x60 == csrrs t1, hie, zero
0xf3,0x23,0x40,0x60 == csrrs t2, hie, zero
0x73,0x23,0x60,0x60 == csrrs t1, hcounteren, zero
0xf3,0x23,0x60,0x60 == csrrs t2, hcounteren, zero
0x73,0x23,0x70,0x60 == csrrs t1, hgeie, zero
0xf3,0x23,0x70,0x60 == csrrs t2, hgeie, zero
0x73,0x23,0x30,0x64 == csrrs t1, htval, zero
0xf3,0x23,0x30,0x64 == csrrs t2, htval, zero
0x73,0x23,0x40,0x64 == csrrs t1, hip, zero
0xf3,0x23,0x40,0x64 == csrrs t2, hip, zero
0x73,0x23,0x50,0x64 == csrrs t1, hvip, zero
0xf3,0x23,0x50,0x64 == csrrs t2, hvip, zero
0x73,0x23,0xa0,0x64 == csrrs t1, htinst, zero
0xf3,0x23,0xa0,0x64 == csrrs t2, htinst, zero
0x73,0x23,0x20,0xe1 == csrrs t1, hgeip, zero
0xf3,0x23,0x20,0xe1 == csrrs t2, hgeip, zero
0x73,0x23,0xa0,0x60 == csrrs t1, henvcfg, zero
0xf3,0x23,0xa0,0x60 == csrrs t2, henvcfg, zero
0x73,0x23,0x00,0x68 == csrrs t1, hgatp, zero
0xf3,0x23,0x00,0x68 == csrrs t2, hgatp, zero
0x73,0x23,0x80,0x6a == csrrs t1, hcontext, zero
0xf3,0x23,0x80,0x6a == csrrs t2, hcontext, zero
0x73,0x23,0x50,0x60 == csrrs t1, htimedelta, zero
0xf3,0x23,0x50,0x60 == csrrs t2, htimedelta, zero
0x73,0x23,0x00,0x20 == csrrs t1, vsstatus, zero
0xf3,0x23,0x00,0x20 == csrrs t2, vsstatus, zero
0x73,0x23,0x40,0x20 == csrrs t1, vsie, zero
0xf3,0x23,0x40,0x20 == csrrs t2, vsie, zero
0x73,0x23,0x50,0x20 == csrrs t1, vstvec, zero
0xf3,0x23,0x50,0x20 == csrrs t2, vstvec, zero
0x73,0x23,0x00,0x24 == csrrs t1, vsscratch, zero
0xf3,0x23,0x00,0x24 == csrrs t2, vsscratch, zero
0x73,0x23,0x10,0x24 == csrrs t1, vsepc, zero
0xf3,0x23,0x10,0x24 == csrrs t2, vsepc, zero
0x73,0x23,0x20,0x24 == csrrs t1, vscause, zero
0xf3,0x23,0x20,0x24 == csrrs t2, vscause, zero
0x73,0x23,0x30,0x24 == csrrs t1, vstval, zero
0xf3,0x23,0x30,0x24 == csrrs t2, vstval, zero
0x73,0x23,0x40,0x24 == csrrs t1, vsip, zero
0xf3,0x23,0x40,0x24 == csrrs t2, vsip, zero
0x73,0x23,0xd0,0x24 == csrrs t1, vstimecmp, zero
0xf3,0x23,0xd0,0x24 == csrrs t2, vstimecmp, zero
0x73,0x23,0x00,0x28 == csrrs t1, vsatp, zero
0xf3,0x23,0x00,0x28 == csrrs t2, vsatp, zero
0x73,0x23,0xc0,0x60 == csrrs t1, hstateen0, zero
0xf3,0x23,0xc0,0x60 == csrrs t2, hstateen0, zero
0x73,0x23,0xd0,0x60 == csrrs t1, hstateen1, zero
0xf3,0x23,0xd0,0x60 == csrrs t2, hstateen1, zero
0x73,0x23,0xe0,0x60 == csrrs t1, hstateen2, zero
0xf3,0x23,0xe0,0x60 == csrrs t2, hstateen2, zero
0x73,0x23,0xf0,0x60 == csrrs t1, hstateen3, zero
0xf3,0x23,0xf0,0x60 == csrrs t2, hstateen3, zero
0x73,0x23,0x80,0x60 == csrrs t1, hvien, zero
0xf3,0x23,0x80,0x60 == csrrs t2, hvien, zero
0x73,0x23,0x90,0x60 == csrrs t1, hvictl, zero
0xf3,0x23,0x90,0x60 == csrrs t2, hvictl, zero
0x73,0x23,0x60,0x64 == csrrs t1, hviprio1, zero
0xf3,0x23,0x60,0x64 == csrrs t2, hviprio1, zero
0x73,0x23,0x70,0x64 == csrrs t1, hviprio2, zero
0xf3,0x23,0x70,0x64 == csrrs t2, hviprio2, zero
0x73,0x23,0x00,0x25 == csrrs t1, vsiselect, zero
0xf3,0x23,0x00,0x25 == csrrs t2, vsiselect, zero
0x73,0x23,0x10,0x25 == csrrs t1, vsireg, zero
0xf3,0x23,0x10,0x25 == csrrs t2, vsireg, zero
0x73,0x23,0xc0,0x25 == csrrs t1, vstopei, zero
0xf3,0x23,0xc0,0x25 == csrrs t2, vstopei, zero
0x73,0x23,0x00,0xeb == csrrs t1, vstopi, zero
0xf3,0x23,0x00,0xeb == csrrs t2, vstopi, zero
suite/MC/RISCV/load_riscv64_riscv_v_syntax_no_alias_text.txt.cs
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# CS_ARCH_RISCV, "CS_MODE_RISCV64"|"CS_MODE_RISCV_V", None
0x07,0x00,0xb5,0x02 == vlm.v v0, (a0)
0x07,0x04,0xb5,0x02 == vlm.v v8, (a0)
0x07,0x04,0x05,0x00 == vle8.v v8, (a0), v0.t
0x07,0x04,0x05,0x02 == vle8.v v8, (a0)
0x07,0x54,0x05,0x00 == vle16.v v8, (a0), v0.t
0x07,0x54,0x05,0x02 == vle16.v v8, (a0)
0x07,0x64,0x05,0x00 == vle32.v v8, (a0), v0.t
0x07,0x64,0x05,0x02 == vle32.v v8, (a0)
0x07,0x74,0x05,0x00 == vle64.v v8, (a0), v0.t
0x07,0x74,0x05,0x02 == vle64.v v8, (a0)
0x07,0x04,0x05,0x01 == vle8ff.v v8, (a0), v0.t
0x07,0x04,0x05,0x03 == vle8ff.v v8, (a0)
0x07,0x54,0x05,0x01 == vle16ff.v v8, (a0), v0.t
0x07,0x54,0x05,0x03 == vle16ff.v v8, (a0)
0x07,0x64,0x05,0x01 == vle32ff.v v8, (a0), v0.t
0x07,0x64,0x05,0x03 == vle32ff.v v8, (a0)
0x07,0x74,0x05,0x01 == vle64ff.v v8, (a0), v0.t
0x07,0x74,0x05,0x03 == vle64ff.v v8, (a0)
0x07,0x04,0xb5,0x08 == vlse8.v v8, (a0), a1, v0.t
0x07,0x04,0xb5,0x0a == vlse8.v v8, (a0), a1
0x07,0x54,0xb5,0x08 == vlse16.v v8, (a0), a1, v0.t
0x07,0x54,0xb5,0x0a == vlse16.v v8, (a0), a1
0x07,0x64,0xb5,0x08 == vlse32.v v8, (a0), a1, v0.t
0x07,0x64,0xb5,0x0a == vlse32.v v8, (a0), a1
0x07,0x74,0xb5,0x08 == vlse64.v v8, (a0), a1, v0.t
0x07,0x74,0xb5,0x0a == vlse64.v v8, (a0), a1
0x07,0x04,0x45,0x04 == vluxei8.v v8, (a0), v4, v0.t
0x07,0x04,0x45,0x06 == vluxei8.v v8, (a0), v4
0x07,0x54,0x45,0x04 == vluxei16.v v8, (a0), v4, v0.t
0x07,0x54,0x45,0x06 == vluxei16.v v8, (a0), v4
0x07,0x64,0x45,0x04 == vluxei32.v v8, (a0), v4, v0.t
0x07,0x64,0x45,0x06 == vluxei32.v v8, (a0), v4
0x07,0x74,0x45,0x04 == vluxei64.v v8, (a0), v4, v0.t
0x07,0x74,0x45,0x06 == vluxei64.v v8, (a0), v4
0x07,0x04,0x45,0x0c == vloxei8.v v8, (a0), v4, v0.t
0x07,0x04,0x45,0x0e == vloxei8.v v8, (a0), v4
0x07,0x54,0x45,0x0c == vloxei16.v v8, (a0), v4, v0.t
0x07,0x54,0x45,0x0e == vloxei16.v v8, (a0), v4
0x07,0x64,0x45,0x0c == vloxei32.v v8, (a0), v4, v0.t
0x07,0x64,0x45,0x0e == vloxei32.v v8, (a0), v4
0x07,0x74,0x45,0x0c == vloxei64.v v8, (a0), v4, v0.t
0x07,0x74,0x45,0x0e == vloxei64.v v8, (a0), v4
0x07,0x04,0x85,0x02 == vl1re8.v v8, (a0)
0x07,0x54,0x85,0x02 == vl1re16.v v8, (a0)
0x07,0x64,0x85,0x02 == vl1re32.v v8, (a0)
0x07,0x74,0x85,0x02 == vl1re64.v v8, (a0)
0x07,0x04,0x85,0x22 == vl2re8.v v8, (a0)
0x07,0x54,0x85,0x22 == vl2re16.v v8, (a0)
0x07,0x64,0x85,0x22 == vl2re32.v v8, (a0)
0x07,0x74,0x85,0x22 == vl2re64.v v8, (a0)
0x07,0x04,0x85,0x62 == vl4re8.v v8, (a0)
0x07,0x54,0x85,0x62 == vl4re16.v v8, (a0)
0x07,0x64,0x85,0x62 == vl4re32.v v8, (a0)
0x07,0x74,0x85,0x62 == vl4re64.v v8, (a0)
0x07,0x04,0x85,0xe2 == vl8re8.v v8, (a0)
0x07,0x54,0x85,0xe2 == vl8re16.v v8, (a0)
0x07,0x64,0x85,0xe2 == vl8re32.v v8, (a0)
0x07,0x74,0x85,0xe2 == vl8re64.v v8, (a0)
suite/MC/RISCV/macc_riscv64_riscv_v.txt.cs
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# CS_ARCH_RISCV, "CS_MODE_RISCV64"|"CS_MODE_RISCV_V", None
0x57,0x24,0x4a,0xb4 == vmacc.vv v8, v20, v4, v0.t
0x57,0x24,0x4a,0xb6 == vmacc.vv v8, v20, v4
0x57,0x64,0x45,0xb4 == vmacc.vx v8, a0, v4, v0.t
0x57,0x64,0x45,0xb6 == vmacc.vx v8, a0, v4
0x57,0x24,0x4a,0xbc == vnmsac.vv v8, v20, v4, v0.t
0x57,0x24,0x4a,0xbe == vnmsac.vv v8, v20, v4
0x57,0x64,0x45,0xbc == vnmsac.vx v8, a0, v4, v0.t
0x57,0x64,0x45,0xbe == vnmsac.vx v8, a0, v4
0x57,0x24,0x4a,0xa4 == vmadd.vv v8, v20, v4, v0.t
0x57,0x24,0x4a,0xa6 == vmadd.vv v8, v20, v4
0x57,0x64,0x45,0xa4 == vmadd.vx v8, a0, v4, v0.t
0x57,0x64,0x45,0xa6 == vmadd.vx v8, a0, v4
0x57,0x24,0x4a,0xac == vnmsub.vv v8, v20, v4, v0.t
0x57,0x24,0x4a,0xae == vnmsub.vv v8, v20, v4
0x57,0x64,0x45,0xac == vnmsub.vx v8, a0, v4, v0.t
0x57,0x64,0x45,0xae == vnmsub.vx v8, a0, v4
0x57,0x24,0x4a,0xf0 == vwmaccu.vv v8, v20, v4, v0.t
0x57,0x24,0x4a,0xf2 == vwmaccu.vv v8, v20, v4
0x57,0x64,0x45,0xf0 == vwmaccu.vx v8, a0, v4, v0.t
0x57,0x64,0x45,0xf2 == vwmaccu.vx v8, a0, v4
0x57,0x24,0x4a,0xf4 == vwmacc.vv v8, v20, v4, v0.t
0x57,0x24,0x4a,0xf6 == vwmacc.vv v8, v20, v4
0x57,0x64,0x45,0xf4 == vwmacc.vx v8, a0, v4, v0.t
0x57,0x64,0x45,0xf6 == vwmacc.vx v8, a0, v4
0x57,0x24,0x4a,0xfc == vwmaccsu.vv v8, v20, v4, v0.t
0x57,0x24,0x4a,0xfe == vwmaccsu.vv v8, v20, v4
0x57,0x64,0x45,0xfc == vwmaccsu.vx v8, a0, v4, v0.t
0x57,0x64,0x45,0xfe == vwmaccsu.vx v8, a0, v4
0x57,0x64,0x45,0xf8 == vwmaccus.vx v8, a0, v4, v0.t
0x57,0x64,0x45,0xfa == vwmaccus.vx v8, a0, v4
suite/MC/RISCV/machine_csr_names_riscv32_syntax_no_alias_text.txt.cs
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# CS_ARCH_RISCV, "CS_MODE_RISCV32", None
0x73,0x23,0x10,0xf1 == csrrs t1, mvendorid, zero
0xf3,0x23,0x10,0xf1 == csrrs t2, mvendorid, zero
0x73,0x23,0x20,0xf1 == csrrs t1, marchid, zero
0xf3,0x23,0x20,0xf1 == csrrs t2, marchid, zero
0x73,0x23,0x30,0xf1 == csrrs t1, mimpid, zero
0xf3,0x23,0x30,0xf1 == csrrs t2, mimpid, zero
0x73,0x23,0x40,0xf1 == csrrs t1, mhartid, zero
0xf3,0x23,0x40,0xf1 == csrrs t2, mhartid, zero
0x73,0x23,0x50,0xf1 == csrrs t1, mconfigptr, zero
0xf3,0x23,0x50,0xf1 == csrrs t2, mconfigptr, zero
0x73,0x23,0x00,0x30 == csrrs t1, mstatus, zero
0xf3,0x23,0x00,0x30 == csrrs t2, mstatus, zero
0x73,0x23,0x10,0x30 == csrrs t1, misa, zero
0xf3,0x23,0x10,0x30 == csrrs t2, misa, zero
0x73,0x23,0x20,0x30 == csrrs t1, medeleg, zero
0xf3,0x23,0x20,0x30 == csrrs t2, medeleg, zero
0x73,0x23,0x30,0x30 == csrrs t1, mideleg, zero
0xf3,0x23,0x30,0x30 == csrrs t2, mideleg, zero
0x73,0x23,0x40,0x30 == csrrs t1, mie, zero
0xf3,0x23,0x40,0x30 == csrrs t2, mie, zero
0x73,0x23,0x50,0x30 == csrrs t1, mtvec, zero
0xf3,0x23,0x50,0x30 == csrrs t2, mtvec, zero
0x73,0x23,0x60,0x30 == csrrs t1, mcounteren, zero
0xf3,0x23,0x60,0x30 == csrrs t2, mcounteren, zero
0x73,0x23,0x00,0x34 == csrrs t1, mscratch, zero
0xf3,0x23,0x00,0x34 == csrrs t2, mscratch, zero
0x73,0x23,0x10,0x34 == csrrs t1, mepc, zero
0xf3,0x23,0x10,0x34 == csrrs t2, mepc, zero
0x73,0x23,0x20,0x34 == csrrs t1, mcause, zero
0xf3,0x23,0x20,0x34 == csrrs t2, mcause, zero
0x73,0x23,0x30,0x34 == csrrs t1, mtval, zero
0xf3,0x23,0x30,0x34 == csrrs t2, mtval, zero
0x73,0x23,0x40,0x34 == csrrs t1, mip, zero
0xf3,0x23,0x40,0x34 == csrrs t2, mip, zero
0x73,0x23,0xa0,0x34 == csrrs t1, mtinst, zero
0xf3,0x23,0xa0,0x34 == csrrs t2, mtinst, zero
0x73,0x23,0xb0,0x34 == csrrs t1, mtval2, zero
0xf3,0x23,0xb0,0x34 == csrrs t2, mtval2, zero
0x73,0x23,0xa0,0x30 == csrrs t1, menvcfg, zero
0xf3,0x23,0xa0,0x30 == csrrs t2, menvcfg, zero
0x73,0x23,0x70,0x74 == csrrs t1, mseccfg, zero
0xf3,0x23,0x70,0x74 == csrrs t2, mseccfg, zero
0x73,0x23,0x00,0x3a == csrrs t1, pmpcfg0, zero
0xf3,0x23,0x00,0x3a == csrrs t2, pmpcfg0, zero
0x73,0x23,0x20,0x3a == csrrs t1, pmpcfg2, zero
0xf3,0x23,0x20,0x3a == csrrs t2, pmpcfg2, zero
0x73,0x23,0x40,0x3a == csrrs t1, pmpcfg4, zero
0xf3,0x23,0x40,0x3a == csrrs t2, pmpcfg4, zero
0x73,0x23,0x60,0x3a == csrrs t1, pmpcfg6, zero
0xf3,0x23,0x60,0x3a == csrrs t2, pmpcfg6, zero
0x73,0x23,0x80,0x3a == csrrs t1, pmpcfg8, zero
0xf3,0x23,0x80,0x3a == csrrs t2, pmpcfg8, zero
0x73,0x23,0xa0,0x3a == csrrs t1, pmpcfg10, zero
0xf3,0x23,0xa0,0x3a == csrrs t2, pmpcfg10, zero
0x73,0x23,0xc0,0x3a == csrrs t1, pmpcfg12, zero
0xf3,0x23,0xc0,0x3a == csrrs t2, pmpcfg12, zero
0x73,0x23,0xe0,0x3a == csrrs t1, pmpcfg14, zero
0xf3,0x23,0xe0,0x3a == csrrs t2, pmpcfg14, zero
0x73,0x23,0x00,0x3b == csrrs t1, pmpaddr0, zero
0xf3,0x23,0x00,0x3b == csrrs t2, pmpaddr0, zero
0x73,0x23,0x10,0x3b == csrrs t1, pmpaddr1, zero
0xf3,0x23,0x10,0x3b == csrrs t2, pmpaddr1, zero
0x73,0x23,0x20,0x3b == csrrs t1, pmpaddr2, zero
0xf3,0x23,0x20,0x3b == csrrs t2, pmpaddr2, zero
0x73,0x23,0x30,0x3b == csrrs t1, pmpaddr3, zero
0xf3,0x23,0x30,0x3b == csrrs t2, pmpaddr3, zero
0x73,0x23,0x40,0x3b == csrrs t1, pmpaddr4, zero
0xf3,0x23,0x40,0x3b == csrrs t2, pmpaddr4, zero
0x73,0x23,0x50,0x3b == csrrs t1, pmpaddr5, zero
0xf3,0x23,0x50,0x3b == csrrs t2, pmpaddr5, zero
0x73,0x23,0x60,0x3b == csrrs t1, pmpaddr6, zero
0xf3,0x23,0x60,0x3b == csrrs t2, pmpaddr6, zero
0x73,0x23,0x70,0x3b == csrrs t1, pmpaddr7, zero
0xf3,0x23,0x70,0x3b == csrrs t2, pmpaddr7, zero
0x73,0x23,0x80,0x3b == csrrs t1, pmpaddr8, zero
0xf3,0x23,0x80,0x3b == csrrs t2, pmpaddr8, zero
0x73,0x23,0x90,0x3b == csrrs t1, pmpaddr9, zero
0xf3,0x23,0x90,0x3b == csrrs t2, pmpaddr9, zero
0x73,0x23,0xa0,0x3b == csrrs t1, pmpaddr10, zero
0xf3,0x23,0xa0,0x3b == csrrs t2, pmpaddr10, zero
0x73,0x23,0xb0,0x3b == csrrs t1, pmpaddr11, zero
0xf3,0x23,0xb0,0x3b == csrrs t2, pmpaddr11, zero
0x73,0x23,0xc0,0x3b == csrrs t1, pmpaddr12, zero
0xf3,0x23,0xc0,0x3b == csrrs t2, pmpaddr12, zero
0x73,0x23,0xd0,0x3b == csrrs t1, pmpaddr13, zero
0xf3,0x23,0xd0,0x3b == csrrs t2, pmpaddr13, zero
0x73,0x23,0xe0,0x3b == csrrs t1, pmpaddr14, zero
0xf3,0x23,0xe0,0x3b == csrrs t2, pmpaddr14, zero
0x73,0x23,0xf0,0x3b == csrrs t1, pmpaddr15, zero
0xf3,0x23,0xf0,0x3b == csrrs t2, pmpaddr15, zero
0x73,0x23,0x00,0x3c == csrrs t1, pmpaddr16, zero
0xf3,0x23,0x00,0x3c == csrrs t2, pmpaddr16, zero
0x73,0x23,0x10,0x3c == csrrs t1, pmpaddr17, zero
0xf3,0x23,0x10,0x3c == csrrs t2, pmpaddr17, zero
0x73,0x23,0x20,0x3c == csrrs t1, pmpaddr18, zero
0xf3,0x23,0x20,0x3c == csrrs t2, pmpaddr18, zero
0x73,0x23,0x30,0x3c == csrrs t1, pmpaddr19, zero
0xf3,0x23,0x30,0x3c == csrrs t2, pmpaddr19, zero
0x73,0x23,0x40,0x3c == csrrs t1, pmpaddr20, zero
0xf3,0x23,0x40,0x3c == csrrs t2, pmpaddr20, zero
0x73,0x23,0x50,0x3c == csrrs t1, pmpaddr21, zero
0xf3,0x23,0x50,0x3c == csrrs t2, pmpaddr21, zero
0x73,0x23,0x60,0x3c == csrrs t1, pmpaddr22, zero
0xf3,0x23,0x60,0x3c == csrrs t2, pmpaddr22, zero
0x73,0x23,0x70,0x3c == csrrs t1, pmpaddr23, zero
0xf3,0x23,0x70,0x3c == csrrs t2, pmpaddr23, zero
0x73,0x23,0x80,0x3c == csrrs t1, pmpaddr24, zero
0xf3,0x23,0x80,0x3c == csrrs t2, pmpaddr24, zero
0x73,0x23,0x90,0x3c == csrrs t1, pmpaddr25, zero
0xf3,0x23,0x90,0x3c == csrrs t2, pmpaddr25, zero
0x73,0x23,0xa0,0x3c == csrrs t1, pmpaddr26, zero
0xf3,0x23,0xa0,0x3c == csrrs t2, pmpaddr26, zero
0x73,0x23,0xb0,0x3c == csrrs t1, pmpaddr27, zero
0xf3,0x23,0xb0,0x3c == csrrs t2, pmpaddr27, zero
0x73,0x23,0xc0,0x3c == csrrs t1, pmpaddr28, zero
0xf3,0x23,0xc0,0x3c == csrrs t2, pmpaddr28, zero
0x73,0x23,0xd0,0x3c == csrrs t1, pmpaddr29, zero
0xf3,0x23,0xd0,0x3c == csrrs t2, pmpaddr29, zero
0x73,0x23,0xe0,0x3c == csrrs t1, pmpaddr30, zero
0xf3,0x23,0xe0,0x3c == csrrs t2, pmpaddr30, zero
0x73,0x23,0xf0,0x3c == csrrs t1, pmpaddr31, zero
0xf3,0x23,0xf0,0x3c == csrrs t2, pmpaddr31, zero
0x73,0x23,0x00,0x3d == csrrs t1, pmpaddr32, zero
0xf3,0x23,0x00,0x3d == csrrs t2, pmpaddr32, zero
0x73,0x23,0x10,0x3d == csrrs t1, pmpaddr33, zero
0xf3,0x23,0x10,0x3d == csrrs t2, pmpaddr33, zero
0x73,0x23,0x20,0x3d == csrrs t1, pmpaddr34, zero
0xf3,0x23,0x20,0x3d == csrrs t2, pmpaddr34, zero
0x73,0x23,0x30,0x3d == csrrs t1, pmpaddr35, zero
0xf3,0x23,0x30,0x3d == csrrs t2, pmpaddr35, zero
0x73,0x23,0x40,0x3d == csrrs t1, pmpaddr36, zero
0xf3,0x23,0x40,0x3d == csrrs t2, pmpaddr36, zero
0x73,0x23,0x50,0x3d == csrrs t1, pmpaddr37, zero
0xf3,0x23,0x50,0x3d == csrrs t2, pmpaddr37, zero
0x73,0x23,0x60,0x3d == csrrs t1, pmpaddr38, zero
0xf3,0x23,0x60,0x3d == csrrs t2, pmpaddr38, zero
0x73,0x23,0x70,0x3d == csrrs t1, pmpaddr39, zero
0xf3,0x23,0x70,0x3d == csrrs t2, pmpaddr39, zero
0x73,0x23,0x80,0x3d == csrrs t1, pmpaddr40, zero
0xf3,0x23,0x80,0x3d == csrrs t2, pmpaddr40, zero
0x73,0x23,0x90,0x3d == csrrs t1, pmpaddr41, zero
0xf3,0x23,0x90,0x3d == csrrs t2, pmpaddr41, zero
0x73,0x23,0xa0,0x3d == csrrs t1, pmpaddr42, zero
0xf3,0x23,0xa0,0x3d == csrrs t2, pmpaddr42, zero
0x73,0x23,0xb0,0x3d == csrrs t1, pmpaddr43, zero
0xf3,0x23,0xb0,0x3d == csrrs t2, pmpaddr43, zero
0x73,0x23,0xc0,0x3d == csrrs t1, pmpaddr44, zero
0xf3,0x23,0xc0,0x3d == csrrs t2, pmpaddr44, zero
0x73,0x23,0xd0,0x3d == csrrs t1, pmpaddr45, zero
0xf3,0x23,0xd0,0x3d == csrrs t2, pmpaddr45, zero
0x73,0x23,0xe0,0x3d == csrrs t1, pmpaddr46, zero
0xf3,0x23,0xe0,0x3d == csrrs t2, pmpaddr46, zero
0x73,0x23,0xf0,0x3d == csrrs t1, pmpaddr47, zero
0xf3,0x23,0xf0,0x3d == csrrs t2, pmpaddr47, zero
0x73,0x23,0x00,0x3e == csrrs t1, pmpaddr48, zero
0xf3,0x23,0x00,0x3e == csrrs t2, pmpaddr48, zero
0x73,0x23,0x10,0x3e == csrrs t1, pmpaddr49, zero
0xf3,0x23,0x10,0x3e == csrrs t2, pmpaddr49, zero
0x73,0x23,0x20,0x3e == csrrs t1, pmpaddr50, zero
0xf3,0x23,0x20,0x3e == csrrs t2, pmpaddr50, zero
0x73,0x23,0x30,0x3e == csrrs t1, pmpaddr51, zero
0xf3,0x23,0x30,0x3e == csrrs t2, pmpaddr51, zero
0x73,0x23,0x40,0x3e == csrrs t1, pmpaddr52, zero
0xf3,0x23,0x40,0x3e == csrrs t2, pmpaddr52, zero
0x73,0x23,0x50,0x3e == csrrs t1, pmpaddr53, zero
0xf3,0x23,0x50,0x3e == csrrs t2, pmpaddr53, zero
0x73,0x23,0x60,0x3e == csrrs t1, pmpaddr54, zero
0xf3,0x23,0x60,0x3e == csrrs t2, pmpaddr54, zero
0x73,0x23,0x70,0x3e == csrrs t1, pmpaddr55, zero
0xf3,0x23,0x70,0x3e == csrrs t2, pmpaddr55, zero
0x73,0x23,0x80,0x3e == csrrs t1, pmpaddr56, zero
0xf3,0x23,0x80,0x3e == csrrs t2, pmpaddr56, zero
0x73,0x23,0x90,0x3e == csrrs t1, pmpaddr57, zero
0xf3,0x23,0x90,0x3e == csrrs t2, pmpaddr57, zero
0x73,0x23,0xa0,0x3e == csrrs t1, pmpaddr58, zero
0xf3,0x23,0xa0,0x3e == csrrs t2, pmpaddr58, zero
0x73,0x23,0xb0,0x3e == csrrs t1, pmpaddr59, zero
0xf3,0x23,0xb0,0x3e == csrrs t2, pmpaddr59, zero
0x73,0x23,0xc0,0x3e == csrrs t1, pmpaddr60, zero
0xf3,0x23,0xc0,0x3e == csrrs t2, pmpaddr60, zero
0x73,0x23,0xd0,0x3e == csrrs t1, pmpaddr61, zero
0xf3,0x23,0xd0,0x3e == csrrs t2, pmpaddr61, zero
0x73,0x23,0xe0,0x3e == csrrs t1, pmpaddr62, zero
0xf3,0x23,0xe0,0x3e == csrrs t2, pmpaddr62, zero
0x73,0x23,0xf0,0x3e == csrrs t1, pmpaddr63, zero
0xf3,0x23,0xf0,0x3e == csrrs t2, pmpaddr63, zero
0x73,0x23,0x00,0xb0 == csrrs t1, mcycle, zero
0xf3,0x23,0x00,0xb0 == csrrs t2, mcycle, zero
0x73,0x23,0x20,0xb0 == csrrs t1, minstret, zero
0xf3,0x23,0x20,0xb0 == csrrs t2, minstret, zero
0x73,0x23,0x00,0x7a == csrrs t1, tselect, zero
0xf3,0x23,0x00,0x7a == csrrs t2, tselect, zero
0x73,0x23,0x10,0x7a == csrrs t1, tdata1, zero
0xf3,0x23,0x10,0x7a == csrrs t2, tdata1, zero
0x73,0x23,0x20,0x7a == csrrs t1, tdata2, zero
0xf3,0x23,0x20,0x7a == csrrs t2, tdata2, zero
0x73,0x23,0x30,0x7a == csrrs t1, tdata3, zero
0xf3,0x23,0x30,0x7a == csrrs t2, tdata3, zero
0x73,0x23,0x80,0x7a == csrrs t1, mcontext, zero
0xf3,0x23,0x80,0x7a == csrrs t2, mcontext, zero
0x73,0x23,0x00,0x7b == csrrs t1, dcsr, zero
0xf3,0x23,0x00,0x7b == csrrs t2, dcsr, zero
0x73,0x23,0x10,0x7b == csrrs t1, dpc, zero
0xf3,0x23,0x10,0x7b == csrrs t2, dpc, zero
0x73,0x23,0x20,0x7b == csrrs t1, dscratch0, zero
0xf3,0x23,0x20,0x7b == csrrs t2, dscratch0, zero
0x73,0x23,0x30,0x7b == csrrs t1, dscratch1, zero
0xf3,0x23,0x30,0x7b == csrrs t2, dscratch1, zero
0x73,0x23,0x30,0xb0 == csrrs t1, mhpmcounter3, zero
0xf3,0x23,0x30,0xb0 == csrrs t2, mhpmcounter3, zero
0x73,0x23,0x40,0xb0 == csrrs t1, mhpmcounter4, zero
0xf3,0x23,0x40,0xb0 == csrrs t2, mhpmcounter4, zero
0x73,0x23,0x50,0xb0 == csrrs t1, mhpmcounter5, zero
0xf3,0x23,0x50,0xb0 == csrrs t2, mhpmcounter5, zero
0x73,0x23,0x60,0xb0 == csrrs t1, mhpmcounter6, zero
0xf3,0x23,0x60,0xb0 == csrrs t2, mhpmcounter6, zero
0x73,0x23,0x70,0xb0 == csrrs t1, mhpmcounter7, zero
0xf3,0x23,0x70,0xb0 == csrrs t2, mhpmcounter7, zero
0x73,0x23,0x80,0xb0 == csrrs t1, mhpmcounter8, zero
0xf3,0x23,0x80,0xb0 == csrrs t2, mhpmcounter8, zero
0x73,0x23,0x90,0xb0 == csrrs t1, mhpmcounter9, zero
0xf3,0x23,0x90,0xb0 == csrrs t2, mhpmcounter9, zero
0x73,0x23,0xa0,0xb0 == csrrs t1, mhpmcounter10, zero
0xf3,0x23,0xa0,0xb0 == csrrs t2, mhpmcounter10, zero
0x73,0x23,0xb0,0xb0 == csrrs t1, mhpmcounter11, zero
0xf3,0x23,0xb0,0xb0 == csrrs t2, mhpmcounter11, zero
0x73,0x23,0xc0,0xb0 == csrrs t1, mhpmcounter12, zero
0xf3,0x23,0xc0,0xb0 == csrrs t2, mhpmcounter12, zero
0x73,0x23,0xd0,0xb0 == csrrs t1, mhpmcounter13, zero
0xf3,0x23,0xd0,0xb0 == csrrs t2, mhpmcounter13, zero
0x73,0x23,0xe0,0xb0 == csrrs t1, mhpmcounter14, zero
0xf3,0x23,0xe0,0xb0 == csrrs t2, mhpmcounter14, zero
0x73,0x23,0xf0,0xb0 == csrrs t1, mhpmcounter15, zero
0xf3,0x23,0xf0,0xb0 == csrrs t2, mhpmcounter15, zero
0x73,0x23,0x00,0xb1 == csrrs t1, mhpmcounter16, zero
0xf3,0x23,0x00,0xb1 == csrrs t2, mhpmcounter16, zero
0x73,0x23,0x10,0xb1 == csrrs t1, mhpmcounter17, zero
0xf3,0x23,0x10,0xb1 == csrrs t2, mhpmcounter17, zero
0x73,0x23,0x20,0xb1 == csrrs t1, mhpmcounter18, zero
0xf3,0x23,0x20,0xb1 == csrrs t2, mhpmcounter18, zero
0x73,0x23,0x30,0xb1 == csrrs t1, mhpmcounter19, zero
0xf3,0x23,0x30,0xb1 == csrrs t2, mhpmcounter19, zero
0x73,0x23,0x40,0xb1 == csrrs t1, mhpmcounter20, zero
0xf3,0x23,0x40,0xb1 == csrrs t2, mhpmcounter20, zero
0x73,0x23,0x50,0xb1 == csrrs t1, mhpmcounter21, zero
0xf3,0x23,0x50,0xb1 == csrrs t2, mhpmcounter21, zero
0x73,0x23,0x60,0xb1 == csrrs t1, mhpmcounter22, zero
0xf3,0x23,0x60,0xb1 == csrrs t2, mhpmcounter22, zero
0x73,0x23,0x70,0xb1 == csrrs t1, mhpmcounter23, zero
0xf3,0x23,0x70,0xb1 == csrrs t2, mhpmcounter23, zero
0x73,0x23,0x80,0xb1 == csrrs t1, mhpmcounter24, zero
0xf3,0x23,0x80,0xb1 == csrrs t2, mhpmcounter24, zero
0x73,0x23,0x90,0xb1 == csrrs t1, mhpmcounter25, zero
0xf3,0x23,0x90,0xb1 == csrrs t2, mhpmcounter25, zero
0x73,0x23,0xa0,0xb1 == csrrs t1, mhpmcounter26, zero
0xf3,0x23,0xa0,0xb1 == csrrs t2, mhpmcounter26, zero
0x73,0x23,0xb0,0xb1 == csrrs t1, mhpmcounter27, zero
0xf3,0x23,0xb0,0xb1 == csrrs t2, mhpmcounter27, zero
0x73,0x23,0xc0,0xb1 == csrrs t1, mhpmcounter28, zero
0xf3,0x23,0xc0,0xb1 == csrrs t2, mhpmcounter28, zero
0x73,0x23,0xd0,0xb1 == csrrs t1, mhpmcounter29, zero
0xf3,0x23,0xd0,0xb1 == csrrs t2, mhpmcounter29, zero
0x73,0x23,0xe0,0xb1 == csrrs t1, mhpmcounter30, zero
0xf3,0x23,0xe0,0xb1 == csrrs t2, mhpmcounter30, zero
0x73,0x23,0xf0,0xb1 == csrrs t1, mhpmcounter31, zero
0xf3,0x23,0xf0,0xb1 == csrrs t2, mhpmcounter31, zero
0x73,0x23,0x00,0x32 == csrrs t1, mcountinhibit, zero
0xf3,0x23,0x00,0x32 == csrrs t2, mcountinhibit, zero
0x73,0x23,0x30,0x32 == csrrs t1, mhpmevent3, zero
0xf3,0x23,0x30,0x32 == csrrs t2, mhpmevent3, zero
0x73,0x23,0x40,0x32 == csrrs t1, mhpmevent4, zero
0xf3,0x23,0x40,0x32 == csrrs t2, mhpmevent4, zero
0x73,0x23,0x50,0x32 == csrrs t1, mhpmevent5, zero
0xf3,0x23,0x50,0x32 == csrrs t2, mhpmevent5, zero
0x73,0x23,0x60,0x32 == csrrs t1, mhpmevent6, zero
0xf3,0x23,0x60,0x32 == csrrs t2, mhpmevent6, zero
0x73,0x23,0x70,0x32 == csrrs t1, mhpmevent7, zero
0xf3,0x23,0x70,0x32 == csrrs t2, mhpmevent7, zero
0x73,0x23,0x80,0x32 == csrrs t1, mhpmevent8, zero
0xf3,0x23,0x80,0x32 == csrrs t2, mhpmevent8, zero
0x73,0x23,0x90,0x32 == csrrs t1, mhpmevent9, zero
0xf3,0x23,0x90,0x32 == csrrs t2, mhpmevent9, zero
0x73,0x23,0xa0,0x32 == csrrs t1, mhpmevent10, zero
0xf3,0x23,0xa0,0x32 == csrrs t2, mhpmevent10, zero
0x73,0x23,0xb0,0x32 == csrrs t1, mhpmevent11, zero
0xf3,0x23,0xb0,0x32 == csrrs t2, mhpmevent11, zero
0x73,0x23,0xc0,0x32 == csrrs t1, mhpmevent12, zero
0xf3,0x23,0xc0,0x32 == csrrs t2, mhpmevent12, zero
0x73,0x23,0xd0,0x32 == csrrs t1, mhpmevent13, zero
0xf3,0x23,0xd0,0x32 == csrrs t2, mhpmevent13, zero
0x73,0x23,0xe0,0x32 == csrrs t1, mhpmevent14, zero
0xf3,0x23,0xe0,0x32 == csrrs t2, mhpmevent14, zero
0x73,0x23,0xf0,0x32 == csrrs t1, mhpmevent15, zero
0xf3,0x23,0xf0,0x32 == csrrs t2, mhpmevent15, zero
0x73,0x23,0x00,0x33 == csrrs t1, mhpmevent16, zero
0xf3,0x23,0x00,0x33 == csrrs t2, mhpmevent16, zero
0x73,0x23,0x10,0x33 == csrrs t1, mhpmevent17, zero
0xf3,0x23,0x10,0x33 == csrrs t2, mhpmevent17, zero
0x73,0x23,0x20,0x33 == csrrs t1, mhpmevent18, zero
0xf3,0x23,0x20,0x33 == csrrs t2, mhpmevent18, zero
0x73,0x23,0x30,0x33 == csrrs t1, mhpmevent19, zero
0xf3,0x23,0x30,0x33 == csrrs t2, mhpmevent19, zero
0x73,0x23,0x40,0x33 == csrrs t1, mhpmevent20, zero
0xf3,0x23,0x40,0x33 == csrrs t2, mhpmevent20, zero
0x73,0x23,0x50,0x33 == csrrs t1, mhpmevent21, zero
0xf3,0x23,0x50,0x33 == csrrs t2, mhpmevent21, zero
0x73,0x23,0x60,0x33 == csrrs t1, mhpmevent22, zero
0xf3,0x23,0x60,0x33 == csrrs t2, mhpmevent22, zero
0x73,0x23,0x70,0x33 == csrrs t1, mhpmevent23, zero
0xf3,0x23,0x70,0x33 == csrrs t2, mhpmevent23, zero
0x73,0x23,0x80,0x33 == csrrs t1, mhpmevent24, zero
0xf3,0x23,0x80,0x33 == csrrs t2, mhpmevent24, zero
0x73,0x23,0x90,0x33 == csrrs t1, mhpmevent25, zero
0xf3,0x23,0x90,0x33 == csrrs t2, mhpmevent25, zero
0x73,0x23,0xa0,0x33 == csrrs t1, mhpmevent26, zero
0xf3,0x23,0xa0,0x33 == csrrs t2, mhpmevent26, zero
0x73,0x23,0xb0,0x33 == csrrs t1, mhpmevent27, zero
0xf3,0x23,0xb0,0x33 == csrrs t2, mhpmevent27, zero
0x73,0x23,0xc0,0x33 == csrrs t1, mhpmevent28, zero
0xf3,0x23,0xc0,0x33 == csrrs t2, mhpmevent28, zero
0x73,0x23,0xd0,0x33 == csrrs t1, mhpmevent29, zero
0xf3,0x23,0xd0,0x33 == csrrs t2, mhpmevent29, zero
0x73,0x23,0xe0,0x33 == csrrs t1, mhpmevent30, zero
0xf3,0x23,0xe0,0x33 == csrrs t2, mhpmevent30, zero
0x73,0x23,0xf0,0x33 == csrrs t1, mhpmevent31, zero
0xf3,0x23,0xf0,0x33 == csrrs t2, mhpmevent31, zero
0x73,0x23,0xc0,0x30 == csrrs t1, mstateen0, zero
0xf3,0x23,0xc0,0x30 == csrrs t2, mstateen0, zero
0x73,0x23,0xd0,0x30 == csrrs t1, mstateen1, zero
0xf3,0x23,0xd0,0x30 == csrrs t2, mstateen1, zero
0x73,0x23,0xe0,0x30 == csrrs t1, mstateen2, zero
0xf3,0x23,0xe0,0x30 == csrrs t2, mstateen2, zero
0x73,0x23,0xf0,0x30 == csrrs t1, mstateen3, zero
0xf3,0x23,0xf0,0x30 == csrrs t2, mstateen3, zero
0x73,0x23,0x00,0x35 == csrrs t1, miselect, zero
0xf3,0x23,0x00,0x35 == csrrs t2, miselect, zero
0x73,0x23,0x10,0x35 == csrrs t1, mireg, zero
0xf3,0x23,0x10,0x35 == csrrs t2, mireg, zero
0x73,0x23,0xc0,0x35 == csrrs t1, mtopei, zero
0xf3,0x23,0xc0,0x35 == csrrs t2, mtopei, zero
0x73,0x23,0x00,0xfb == csrrs t1, mtopi, zero
0xf3,0x23,0x00,0xfb == csrrs t2, mtopi, zero
0x73,0x23,0x80,0x30 == csrrs t1, mvien, zero
0xf3,0x23,0x80,0x30 == csrrs t2, mvien, zero
0x73,0x23,0x90,0x30 == csrrs t1, mvip, zero
0xf3,0x23,0x90,0x30 == csrrs t2, mvip, zero
suite/MC/RISCV/mask_riscv64_riscv_v.txt.cs
+27
View File
@@ -0,0 +1,27 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV64"|"CS_MODE_RISCV_V", None
0x57,0x24,0x4a,0x66 == vmand.mm v8, v4, v20
0x57,0x24,0x4a,0x76 == vmnand.mm v8, v4, v20
0x57,0x24,0x4a,0x62 == vmandn.mm v8, v4, v20
0x57,0x24,0x4a,0x6e == vmxor.mm v8, v4, v20
0x57,0x24,0x4a,0x6a == vmor.mm v8, v4, v20
0x57,0x24,0x4a,0x7a == vmnor.mm v8, v4, v20
0x57,0x24,0x4a,0x72 == vmorn.mm v8, v4, v20
0x57,0x24,0x4a,0x7e == vmxnor.mm v8, v4, v20
0x57,0x26,0x48,0x40 == vcpop.m a2, v4, v0.t
0x57,0x26,0x48,0x42 == vcpop.m a2, v4
0x57,0xa6,0x48,0x40 == vfirst.m a2, v4, v0.t
0x57,0xa6,0x48,0x42 == vfirst.m a2, v4
0x57,0xa4,0x40,0x50 == vmsbf.m v8, v4, v0.t
0x57,0xa4,0x40,0x52 == vmsbf.m v8, v4
0x57,0xa4,0x41,0x50 == vmsif.m v8, v4, v0.t
0x57,0xa4,0x41,0x52 == vmsif.m v8, v4
0x57,0x24,0x41,0x50 == vmsof.m v8, v4, v0.t
0x57,0x24,0x41,0x52 == vmsof.m v8, v4
0x57,0x24,0x48,0x50 == viota.m v8, v4, v0.t
0x57,0x24,0x48,0x52 == viota.m v8, v4
0x57,0xa4,0x08,0x50 == vid.v v8, v0.t
0x57,0xa4,0x08,0x52 == vid.v v8
0x57,0x24,0x42,0x66 == vmmv.m v8, v4
0x57,0x24,0x84,0x6e == vmclr.m v8
0x57,0x24,0x84,0x7e == vmset.m v8
0x57,0x24,0x42,0x76 == vmnot.m v8, v4
suite/MC/RISCV/minmax_riscv64_riscv_v.txt.cs
+17
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@@ -0,0 +1,17 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV64"|"CS_MODE_RISCV_V", None
0x57,0x04,0x4a,0x10 == vminu.vv v8, v4, v20, v0.t
0x57,0x04,0x4a,0x12 == vminu.vv v8, v4, v20
0x57,0x44,0x45,0x10 == vminu.vx v8, v4, a0, v0.t
0x57,0x44,0x45,0x12 == vminu.vx v8, v4, a0
0x57,0x04,0x4a,0x14 == vmin.vv v8, v4, v20, v0.t
0x57,0x04,0x4a,0x16 == vmin.vv v8, v4, v20
0x57,0x44,0x45,0x14 == vmin.vx v8, v4, a0, v0.t
0x57,0x44,0x45,0x16 == vmin.vx v8, v4, a0
0x57,0x04,0x4a,0x18 == vmaxu.vv v8, v4, v20, v0.t
0x57,0x04,0x4a,0x1a == vmaxu.vv v8, v4, v20
0x57,0x44,0x45,0x18 == vmaxu.vx v8, v4, a0, v0.t
0x57,0x44,0x45,0x1a == vmaxu.vx v8, v4, a0
0x57,0x04,0x4a,0x1c == vmax.vv v8, v4, v20, v0.t
0x57,0x04,0x4a,0x1e == vmax.vv v8, v4, v20
0x57,0x44,0x45,0x1c == vmax.vx v8, v4, a0, v0.t
0x57,0x44,0x45,0x1e == vmax.vx v8, v4, a0
suite/MC/RISCV/mul_riscv64_riscv_v.txt.cs
+33
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@@ -0,0 +1,33 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV64"|"CS_MODE_RISCV_V", None
0x57,0x24,0x4a,0x94 == vmul.vv v8, v4, v20, v0.t
0x57,0x24,0x4a,0x96 == vmul.vv v8, v4, v20
0x57,0x64,0x45,0x94 == vmul.vx v8, v4, a0, v0.t
0x57,0x64,0x45,0x96 == vmul.vx v8, v4, a0
0x57,0x24,0x4a,0x9c == vmulh.vv v8, v4, v20, v0.t
0x57,0x24,0x4a,0x9e == vmulh.vv v8, v4, v20
0x57,0x64,0x45,0x9c == vmulh.vx v8, v4, a0, v0.t
0x57,0x64,0x45,0x9e == vmulh.vx v8, v4, a0
0x57,0x24,0x4a,0x90 == vmulhu.vv v8, v4, v20, v0.t
0x57,0x24,0x4a,0x92 == vmulhu.vv v8, v4, v20
0x57,0x64,0x45,0x90 == vmulhu.vx v8, v4, a0, v0.t
0x57,0x64,0x45,0x92 == vmulhu.vx v8, v4, a0
0x57,0x24,0x4a,0x98 == vmulhsu.vv v8, v4, v20, v0.t
0x57,0x24,0x4a,0x9a == vmulhsu.vv v8, v4, v20
0x57,0x64,0x45,0x98 == vmulhsu.vx v8, v4, a0, v0.t
0x57,0x64,0x45,0x9a == vmulhsu.vx v8, v4, a0
0x57,0x24,0x4a,0xec == vwmul.vv v8, v4, v20, v0.t
0x57,0x24,0x4a,0xee == vwmul.vv v8, v4, v20
0x57,0x64,0x45,0xec == vwmul.vx v8, v4, a0, v0.t
0x57,0x64,0x45,0xee == vwmul.vx v8, v4, a0
0x57,0x24,0x4a,0xe0 == vwmulu.vv v8, v4, v20, v0.t
0x57,0x24,0x4a,0xe2 == vwmulu.vv v8, v4, v20
0x57,0x64,0x45,0xe0 == vwmulu.vx v8, v4, a0, v0.t
0x57,0x64,0x45,0xe2 == vwmulu.vx v8, v4, a0
0x57,0x24,0x4a,0xe8 == vwmulsu.vv v8, v4, v20, v0.t
0x57,0x24,0x4a,0xea == vwmulsu.vv v8, v4, v20
0x57,0x64,0x45,0xe8 == vwmulsu.vx v8, v4, a0, v0.t
0x57,0x64,0x45,0xea == vwmulsu.vx v8, v4, a0
0x57,0x04,0x4a,0x9c == vsmul.vv v8, v4, v20, v0.t
0x57,0x04,0x4a,0x9e == vsmul.vv v8, v4, v20
0x57,0x44,0x45,0x9c == vsmul.vx v8, v4, a0, v0.t
0x57,0x44,0x45,0x9e == vsmul.vx v8, v4, a0
suite/MC/RISCV/mv_riscv64_riscv_v.txt.cs
+10
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@@ -0,0 +1,10 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV64"|"CS_MODE_RISCV_V", None
0x57,0x04,0x0a,0x5e == vmv.v.v v8, v20
0x57,0x44,0x05,0x5e == vmv.v.x v8, a0
0x57,0xb4,0x07,0x5e == vmv.v.i v8, 15
0x57,0x26,0x40,0x42 == vmv.x.s a2, v4
0x57,0x64,0x05,0x42 == vmv.s.x v8, a0
0x57,0x34,0x40,0x9e == vmv1r.v v8, v4
0x57,0xb4,0x40,0x9e == vmv2r.v v8, v4
0x57,0xb4,0x41,0x9e == vmv4r.v v8, v4
0x57,0xb4,0x83,0x9f == vmv8r.v v8, v24
suite/MC/RISCV/option_arch_riscv32.txt.cs
+10
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@@ -0,0 +1,10 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32", None
0x13,0x85,0x05,0x00 == mv a0, a1
0x13,0x04,0xc1,0x3f == addi s0, sp, 1020
0x2e,0x85 == mv a0, a1
0xe0,0x1f == addi s0, sp, 1020
0x07,0x20,0xc5,0x00 == flw ft0, 12(a0)
0x33,0x87,0x80,0x02 == mul a4, ra, s0
0xaf,0x22,0x03,0x10 == lr.w t0, (t1)
0xb3,0x22,0x73,0x20 == sh1add t0, t1, t2
0x08,0x61 == flw fa0, 0(a0)
suite/MC/RISCV/option_rvc_riscv32.txt.cs
+5
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@@ -0,0 +1,5 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV32", None
0x13,0x85,0x05,0x00 == mv a0, a1
0x13,0x04,0xc1,0x3f == addi s0, sp, 1020
0x2e,0x85 == mv a0, a1
0xe0,0x1f == addi s0, sp, 1020
suite/MC/RISCV/or_riscv64_riscv_v.txt.cs
+7
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@@ -0,0 +1,7 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV64"|"CS_MODE_RISCV_V", None
0x57,0x04,0x4a,0x28 == vor.vv v8, v4, v20, v0.t
0x57,0x04,0x4a,0x2a == vor.vv v8, v4, v20
0x57,0x44,0x45,0x28 == vor.vx v8, v4, a0, v0.t
0x57,0x44,0x45,0x2a == vor.vx v8, v4, a0
0x57,0xb4,0x47,0x28 == vor.vi v8, v4, 15, v0.t
0x57,0xb4,0x47,0x2a == vor.vi v8, v4, 15
suite/MC/RISCV/others_riscv64_riscv_v_syntax_no_alias_text.txt.cs
+25
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@@ -0,0 +1,25 @@
# CS_ARCH_RISCV, "CS_MODE_RISCV64"|"CS_MODE_RISCV_V", None
0x57,0x04,0x4a,0x5c == vmerge.vvm v8, v4, v20, v0
0x57,0x44,0x45,0x5c == vmerge.vxm v8, v4, a0, v0
0x57,0xb4,0x47,0x5c == vmerge.vim v8, v4, 15, v0
0x57,0x44,0x45,0x38 == vslideup.vx v8, v4, a0, v0.t
0x57,0x44,0x45,0x3a == vslideup.vx v8, v4, a0
0x57,0xb4,0x4f,0x38 == vslideup.vi v8, v4, 31, v0.t
0x57,0xb4,0x4f,0x3a == vslideup.vi v8, v4, 31
0x57,0x44,0x45,0x3c == vslidedown.vx v8, v4, a0, v0.t
0x57,0x44,0x45,0x3e == vslidedown.vx v8, v4, a0
0x57,0xb4,0x4f,0x3c == vslidedown.vi v8, v4, 31, v0.t
0x57,0xb4,0x4f,0x3e == vslidedown.vi v8, v4, 31
0x57,0x64,0x45,0x38 == vslide1up.vx v8, v4, a0, v0.t
0x57,0x64,0x45,0x3a == vslide1up.vx v8, v4, a0
0x57,0x64,0x45,0x3c == vslide1down.vx v8, v4, a0, v0.t
0x57,0x64,0x45,0x3e == vslide1down.vx v8, v4, a0
0x57,0x04,0x4a,0x30 == vrgather.vv v8, v4, v20, v0.t
0x57,0x04,0x4a,0x32 == vrgather.vv v8, v4, v20
0x57,0x44,0x45,0x30 == vrgather.vx v8, v4, a0, v0.t
0x57,0x44,0x45,0x32 == vrgather.vx v8, v4, a0
0x57,0xb4,0x4f,0x30 == vrgather.vi v8, v4, 31, v0.t
0x57,0xb4,0x4f,0x32 == vrgather.vi v8, v4, 31
0x57,0x04,0x4a,0x38 == vrgatherei16.vv v8, v4, v20, v0.t
0x57,0x04,0x4a,0x3a == vrgatherei16.vv v8, v4, v20
0x57,0x24,0x4a,0x5e == vcompress.vm v8, v4, v20

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